CN112217185A - Electrostatic protection circuit and chip - Google Patents

Electrostatic protection circuit and chip Download PDF

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Publication number
CN112217185A
CN112217185A CN201910615957.XA CN201910615957A CN112217185A CN 112217185 A CN112217185 A CN 112217185A CN 201910615957 A CN201910615957 A CN 201910615957A CN 112217185 A CN112217185 A CN 112217185A
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coupled
type transistor
voltage
node
terminal
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许杞安
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present disclosure provides an electrostatic protection circuit, including: the first electrostatic bypass comprises a first P-type transistor, wherein the drain electrode is coupled to a first node, the source electrode is coupled to a first voltage, the grid electrode is connected to a second voltage through a first resistor module, and the first node is electrically connected to the signal input pin; a second electrostatic bypass including a first N-type transistor having a drain coupled to the first node, a source coupled to a second voltage, and a gate connected to the first voltage through a second resistor module; an input buffer circuit, comprising at least a second N-type transistor and a second P-type transistor with gates coupled to a second node; a third N-type transistor coupled to the first node and the second node, and having a control terminal coupled to the third node; the control module is coupled to the first voltage, the second voltage and the third node and used for controlling the third N-type transistor to be turned off when the ESD current is generated. The embodiment of the disclosure can overcome the problem of the protection function failure of the GGNMOS circuit caused by the reduction of the thickness of the gate oxide layer of the MOS tube.

Description

Electrostatic protection circuit and chip
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to an electrostatic protection circuit and a chip using the same.
Background
The design of ESD (Electrostatic Discharge) protection circuits is of great significance to integrated circuit chips. When ESD occurs, transient voltages enter internal circuits through chip Pins (PADs), and transient accumulation of charge can cause damage to devices of the chip internal circuits. The ESD circuit, which is designed beside the PAD and coupled to the PAD, can provide a low-resistance bypass for these transient voltages to enter the power line (VDD or VSS) to protect the internal working circuits of the chip.
The electrostatic protection circuit of GGNMOS (gate-grounded NMOS, N-type MOS tube with grounded grid) is a common electrostatic protection circuit, and a transistor with grounded grid provides a low-resistance bypass for ESD current to prevent the ESD current from breaking down a grid oxide layer of a transistor in an input buffer circuit. In the existing electrostatic protection circuit of GGNMOS, the breakdown voltage of the PN junction of the GGNMOS is smaller than the breakdown voltage of the gate oxide layer of a transistor in an input buffer circuit (buffer), when transient ESD current enters through a chip Pin (PAD), the PN junction of the GGNMOS is instantaneously broken down, and the current is bypassed to a power line, so that the protection purpose is realized.
However, as the process advances, the thickness of the transistor gate oxide layer becomes smaller and smaller, and is already lower than the breakdown voltage of the PN junction, the ESD current can firstly break down the transistor gate oxide of the input buffer circuit, and the existing ESD protection circuit formed by the GGNMOS loses meaning.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to an electrostatic protection circuit for overcoming, at least to some extent, the problem of the GGNMOS electrostatic protection circuit not being able to accommodate the gate oxide thickness reduction brought about by the technological advancement due to the drawbacks of the related art.
According to a first aspect of the present disclosure, there is provided an electrostatic protection circuit including:
the first electrostatic bypass at least comprises a first P-type transistor, wherein the drain electrode of the first P-type transistor is coupled to a first node, the source electrode of the first P-type transistor is coupled to a first voltage, the grid electrode of the first P-type transistor is connected to the first voltage through a first resistor module, and the first node is electrically connected to a signal input pin;
a second electrostatic bypass at least comprising a first N-type transistor, wherein a drain of the first N-type transistor is coupled to the first node, a source of the first N-type transistor is coupled to the second voltage, and a gate of the first N-type transistor is connected to the second voltage through a second resistor module;
an input buffer circuit at least comprising a second N-type transistor and a second P-type transistor, wherein the grid electrode of the second N-type transistor and the grid electrode of the second P-type transistor are coupled to a second node;
a third N-type transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a third node;
a control module, having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and an output terminal coupled to the third node, for controlling the third N-type transistor to turn off when the ESD current is generated;
wherein the first and second resistance modules are configured to provide a resistive function.
In an exemplary embodiment of the present disclosure, the control module includes:
a first capacitor, a first end of which is coupled to the first voltage and a second end of which is coupled to a fourth node;
a third resistor module for providing a resistor function, wherein a first terminal is coupled to the fourth node, and a second terminal is coupled to the second voltage;
a first inverter having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, a third terminal coupled to the fourth node, and a fourth terminal coupled to the third node.
In an exemplary embodiment of the disclosure, the first resistance module is implemented by a first resistor, or the first resistance module is implemented by a third P-type transistor, a drain of the third P-type transistor is coupled to a gate of the first P-type transistor, a source of the second P-type transistor is coupled to the first voltage, and a gate of the second P-type transistor is connected to the second voltage through a second resistor.
In an exemplary embodiment of the disclosure, the second resistor module is implemented by a third resistor, or the second resistor module is implemented by a fourth N-type transistor, a drain of the fourth N-type transistor is coupled to a gate of the first N-type transistor, a source of the second N-type transistor is coupled to the second voltage, and a gate of the second N-type transistor is connected to the first voltage through a fourth resistor.
In an exemplary embodiment of the disclosure, the third resistance module is implemented by a fifth resistance, or the third resistance module is implemented by a fifth N-type transistor, a drain of the fifth N-type transistor is coupled to the fourth node, a source of the fifth N-type transistor is coupled to the second voltage, and a gate of the fifth N-type transistor is coupled to the first voltage through a sixth resistance.
In an exemplary embodiment of the present disclosure, further comprising:
a first diode, the anode of which is coupled to the signal input pin and the cathode of which is coupled to the first voltage;
a second diode having a cathode coupled to the signal input pin and an anode coupled to the first voltage;
and a seventh resistor, a first end of which is coupled to the signal input pin and a second end of which is coupled to the first node.
In an exemplary embodiment of the present disclosure, the input buffer circuit is implemented by a second inverter composed of the second P-type transistor and the second N-type transistor, a first terminal of the second inverter is coupled to the first voltage, a second terminal is coupled to the second voltage, a third terminal is coupled to the second node, and a fourth terminal is coupled to an internal circuit.
In an exemplary embodiment of the disclosure, the input buffer circuit is implemented by a schmitt trigger, the schmitt trigger is composed of a fourth P-type transistor, a second N-type transistor, a sixth N-type transistor, a fifth P-type transistor, and a seventh N-type transistor, a first terminal of the schmitt trigger is coupled to the first voltage, a second terminal of the schmitt trigger is coupled to the second voltage, a third terminal of the schmitt trigger is coupled to the second node, and a fourth terminal of the schmitt trigger is coupled to an internal circuit.
According to an aspect of the present disclosure, there is provided a chip, wherein one or more pins are electrically connected to the electrostatic protection circuit.
According to the electrostatic protection circuit provided by the embodiment of the disclosure, the NMOS with the controlled grid electrode is arranged between the electrostatic protection circuit and the input buffer circuit, so that the difficulty of breaking down the input buffer circuit can be increased on the premise of not influencing the normal work of the circuit, and the problem of ESD protection circuit failure caused by the reduction of the thickness of the gate oxide layer is effectively solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic diagram of an electrostatic protection circuit provided by the present disclosure.
FIG. 2 is a schematic diagram of an electrostatic protection circuit in one embodiment.
Fig. 3A to 3C are schematic diagrams of the implementation circuits of the resistor modules in the three embodiments of the disclosure.
FIG. 4 is a schematic diagram of an input buffer circuit in an embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
Fig. 1 is a schematic diagram of an electrostatic protection circuit 100 provided by the present disclosure.
Referring to fig. 1, the electrostatic protection circuit 100 may include:
a first electrostatic bypass 11, at least including a first P-type transistor MP1, a drain of the first P-type transistor MP1 being coupled to a first node N1, a source thereof being coupled to a first voltage VDD, a gate thereof being connected to a second voltage VSS through a first resistor MR1, the first node N1 being electrically connected to the signal input pin IN;
a second electrostatic bypass 12, at least comprising a first N-type transistor MN1, a drain of the first N-type transistor MN1 being coupled to the first node N1, a source thereof being coupled to the second voltage VSS, a gate thereof being connected to the first voltage VDD through the second resistor MR 2;
an input buffer circuit 13 at least including a second N-type transistor MN2 and a second P-type transistor MP2, a gate of the second N-type transistor MN2 and a gate of the second P-type transistor MP2 being coupled to a second node N2;
a third N-type transistor MN3, having a first terminal coupled to the first node N1, a second terminal coupled to the second node N2, and a control terminal coupled to the third node N3;
a control module 14 having a first terminal coupled to the first voltage VDD, a second terminal coupled to the second voltage VSS, and an output terminal coupled to the third node N3, for controlling the third N-type transistor MN3 to turn off when the ESD current is generated;
the first resistance module MR1 and the second resistance module MR2 are used for providing resistance function. MR1 and MR2 are equivalent to two resistors, and the two resistors have larger resistance values and are used for controlling MP1 and MN1 to be turned off when no ESD current is generated, and MN1 or MP1 is broken down when ESD current is generated, so that a discharge path is provided for the ESD current.
In the prior art, assuming that the gate breakdown voltages of MP2 and MN2 are higher than the PN junction breakdown voltages of MP1 and MN1, when ESD current enters the N1 node, the PN junction of MP1 or MN1 is broken down before the gates of MP2 and MN2, and ESD current is discharged through MP1 or MN 1. However, as the gate oxide thickness is further reduced, the gate breakdown voltages of MP2 and MN2 may be lower than the PN junction breakdown voltages of MP1 and MN1, and the ESD current may directly break down the gates of MP2 and MN2, thereby causing damage to the internal circuit.
IN the embodiment shown IN fig. 1, MN3 is IN a conducting state when no ESD current is generated, and does not affect the signal transmission from the signal input pin IN to the input buffer circuit 13. When ESD current is generated, the control module 14 controls MN3 to turn off, and only when the voltage of the first node N1 is higher than the sum of the PN junction breakdown voltage of MN3 and the gate oxide breakdown voltages of MN2 and MP2, damage may be generated to the gate oxide of MN2 and MP 2. IN one embodiment, MN3 may be a device of the same type as MN1, and has the same PN junction breakdown voltage, so that when the ESD current reaches the signal input pin IN, it is blocked by MN3 being turned off, and it gains time for the ESD current to be discharged through the first electrostatic bypass 11 and the second electrostatic bypass 12, and effectively protects the transistors IN the input buffer circuit 13 before the electrostatic discharge is successful.
After the ESD current is discharged through the first electrostatic bypass 11 and the second electrostatic bypass 12, that is, after the ESD current disappears, the control module 14 controls MN3 to be turned on again, and the input buffer circuit 13 can normally receive the signal input through the signal input pin IN.
Therefore, under the condition that the normal function of the input circuit is not influenced, the embodiment of the disclosure can be applied to the condition that the breakdown voltage of the gate oxide layer of the transistor in the input buffer circuit 13 is smaller than the breakdown voltage of the PN junction, the performance advantage of the GGNMOS electrostatic protection circuit is kept, and the problem that the conventional GGNMOS electrostatic protection circuit cannot adapt to the reduction of the thickness of the gate oxide layer of the novel transistor is solved.
Fig. 2 is a schematic diagram of an electrostatic protection circuit 100 in one embodiment.
Referring to fig. 2, in one embodiment, the electrostatic protection circuit 100 may further include:
a first diode Dp having an anode coupled to the signal input pin IN and a cathode coupled to a first voltage VDD;
a second diode Dn having a cathode coupled to the signal input pin IN and an anode coupled to the first voltage VSS;
a seventh resistor R7 has a first terminal coupled to the signal input pin IN and a second terminal coupled to the first node N1.
Dp and Dn exist as electrostatic bypasses in the basic ESD protection circuit, respectively, and R7 functions to increase the resistance of the signal input path, allowing ESD current to preferentially enter the power line through Dp or Dn. In order to prevent the influence on the normal signal processing, the resistance of R7 is generally small, and a polysilicon (poly) resistor may be used.
The control module 14 may include:
a first capacitor C having a first terminal coupled to the first voltage VDD and a second terminal coupled to the fourth node N4;
a third resistance module MR3 for providing a resistance function, having a first terminal coupled to the fourth node N4 and a second terminal coupled to the second voltage VSS;
the first inverter CV1 has a first terminal coupled to the first voltage VDD, a second terminal coupled to the second voltage VSS, a third terminal coupled to the fourth node N4, and a fourth terminal coupled to the third node N3.
When an ESD positive voltage is generated, an ESD current instantly enters VDD through Dp, the voltage value of VDD is increased, and further the voltage value of the other plate of the capacitor C is increased, the high voltage pulse outputs a low level pulse to the gate of MN3 after passing through the inverter, MN3 is turned off, the path between the signal input pin IN and the input buffer circuit 13 is cut off, so that the electrostatic current is discharged to the power line through the first electrostatic bypass or the second electrostatic bypass, and the ESD protection function is realized.
In an exemplary embodiment of the present disclosure, when no electrostatic current occurs, the voltage value of the fourth node N4 is pulled low to a low level by the third resistor module MR3, and the first inverter CV1 outputs a high level to the gate of the MN3, so that the MN3 is controlled to be turned on, and normal operation of the signal input path is prevented from being affected.
In the embodiment shown in FIG. 1 or FIG. 2, the resistance modules MR 1-MR 3 are used to realize the resistance function and provide the resistance value. In the embodiments of the present disclosure, the above-described resistance module may be implemented in various ways.
Fig. 3A to 3C are schematic diagrams of the implementation circuits of the resistor modules in the three embodiments of the disclosure.
Referring to fig. 3A, the first resistance module MR1 may be implemented by a first resistor R1, the second resistance module MR2 may be implemented by a third resistor R3, and the third resistance module MR3 may be implemented by a fifth resistor R5. In order to protect the transistors and control the transistors MP1 and MN1 to be normally turned off, the resistances of MR1 to MR3 are large, so that the function of the resistor module realized by a single resistor can save cost, but occupies a large design area.
Referring to fig. 3B, in another embodiment, the first resistor module MR1 can be implemented by a third P-type transistor MP3, wherein a drain of MP3 is coupled to a gate of MP1, a source is coupled to the first voltage VDD, and the gate is connected to the second voltage VSS through a second resistor R2.
The second resistance module MR2 can be implemented by a fourth N-type transistor MN4, MN4 having a drain coupled to the gate of MN1, a source coupled to the second voltage VSS, and a gate connected to the first voltage VDD through a fourth resistor R4.
In the embodiment shown in fig. 3, a resistor module with a higher resistance value is realized by using a normally-on MOS transistor instead of a single resistor, so that the area of the device can be effectively saved. The resistance of the PN junction of the conducted MOS transistor is higher, the manufacturing area occupied by the MOS transistor is smaller, and the resistances of R2 and R4 are smaller due to the fact that the MOS transistor is controlled to be normally open, and in some embodiments, the resistance can be achieved by a Poly resistor.
Referring to fig. 3C, the third resistance module MR3 can be implemented by a fifth N-type transistor MN5, MN5 having a drain coupled to a fourth node N4, a source coupled to the second voltage VSS, and a gate coupled to the first voltage VDD through a sixth resistor R6.
In the embodiment shown in fig. 3A to 3C, the input buffer circuit 13 is implemented by a second inverter, which is composed of MP2 and MN2, and has a first terminal coupled to the first voltage VDD, a second terminal coupled to the second voltage VSS, a third terminal coupled to the second node N2, and a fourth terminal OUT coupled to the internal circuit, and outputs the CMOS level signal to the internal circuit.
In other embodiments, the input buffer circuit 13 may also be implemented in other ways.
FIG. 4 is a schematic diagram of an input buffer circuit in an embodiment of the present disclosure.
Referring to fig. 4, the input buffer circuit 13 may be implemented by a schmitt trigger, which is composed of a fourth P-type transistor MP4, a second P-type transistor MP2, a second N-type transistor MN2, a sixth N-type transistor MN6, a fifth P-type transistor MP5, and a seventh N-type transistor MN7 as the input buffer circuit 13, and the schmitt trigger has a first terminal coupled to the first voltage VDD, a second terminal coupled to the second voltage VSS, a third terminal coupled to the second node N2, and a fourth terminal OUT coupled to the internal circuit, and outputs a CMOS level signal to the internal circuit.
According to yet another aspect of the present disclosure, a chip is provided, one or more pins of which are electrically connected to the electrostatic protection circuit as described above. Because the chip comprises the electrostatic protection circuit, the problem that the GGNMOS circuit cannot adapt to the reduction of the thickness of a gate oxide layer can be solved while the advantage of the ESD protection circuit consisting of the GGNMOS is utilized.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (9)

1. An electrostatic protection circuit, comprising:
the first electrostatic bypass at least comprises a first P-type transistor, wherein the drain electrode of the first P-type transistor is coupled to a first node, the source electrode of the first P-type transistor is coupled to a first voltage, the grid electrode of the first P-type transistor is connected to the first voltage through a first resistor module, and the first node is electrically connected to a signal input pin;
a second electrostatic bypass at least comprising a first N-type transistor, wherein a drain of the first N-type transistor is coupled to the first node, a source of the first N-type transistor is coupled to the second voltage, and a gate of the first N-type transistor is connected to the second voltage through a second resistor module;
an input buffer circuit at least comprising a second N-type transistor and a second P-type transistor, wherein the grid electrode of the second N-type transistor and the grid electrode of the second P-type transistor are coupled to a second node;
a third N-type transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a third node;
a control module, having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, and an output terminal coupled to the third node, for controlling the third N-type transistor to turn off when the ESD current is generated;
wherein the first and second resistance modules are configured to provide a resistive function.
2. The electrostatic protection circuit of claim 1, wherein the control module comprises:
a first capacitor, a first end of which is coupled to the first voltage and a second end of which is coupled to a fourth node;
a third resistor module for providing a resistor function, wherein a first terminal is coupled to the fourth node, and a second terminal is coupled to the second voltage;
a first inverter having a first terminal coupled to the first voltage, a second terminal coupled to the second voltage, a third terminal coupled to the fourth node, and a fourth terminal coupled to the third node.
3. The ESD circuit of claim 1, wherein the first resistor module is implemented by a first resistor, or the first resistor module is implemented by a third P-type transistor, a drain of the third P-type transistor is coupled to a gate of the first P-type transistor, a source of the third P-type transistor is coupled to the first voltage, and a gate of the third P-type transistor is connected to the second voltage through a second resistor.
4. The ESD protection circuit of claim 1, wherein the second resistor module is implemented by a third resistor, or the second resistor module is implemented by a fourth N-type transistor, a drain of the fourth N-type transistor is coupled to a gate of the first N-type transistor, a source of the fourth N-type transistor is coupled to the second voltage, and a gate of the fourth N-type transistor is connected to the first voltage through a fourth resistor.
5. The ESD protection circuit of claim 2, wherein the third resistor module is implemented by a fifth resistor, or the third resistor module is implemented by a fifth N-type transistor, wherein a drain of the fifth N-type transistor is coupled to the fourth node, a source of the fifth N-type transistor is coupled to the second voltage, and a gate of the fifth N-type transistor is coupled to the first voltage through a sixth resistor.
6. The electrostatic protection circuit of claim 1, further comprising:
a first diode, the anode of which is coupled to the signal input pin and the cathode of which is coupled to the first voltage;
a cathode of the second diode is coupled to the signal input pin, and an anode of the second diode is coupled to the second voltage;
and a seventh resistor, a first end of which is coupled to the signal input pin and a second end of which is coupled to the first node.
7. The ESD protection circuit of claim 1, wherein the input buffer circuit is implemented by a second inverter, the second inverter is composed of the second P-type transistor and the second N-type transistor, a first terminal of the second inverter is coupled to the first voltage, a second terminal of the second inverter is coupled to the second voltage, a third terminal of the second inverter is coupled to the second node, and a fourth terminal of the second inverter is coupled to an internal circuit.
8. The esd protection circuit of claim 1, wherein the input buffer circuit is implemented by a schmitt trigger, the schmitt trigger is composed of a fourth P-type transistor, the second N-type transistor, a sixth N-type transistor, a fifth P-type transistor, and a seventh N-type transistor, a first terminal of the schmitt trigger is coupled to the first voltage, a second terminal of the schmitt trigger is coupled to the second voltage, a third terminal of the schmitt trigger is coupled to the second node, and a fourth terminal of the schmitt trigger is coupled to an internal circuit.
9. A chip, wherein one or more pins are electrically connected to the ESD protection circuit of any of claims 1-8.
CN201910615957.XA 2019-07-09 2019-07-09 Electrostatic protection circuit and chip Pending CN112217185A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007223A1 (en) * 2022-07-06 2024-01-11 华为技术有限公司 Input/output interface, signal amplifier, and integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024007223A1 (en) * 2022-07-06 2024-01-11 华为技术有限公司 Input/output interface, signal amplifier, and integrated circuit

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