CN107424930A - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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CN107424930A
CN107424930A CN201610344090.5A CN201610344090A CN107424930A CN 107424930 A CN107424930 A CN 107424930A CN 201610344090 A CN201610344090 A CN 201610344090A CN 107424930 A CN107424930 A CN 107424930A
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CN107424930B (zh
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李皞明
林胜豪
江怀慈
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构的制作方法，至少包含:首先，形成四个牺牲图案层于一基底上，接着形成多个间隙壁于该四个牺牲图案层周围，然后移除该四个牺牲图案层，接下来，形成一光致抗蚀剂层于各该间隙壁之间，并且部分覆盖各该间隙壁，接着进行一第一蚀刻步骤，以部分移除各该间隙壁，然后移除该光致抗蚀剂层，以及进行一第二蚀刻步骤，再次部分移除各该间隙壁，以形成四个纳米线掩模。

Description

半导体结构的制作方法
技术领域
本发明涉及半导体制作工艺领域，尤其是涉及一种制作微小尺寸的垂直纳米线结构的方法。
背景技术
近年来，垂直晶体管的结构持续被研究。一垂直晶体管可能包含一柱状的纳米线形成于一半导体基底上，例如形成在一块状半导体基底或是位于一半导体层覆绝缘层(Semiconductor-On-Insulator,SOI))基底上。当柱状的纳米线形成之后，接着可形成栅极结构(包含栅极介电层与栅极电极等)，包覆部分的柱状纳米线，栅极结构与柱状纳米线的交界处，当作垂直晶体管的通道区。此外，另可形成源极区与漏极区，两者分别位于通道区的两端(例如连接柱状纳米线的上端与下端)。具有垂直纳米线的垂直晶体管，也属于栅极全环绕(gate-all-around)的纳米线结构晶体管，具有较高驱动电流、降低短通道效应(short-channel effect)等优点。
发明内容
本发明提供一种半导体结构的制作方法，至少包含:首先，形成四个牺牲图案层于一基底上，接着形成多个间隙壁于该四个牺牲图案层周围，然后移除该四个牺牲图案层，接下来，形成一光致抗蚀剂层于各该间隙壁之间，并且部分覆盖各该间隙壁，接着进行一第一蚀刻步骤，以部分移除各该间隙壁，然后移除该光致抗蚀剂层，以及进行一第二蚀刻步骤，再次部分移除各该间隙壁，以形成四个纳米线掩模。
本发明的特征在于，应用14纳米制作工艺的技术，形成至少四个一组的纳米线结构，其中各纳米线结构的尺寸以及彼此之间的间距都远小于14纳米制作工艺的曝光极值，不需要额外通过更复杂或是较高花费的制作工艺(例如E-beam等)即可有效缩减纳米线的尺寸。
附图说明
图1的上半部绘示四个牺牲图案层形成于一基底上的半导体结构的上视图与剖视图；
图2绘示形成四个间隙壁之后的半导体结构的上视图与剖视图；
图3绘示形成形成一光致抗蚀剂层之后的半导体结构的上视图与剖视图；
图4绘示进行一第一蚀刻步骤之后的半导体结构的上视图与剖视图；
图5绘示进行一第二蚀刻步骤之后的半导体结构的上视图与剖视图；
图6绘示进行一第三蚀刻步骤之后的半导体结构的上视图与剖视图；
图7绘示本发明的纳米线结构的示意图；
图8绘示形成栅极与源/漏极后的半导体结构的剖视图；
图9绘示本发明另外一实施例的半导体结构的示意图。
主要元件符号说明
10 基底
12 掩模层
12’ 掩模层
12A 氧化硅层
12B 氮化硅层
12C 氧化硅层
14 牺牲图案层
14A 图案层组
16 间隙壁
16’ 间隙壁
18 空白区域
20 星形区
22 光致抗蚀剂层
24 纳米线掩模
26 纳米线结构
26’ 纳米线结构
28 垂直晶体管
29 介电层
30 源/漏极区
32 源/漏极区
34 通道区
38 栅极电极层
40 导电层
42 导电层
48 导电层
50 接触结构
52 接触结构
58 接触结构
D1 直径
D2 直径
S1 间距
S2 间距
P1 第一蚀刻步骤
P2 第二蚀刻步骤
P3 第三蚀刻步骤
P4 第四蚀刻步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的较佳实施例，并配合所附附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人皆应能理解其是指物件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围，在此容先叙明。
如图1所示，图1上半部绘示四个牺牲图案层形成于一基底上的半导体结构的上视图，而下半部则绘示沿着剖面线A-A’所得的剖视图。首先，提供一基底10，基底10可能包括一硅基底，或是一绝缘层上覆硅基底(silicon-on-insulator；SOI)等的半导体基底，本实施例中以硅基底为例，但不限于此。接着，在基底10上形成一掩模层12，掩模层12较佳为一多层结构，例如可能包含有一氧化硅层12A、一氮化硅层12B以及一氧化硅层12C，不过不限于此，掩模层12所包含的材料可依实际需求而调整。接下来，形成多个，例如至少四个牺牲图案层14于掩模层12上。值得注意的是，本发明的牺牲图案层14以四个为一组，定义为一图案层组14A。也就是说，一图案层组14A包含有四个牺牲图案层14，上述四个牺牲图案层14同时形成，并且以阵列方式排列，也就是说，此四个牺牲图案层14的中心，分别位于一正方形的四个角落(如图1虚线所示)。当然，本发明的半导体结构可能包含有其他组图案组(图未示)，但其他图案层组也各自包含四个牺牲图案层，且同时形成。
在本发明的其他实施例中，可能一组图案层组包含其他数量的牺牲图案层，例如三个或五个等牺牲图案层。不过本实施例中，一组图案层组包含有四个牺牲图案层，具有图案简单、容易与相邻的其他图案层组互相结合等优点，因此以下仍以一组图案层组包含四个牺牲图案层进行说明。
上述四个牺牲图案层14较佳为圆柱状，且彼此之间具有相同尺寸，可通过一光掩模(图未示)，进行单一或双重光刻步骤而直接形成圆柱状。以目前的14纳米制作工艺可达到的最小曝光极值，各牺牲图案层14可达到的直径D1约为30～35纳米，例如为32纳米。而两牺牲图案层14的间距S1约为48～55纳米，例如为52纳米。上述尺寸范围意味在14纳米的制作工艺之下，若要直接以曝光的方式形成图案，当图案直径或是间距小于上述范围时，非常有可能导致曝光失败。因此上述四个牺牲图案层14的尺寸与间距范围即为14纳米的制作工艺之下，可通过直接曝光显影的制作工艺而达到的最小尺寸与间距范围。
接下来，图2上半部绘示形成四个间隙壁之后的半导体结构的上视图，而下半部则绘示沿着剖面线B-B’所得的剖视图。如图2所示，在各牺牲图案层14周围形成间隙壁16。其中，由于本发明中的牺牲图案层14的材质例如为非晶硅或多晶硅，间隙壁16的材质例如为氮化硅、氮氧化硅或是氮碳化硅，因此氧化硅层12C、牺牲图案层14以及间隙壁16三者较佳具有不同的蚀刻率。此外，因为各牺牲图案层14较佳为圆柱状，因此各间隙壁16呈圆环状结构，且任一间隙壁16的边界与另外两相邻的间隙壁16的边界互相接触且切齐。之后，将牺牲图案层14移除。在此将各圆环状的间隙壁16的中心，也就是原先牺牲图案层14的位置定义为一空白区域18，而被各圆环状的间隙壁16所包围的区域则定义为一星形区20。
图3上半部绘示形成一光致抗蚀剂层之后的半导体结构的上视图，而下半部则绘示沿着剖面线C-C’所得的剖视图。如图3所示，一光致抗蚀剂层22形成于基底10上，覆盖部分的掩模层12以及部分的间隙壁16。较佳而言，光致抗蚀剂层22完整覆盖于星形区20的范围及部分的间隙壁16，但是不覆盖于各空白区域18的范围，但不限于此，本发明的其他实施例中，光致抗蚀剂层22的尺寸可以调整，可能较上述光致抗蚀剂层22的范围更小，因此可能仅部分覆盖星形区20与部分的间隙壁16，或是较上述光致抗蚀剂层22的范围更大，因此覆盖完整的星形区20与覆盖部分的间隙壁16，也更覆盖到部分的空白区域18，上述变化也属于本发明的涵盖范围内。
图4上半部绘示进行一第一蚀刻步骤之后的半导体结构的上视图，而下半部则绘示沿着剖面线D-D’所得的剖视图。如图4所示，进行一第一蚀刻步骤P1，将未被光致抗蚀剂层22覆盖的各间隙壁16部分移除，而没有被移除的间隙壁，也就是被光致抗蚀剂层22覆盖的各间隙壁则定义为间隙壁16’。接下来，将光致抗蚀剂层22移除。
图5上半部绘示进行一第二蚀刻步骤之后的半导体结构的上视图，而下半部则绘示沿着剖面线E-E’所得的剖视图。如图5所示，进行一第二蚀刻步骤P2，较佳为一湿蚀刻步骤，同时蚀刻各间隙壁16’，以形成四个纳米线掩模24较佳为圆柱状。本实施例中，第二蚀刻步骤P2可能包含浸泡于热磷酸内的步骤，更进一步，第二蚀刻步骤P2可能包含多次蚀刻步骤，调整不同蚀刻步骤的蚀刻剂温度、浓度、蚀刻的时间等参数，以控制纳米线掩模24的尺寸。本实施例中，各纳米线掩模24的直径D2约为8-12纳米之间，例如为10纳米，而两纳米线掩模24之间的间距S2约为23-28纳米，例如为26纳米。
图6上半部绘示进行一第三蚀刻步骤之后的半导体结构的上视图，而下半部则绘示沿着剖面线F-F’所得的剖视图。如图6所示，在纳米线掩模24形成之后，进行一第三蚀刻步骤P3，以各纳米线掩模24为保护层，蚀刻掩模层12与基底10，以移除部分的掩模层12(剩余的掩模层定义为掩模层12’)，并将纳米线掩模24的图案转移至基底10中。接下来，如图7所示，图7绘示本发明的纳米线结构的示意图，当掩模层12’被移除后，基底10上所留下的结构定义为纳米线结构26。
值得注意的是，本发明所形成的纳米线结构26是由纳米线掩模24的图案转移至基底10而来，因此纳米线结构26的尺寸应等同于纳米线掩模24的尺寸。也就是说，本发明的纳米线结构26的直径约为8-12纳米，两纳米线结构26之间的间距约为23-28纳米。该尺寸已经远小于14纳米制作工艺下所能达到的最小曝光尺寸。如同上述段落所提及，在14纳米的制作工艺之下，若要直接以曝光的方式形成图案，当图案尺寸或是间距小于特定范围时(例如图案的直径小于30纳米，两图案之间的间距小于48纳米)，将很可能导致曝光失败。而通过本发明提供的方法，可利用14纳米制作工艺的现有技术，轻易形成尺寸、间距都远小于最小曝光极限尺寸的元件。
图8绘示在上述纳米线结构上形成栅极与源/漏极后的半导体结构的剖视图。在后续步骤中，纳米线结构26可用于制作垂直晶体管。如图8所示，垂直晶体管28包含有多个纳米线结构26位于一介电层29中，各纳米线结构26中可通过离子注入或其他如固态扩散(Solid-State-Diffusion，SSD)等方式形成源/漏极区30以及源/漏极区32，分别位于纳米线结构26上端与下端。垂直晶体管28的通道区34即位于源/漏极区30以及源/漏极区32之间，通道区34外侧包含有栅极介电层36以及栅极电极层38。其中，源/漏极区30与一导电层40电连接，且导电层40与一接触结构50电连接；源/漏极区32与一导电层42电连接，且导电层42与一接触结构52电连接；栅极电极层38环绕各纳米线结构26，与一导电层48电连接，且导电层48与一接触结构58电连接。因此垂直晶体管28属于栅极全环绕(gate-all-around)的纳米线结构晶体管，具有较高驱动电流、降低短通道效应(short-channel effect)等优点。上述形成垂直晶体管的栅极与源/漏极的方法，为本领域的人员现有技术，在此不另外赘述。
图9绘示本发明另外一实施例的半导体结构的示意图。如之前段落所述，本发明可以形成一组以上的牺牲图案层，因此依照第一实施例所述的方法，包含依序形成间隙壁、形成光致抗蚀剂层、进行第一蚀刻步骤、第二蚀刻步骤与第三蚀刻步骤后，可以形成一组以上的纳米线结构(各组皆包含有四根纳米线结构)。然而，不同组的牺牲图案层，其彼此之间的元件尺寸可以相异，因此最后可以形成不同尺寸的纳米线结构。或是如图9所示，除了在一第一区域R1内形成上述纳米线结构26之外，本发明可在其他区域，例如一第二区域R2内形成纳米线结构26’，本实施例中可以对特定纳米线结构26’额外进行一第四蚀刻步骤P4，例如包含一氧化步骤以及一蚀刻步骤，或是进行一外延步骤，以缩减或增加纳米线结构26’的尺寸(图9中以缩减纳米线结构26’为例)。因此纳米线结构26与纳米线结构26’的尺寸不相同，后续可用于制作不同的垂直晶体管。
本发明的特征在于，应用14纳米制作工艺的技术，形成至少四个一组的纳米线结构，其中各纳米线结构的尺寸以及彼此之间的间距都远小于14纳米制作工艺的曝光极值，不需要额外通过更复杂或是较高花费的制作工艺(例如E-beam等)即可有效缩减纳米线的尺寸。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种半导体结构的制作方法，至少包含:
形成四个牺牲图案层于一基底上；
形成多个间隙壁于该四个牺牲图案层周围；
移除该四个牺牲图案层；
形成一光致抗蚀剂层于各该间隙壁之间，并且部分覆盖各该间隙壁；
进行一第一蚀刻步骤，以部分移除各该间隙壁；
移除该光致抗蚀剂层；以及
进行一第二蚀刻步骤，再次部分移除各该间隙壁，以形成四个纳米线掩模。
2.如权利要求1所述的制作方法，其中还包含形成一掩模层于该基底与该四个牺牲图案层之间。
3.如权利要求2所述的制作方法，其中该掩模层为多层结构。
4.如权利要求1所述的制作方法，其中该四个牺牲图案层呈阵列排列。
5.如权利要求4所述的制作方法，其中各该牺牲图案层呈圆柱形结构。
6.如权利要求5所述的制作方法，其中各该牺牲图案层的直径介于30-35纳米之间。
7.如权利要求5所述的制作方法，其中一牺牲图案层与另一相邻的牺牲图案层之间的距离介于48-55纳米之间。
8.如权利要求5所述的制作方法，其中该多个间隙壁至少包含有四个圆环状间隙壁。
9.如权利要求8所述的制作方法，其中该四个圆环状间隙壁呈阵列排列，且其中一圆环状间隙壁的边界分别与另外两圆环状间隙壁的边界切齐。
10.如权利要求9所述的制作方法，其中该四个圆环状间隙壁之间包含有一星型区域，且该四个牺牲图案层移除后，形成四个空白区域，位置对应该四个牺牲图案层的位置。
11.如权利要求10所述的制作方法，其中该光致抗蚀剂层完整覆盖该星型区域。
12.如权利要求10所述的制作方法，其中该光致抗蚀剂层不覆盖该四个空白区域。
13.如权利要求1所述的制作方法，其中该四个纳米线掩模呈圆柱状，且各纳米线掩模的直径介于8-12纳米。
14.如权利要求13所述的制作方法，其中一纳米线掩模与其相邻的另一纳米线掩模之间的距离介于23-28纳米之间。
15.如权利要求1所述的制作方法，其中该第二蚀刻步骤还包含多次蚀刻步骤。
16.如权利要求1所述的制作方法，其中还包含进行一第三蚀刻步骤，将各纳米线掩模的图案转换至该基底中，以形成多个纳米线结构。
17.如权利要求16所述的制作方法，其中在该纳米线结构完成后，还包含进行一第四蚀刻步骤，以部分移除该纳米线结构。
18.如权利要求16所述的制作方法，其中还包含形成至少一源极结构以及至少一漏极结构，连接该多个纳米线结构。
19.如权利要求16所述的制作方法，其中还包含形成至少一栅极结构，连接该多个纳米线结构。
20.如权利要求16所述的制作方法，还包含形成多个第二纳米线结构，且该多个第二纳米线结构的直径与该多个纳米线结构的直径不同。
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CN109494249B (zh) * 2017-09-11 2022-05-24 联华电子股份有限公司 半导体元件及其制造方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090317748A1 (en) * 2008-06-19 2009-12-24 Hynix Semiconductor Inc. Method for Forming Fine Patterns of Semiconductor Device
US20150348796A1 (en) * 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Nano Wire Structure and Method for Fabricating the Same
US20150348848A1 (en) * 2014-05-28 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US20160099328A1 (en) * 2014-10-03 2016-04-07 Taiwan Semiconductor Manufacturing Company Limited Method of forming nanowires
CN105590845A (zh) * 2015-12-25 2016-05-18 中国科学院微电子研究所 堆叠围栅纳米线制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667237B1 (en) * 2000-10-12 2003-12-23 Vram Technologies, Llc Method and apparatus for patterning fine dimensions
WO2008157068A2 (en) * 2007-06-15 2008-12-24 Applied Materials, Inc. Oxygen sacvd to form sacrificial oxide liners in substrate gaps
US7737039B2 (en) * 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7972926B2 (en) * 2009-07-02 2011-07-05 Micron Technology, Inc. Methods of forming memory cells; and methods of forming vertical structures
KR101150639B1 (ko) * 2010-06-17 2012-07-03 에스케이하이닉스 주식회사 반도체 소자의 패턴 형성 방법
KR101710159B1 (ko) * 2010-09-14 2017-03-08 삼성전자주식회사 Ⅲ족 질화물 나노로드 발광소자 및 그 제조 방법
JPWO2015015694A1 (ja) * 2013-08-01 2017-03-02 パナソニック株式会社 光起電力装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090317748A1 (en) * 2008-06-19 2009-12-24 Hynix Semiconductor Inc. Method for Forming Fine Patterns of Semiconductor Device
US20150348848A1 (en) * 2014-05-28 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US20150348796A1 (en) * 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Nano Wire Structure and Method for Fabricating the Same
US20160099328A1 (en) * 2014-10-03 2016-04-07 Taiwan Semiconductor Manufacturing Company Limited Method of forming nanowires
CN105590845A (zh) * 2015-12-25 2016-05-18 中国科学院微电子研究所 堆叠围栅纳米线制造方法

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