CN107393970A - 一种碳化硅结势垒二极管 - Google Patents
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- 230000004913 activation Effects 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract description 2
- 229910052799 carbon Inorganic materials 0.000 abstract description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 21
- 238000005516 engineering process Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
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- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
本发明公开了一种碳化硅结势垒二极管，将沟槽结构引入4H‑SiC结势垒二极管中，有效的提高4H‑SiC场控二极管的耐压性，改善了高压4H‑SiC结势垒二极管的阻断性能；本发明二极管使用外延形成用于阳极接触的重掺杂接触区，通过刻蚀技术在重掺杂接触区与沟道扩展区制作沟槽的方法，以及离子注入后无碳膜保护的激活退火方法，均有效增加了p结区结深，并改善了欧姆接触阳极的接触特性，降低了器件工艺的复杂度，提高了器件的可行性。
Description
技术领域
本发明属于电力半导体器件技术领域，具体涉及一种碳化硅结势垒二极管。
背景技术
碳化硅(SiC)材料具有禁带宽度大，热导率高，临界雪崩击穿电场强度高，饱和载流子漂移速度大及热稳定性好等特点，是制造功率半导体器件的理想材料。SiC高压器件与同等级的硅器件相比，具有更低的通态压降、更高的工作频率、更低的功耗、更小的体积以及更好的热特性，更适合应用于电力电子电路。
SiC功率肖特基二极管(SBD)作为最早实现商品化的SiC功率器件，兼具了通态压降低与反向恢复时间几乎为零的优势，适合作为续流二极管与Si基IGBT等开关器件组成混合Si-SiC电力电子电路，降低开关损耗。随应用电路电压的提高，耐压性能良好的SiC结势垒肖特基二极管(JBS)成为主流。由于通态时器件中无电导调制，SiC JBS二极管保持了良好的反向恢复特性，但这也使耐压较高的SiC JBS二极管难以获得高的电流密度，不利于降低器件的通态损耗。
硅基混合pn-肖特基势垒(MPS)二极管可以通过调节额外载流子的注入率，使器件的压降与反向恢复时间得到较好的兼顾。但SiC pn结的门槛电压明显高于SiC MPS二极管所使用的肖特基势垒，电导调制效应只能在器件遭受浪涌冲击时起作用，工作于通态时SiCMPS二极管与SiC JBS二极管并无二致。
2013年苗东铭在其学位论文《新型SiC二极管的结构优化及其制造工艺流程设计》中，提出并研究了一种新型SiC二极管结构，改JBS阳极处的肖特基接触为欧姆接触，取消了肖特基势垒对器件正向压降的制约，通过调整p区与导电沟道的宽度，增加沟道区掺杂浓度，获得了具有低通态压降的1200V SiC二极管。同年，Chaofeng Cai等在所发表文章《Silicon Carbide Pinched Barrier Rectifier(PBR)》中提出类似的1200V SiC二极管结构，将1200V SiC JBS二极管的肖特基势垒降为零，有效降低了SiC JBS二极管的通态损耗，改善了SiC JBS二极管的高温性能。但由于SiC高温离子注入技术注入结深较浅、高精度光刻技术成本昂贵以及在沟槽中外延生长技术不够成熟的限制，文中所提出的SiC结势垒二极管结构难以适用于更高的电压等级。
发明内容
本发明的目的是提供一种碳化硅结势垒二极管，解决了现有器件结构难以适用于高电压领域的问题。
本发明所采用的技术方案是，一种碳化硅结势垒二极管，包括衬底，衬底一面自下而上依次设置有缓冲层、漂移区、沟道扩展区，沟道扩展区分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区，沟道区最高面连接有高掺杂接触区，终端台面包括多个场限环，P结区、高掺杂接触区外连接欧姆接触阳极，终端台面上连接有钝化层，衬底另一面连接欧姆接触阴极。
本发明的特点还在于：
缓冲层掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.5μm—2.0μm，漂移区掺杂浓度为2×1014cm-3—2×1016cm-3，厚度为5μm—80μm，高掺杂接触区掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.1μm—0.3μm，沟道扩展区掺杂浓度为2×1016cm-3—2×1017cm-3，厚度为1.1μm—2.1μm。
P结区掺杂浓度为1×1018cm-3—5×1019cm-3，结深为0.5μm—0.8μm。
衬底为n型4H-SiC衬底。
钝化层为SiO2层。
本发明的有益效果是：
(1)本发明的一种碳化硅结势垒二极管，将沟槽结构引入4H-SiC结势垒二极管中，有效的提高4H-SiC场控二极管的耐压性，改善了高压4H-SiC结势垒二极管的阻断性能；
(2)本发明的碳化硅结势垒二极管采用欧姆接触阳极配合使用缓冲层、重掺杂接触区、沟道扩展区、漂移区、P结区以及特定的掺杂浓度、厚度、结深，有效的改善了欧姆接触阳极的接触特性，提高了器件的可行性。
附图说明
图1是本发明一种碳化硅结势垒二极管结构示意图；
图2是本发明一种碳化硅结势垒二极管在3300V电压情况下正向导通特性数值仿真结果；
图3是本发明一种碳化硅结势垒二极管在3300V电压情况下反向阻断特性数值仿真结果。
图中，1.衬底，2.缓冲层，3.漂移区，4.沟道扩展区，5.高掺杂接触区，6.P结区，7.欧姆接触阳极，8.欧姆接触阴极，9.场限环，10.钝化层。
具体实施方式
下面结合附图和具体实施方式对本发明进行详细说明。
本发明一种碳化硅结势垒二极管，如图1所示，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，且终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，且钝化层10为SiO2层；衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.5μm—2.0μm，漂移区3掺杂浓度为2×1014cm-3—2×1016cm-3，厚度为5μm—80μm，高掺杂接触区5掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.1μm—0.3μm，沟道扩展区4掺杂浓度为2×1016cm-3—2×1017cm-3，厚度为1.1μm—2.1μm。
P结区掺杂浓度为1×1018cm-3—5×1019cm-3，结深为0.5μm—0.8μm。
实施例1
一种碳化硅结势垒二极管，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，钝化层10为SiO2层，衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为1×1018cm-3，厚度为0.5μm，漂移区3掺杂浓度为2×1014cm-3，厚度为5μm，高掺杂接触区5掺杂浓度为1×1018cm-3，厚度为0.1μm，沟道扩展区4掺杂浓度为2×1016cm-3，厚度为1.1μm。
P结区掺杂浓度为1×1018cm-3，结深为0.5μm。
实施例2
一种碳化硅结势垒二极管，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，钝化层10为SiO2层，衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为2×1018cm-3，厚度为1.0μm，漂移区3掺杂浓度为5×1015cm-3，厚度为21.2μm，高掺杂接触区5掺杂浓度为2×1018cm-3，厚度为0.15μm，沟道扩展区4掺杂浓度为6.5×1016cm-3，厚度为1.3μm。
P结区掺杂浓度为1.2×1019cm-3，结深为0.65μm。
实施例3
一种碳化硅结势垒二极管，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，钝化层10为SiO2层，衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为2.5×1019cm-3，厚度为1.2μm，漂移区3掺杂浓度为1×1016cm-3，厚度为42.5μm，高掺杂接触区5掺杂浓度为2.5×1019cm-3，厚度为0.2μm，沟道扩展区4掺杂浓度为1×1017cm-3，厚度为1.6μm。
P结区掺杂浓度为2.5×1019cm-3，结深为0.65μm。
实施例4
一种碳化硅结势垒二极管，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，钝化层10为SiO2层，衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为4.5×1019cm-3，厚度为1.8μm，漂移区3掺杂浓度为1×1016cm-3，厚度为63μm，高掺杂接触区5掺杂浓度为3.7×1019cm-3，厚度为0.25μm，沟道扩展区4掺杂浓度为1.65×1017cm-3，厚度为1.8μm。
P结区掺杂浓度为3.7×1019cm-3，结深为0.72μm。
实施例5
一种碳化硅结势垒二极管，包括衬底1，衬底1为n型4H-SiC衬底，衬底1一面自下而上依次设置有缓冲层2、漂移区3、沟道扩展区4，沟道扩展区4分为沟道区和终端台面，终端台面低于沟道区最高面，沟道区开设多个矩形的阳极沟槽，每个阳极沟槽的侧壁和底端均连接P结区6，沟道区最高面连接有高掺杂接触区5，终端台面包括多个场限环9，P结区6、高掺杂接触区5外连接欧姆接触阳极7，终端台面上连接有钝化层10，钝化层10为SiO2层，衬底1另一面连接欧姆接触阴极8。
缓冲层2掺杂浓度为5×1019cm-3，厚度为2.0μm，漂移区3掺杂浓度为2×1016cm-3，厚度为80μm，高掺杂接触区5掺杂浓度为5×1019cm-3，厚度为0.3μm，沟道扩展区4掺杂浓度为2×1017cm-3，厚度为2.1μm。
P结区掺杂浓度为5×1019cm-3，结深为0.8μm。
为了说明本发明4H-SiC结势垒二极管的性能，通过以下数值仿真进行证明。
使用Silvaco TCAD计算机仿真软件对上述实施例3的结势垒二极管进行了数值仿真，仿真中采用的结构为本发明4H-SiC结势垒二极管的元胞。经数值仿真，上述4H-SiC结势垒二极管的正向特性曲线如图2所示，反向特性曲线如图3所示，可见本发明4H-SiC结势垒二极管的门槛电压小于0.3V，正向压降为1.51V，击穿电压大于4000V，在阻断电压为3300V时，器件的漏电流密度低于0.5μA/cm2。相比于相同电压等级的4H-SiC JBS二极管，通态性能得到明显提升。
通过上述方式，本发明一种碳化硅结势垒二极管，有效的提高4H-SiC场控二极管的耐压性，改善了高压4H-SiC结势垒二极管的阻断性能；本发明二极管使用外延形成用于阳极接触的重掺杂接触区，通过刻蚀技术在重掺杂接触区与沟道扩展区制作沟槽的方法，以及离子注入后无碳膜保护的激活退火方法，均有效增加了p结区结深，并改善了欧姆接触阳极的接触特性，降低了器件工艺的复杂度，提高了器件的可行性。
Claims (5)
1.一种碳化硅结势垒二极管，其特征在于，包括衬底(1)，所述衬底(1)一面自下而上依次设置有缓冲层(2)、漂移区(3)、沟道扩展区(4)，所述沟道扩展区(4)分为沟道区和终端台面，所述终端台面低于沟道区最高面，所述沟道区开设多个矩形的阳极沟槽，每个所述阳极沟槽的侧壁和底端均连接P结区(6)，所述沟道区最高面连接有高掺杂接触区(5)，所述终端台面包括多个场限环(9)，所述P结区(6)、高掺杂接触区(5)外连接欧姆接触阳极(7)，所述终端台面上连接有钝化层(10)，所述衬底(1)另一面连接欧姆接触阴极(8)。
2.根据权利要求1所述的一种碳化硅结势垒二极管，其特征在于，所述缓冲层(2)掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.5μm—2.0μm；所述漂移区(3)掺杂浓度为2×1014cm-3—2×1016cm-3，厚度为5μm—80μm；所述高掺杂接触区(5)掺杂浓度为1×1018cm-3—5×1019cm-3，厚度为0.1μm—0.3μm；所述沟道扩展区(4)掺杂浓度为2×1016cm-3—2×1017cm-3，厚度为1.1μm—2.1μm。
3.根据权利要求1所述的一种碳化硅结势垒二极管，其特征在于，所述P结区掺杂浓度为1×1018cm-3—5×1019cm-3，结深为0.5μm—0.8μm。
4.根据权利要求1所述的一种碳化硅结势垒二极管，其特征在于，所述衬底(1)为n型4H-SiC衬底。
5.根据权利要求1所述的一种碳化硅结势垒二极管，其特征在于，所述钝化层(10)为SiO2层。
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