CN107390769B - A kind of high-order curvature correction reference voltage source - Google Patents
A kind of high-order curvature correction reference voltage source Download PDFInfo
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- CN107390769B CN107390769B CN201710711170.4A CN201710711170A CN107390769B CN 107390769 B CN107390769 B CN 107390769B CN 201710711170 A CN201710711170 A CN 201710711170A CN 107390769 B CN107390769 B CN 107390769B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to arrive a kind of high-order curvature correction reference voltage source.The present invention shunts PTAT current using simple shunt circuit, to generate a CTAT current, simplifies CTAT current generation circuit, reduces chip area and design difficulty；It introduces a new positive temperature voltage to pre-compensate for threshold voltage, weakens the demand to the compensation ability of rear class compensation circuit, ensure that two PMOS tube are all operated in normal saturation state；And segmented current curvature correction technology is utilized, obtain the output reference voltage of a high-order curvature correction.In addition, resistance and amplifier is not used in the reference voltage source of the present invention, the chip area of entire reference circuit and the complexity of design are effectively reduced.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to arrive a kind of high-order curvature correction reference voltage source.
Background technology
Reference voltage source provides one precisely as one of the nucleus module in analog circuitry system, for analog circuitry system
Reference voltage, be widely used in the simulations such as analog-digital converter, power amplifier, data collector and mixed analog digital system
In, the reference voltage not varied with temperature is provided for system.
Due to bipolar transistor base-emitter voltage VBEWith negative temperature characteristic, and it is operated under different current densities
Two bipolar transistors base emitter voltage VBEDifference there is positive temperature characterisitic, proposed by Widlar and Brokaw
Traditional bandgap voltage reference is mutually compensated for using both voltages, to obtain a temperature independent benchmark electricity
Pressure.
Traditional bandgap reference voltage source utilizes the bandgap voltage reference same principle with Widlar and Brokaw, such as attached drawing
Shown in 1, wherein operational amplifier makes circuit be in negative-feedback state, clamps down on X points and Y point voltages, keeps 2 voltages equal, and three
Pole pipe is parasitic vertical bipolar transistors (BJT).PMOS tube size is identical, and the current mirror mirror image being made of them obtains three
Identical currents.Reference output voltage is obtained according to bipolar transistor current voltage characteristic：
However due to VBEIt is non-linear, and only carry out first compensation phase, the reference voltage that traditional bandgap reference voltage source generates
Temperature coefficient it is larger.And traditional bandgap voltage reference is needed using amplifier clamper X and 2 current potentials of Y, the work(of amplifier
Consumption occupies the half of entire band-gap reference power consumption and chip area with the big appointment of chip area.Meanwhile traditional band-gap reference electricity
Potential source needs to use resistance, this can also greatly increase entire bandgap voltage reference area.
Due to the reference voltage that the reference voltage source of traditional first compensation phase exports vary with temperature it is larger, and in practical fortune
In, one is needed to vary with temperature smaller reference voltage in many cases, therefore, the reference voltage source of high-order curvature correction
With strong current demand.
The existing segmented current curvature correction technology (high-order curvature correction technology) that reference voltage source is related to is must to use
Complicated circuit generates two electric currents respectively --- with absolute temperature is proportional to (PTAT：proportional to absolute
Temperature it electric current) and is inversely proportional (CTAT with absolute temperature：cognitive to absolute
Temperature electric current)；And current mirror mirror is utilized, low-temperature zone is generated respectively and high temperature section compensates electric current, compensation
Electric current adjusts output reference voltage respectively in low-temperature zone and high temperature section, to obtain the reference voltage of a high-order compensation.It should
The principle that technology generates CTAT current is to utilize transistor base-emitter voltage VBE(subzero temperature voltage) is made with amplifier clamper
With, make resistance both end voltage be equal to VBE, to obtain CTAT current.But this scheme for obtaining CTAT current needs individually
CTAT current generation circuit can occupy a large amount of circuit layout area.
Invention content
For above-mentioned there are problem or deficiency, in order to overcome segmented current curvature correction technology to generate CTAT current circuit mistake
In complexity, the present invention provides a kind of high-order curvature correction reference voltage sources.
The high-order curvature correction reference voltage source, including starting module 201, positive temperature current generating module 202, diverter module
203, VTHPre-compensate for module 204, high temperature electric current compensating module 205, low-temperature current compensating module 206 and voltage superposition module 207.
The starting module 201 is by PMOS tube MSP1, NMOS tube MSN1~MSN2 compositions；The source electrode and substrate of MSP1 and electricity
Source voltage AVDD is connected, and the drain electrode of MSP1 and MSN2 are connected with the grid of MSN1, and the grid of MSP1 and MSN2 are produced with positive warm electric current
The VQ nodes of raw module 202 are connected, and the drain electrode of MSN1 is connected with the VBP nodes of positive warm current generating module 202, MSN1 and MSN2
Source electrode and substrate be connected with ground potential AGND；Starting module 201 is for making entire reference circuit break away from the biasing of " 0 " degeneracy
Point；As shown in Fig. 3.
The positive temperature current generating module 202 by PMOS tube MAP1~MAP5, MP1~MP6, NMOS tube MAN1~MAN5,
MN1~MN7, MNC and PNP pipe Q1~Q3, QB composition.
The source electrode of MAP1, MAP2, MAP3, MAP4, MP1, MP2, MP5 are connected with supply voltage AVDD, MAP1~MAP5 and
The substrate of MP1~MP6 is connected with supply voltage AVDD, the grid of MAP1, MP1, MP2 and MP5 and the drain electrode of MP6 and MN6 and
VBP nodes be connected, the drain electrode of MAP1 and MAN1 are connected with the grid of MAN1, MAN2 and MAN3, the grid of MAP2 and MAP3 and
MAP2 is connected with the drain electrode of MAN2, and the drain electrode of MAP3 and MAN4 are saved with the grid of MAN4, MAN5, MN1, MN2 and MN6 and VBN
Point is connected, and the grid of MAP4, MAP5, MP3, MP4 and MP6 are connected with the drain electrode of MAP5 and MAN3 and VBP_C nodes, MAP4's
Drain electrode is connected with the source electrode of MAP5, and the drain electrode of MP1 is connected with the source electrode of MP3, and the drain electrode of MP2 is connected with the source electrode of MP4, MP5's
Drain electrode is connected with the source electrode of MP6, and the drain electrode of MP3 and MN1 are connected with the grid of MN7 and MNC and VQ nodes, the leakage of MP4 and MN2
Pole is connected with the grid of MN3, MN4 and MN5 and VBN_C nodes.
The collector and base stage of QB, Q1, Q2 and Q3 are connected with ground potential AGND, the source electrode of MAN1, MAN2 and MAN3 with
Ground potential AGND is connected, and the source electrode of MAN4 is connected with the drain electrode of MAN5, and the source electrode of MAN5 is connected with the emitter of QB, the source of MN1
Pole is connected with the drain electrode of MN3, and the source electrode of MN2 is connected with the drain electrode of MN4, and the source electrode of MN3 is connected with the emitter of Q2, the source of MN4
Pole is connected with the drain electrode of MN5, and the source electrode of MN5 is connected with the emitter of Q1, and the source electrode of MN6 is connected with the drain electrode of MN7, the source of MN7
Pole is connected with the emitter of Q3, and the drain electrode of MNC and source electrode and substrate are connected with ground potential AGND, and MN1~MN7 and MAN1~
The substrate of MAN5 is connected with ground potential AGND；Positive temperature current generating module 202 is for generating a PTAT current, the PTAT current
With μnT2It is directly proportional, wherein μnIt is electron mobility, T is absolute temperature；As shown in Fig. 3.
The diverter module 203 is by PMOS tube MP15, MP16, MPR, NMOS tube MNR compositions；The source electrode of MP15 and power supply electricity
AVDD is pressed to be connected, the grid of MP15 is connected with the VBP nodes in positive warm current generating module 202, and the drain electrode of MP15 is with MP16's
Source electrode is connected, and the grid of MP16 is connected with the VBP_C nodes in positive temperature current generating module 202, the drain electrode of MP16 and MNR and
The source electrode of MPR, the grid of MNR and VM nodes are connected, the source electrode of MNR, the drain electrode of the grid of MPR and MPR and ground potential
AGND is connected, and the substrate of MP15 and MP16 are connected with supply voltage AVDD, and the substrate of MNR is connected with ground potential AGND, the lining of MPR
Bottom is connected with VM nodes, and the diverter module 203 is used to carry out shunting function to the PTAT current that module 202 generates, to produce
A raw CTAT current；As shown in Fig. 4.
The VTHModule 204 is pre-compensated for by PMOS tube MP7~MP10, NMOS tube MN8~MN11 compositions；The source of MP7 and MP9
The substrate of pole and MP7~MP10 are connected with supply voltage AVDD, in the grid of MP7 and MP9 and positive warm current generating module 202
VBP nodes be connected, the drain electrode of MP7 is connected with the source electrode of MP8, and the drain electrode of MP9 is connected with the source electrode of MP10, MP8 and MP10's
Grid is connected with the VBP_C nodes in positive warm current generating module 202, the drain electrode of MP8 and MN9, the source electrode of MN8 and MN10 and
The grid and V2 nodes of MN11 is connected, and the drain electrode of MP10 and MN8 are connected with the grid of MN8 and MN9 and V1 nodes, MN9's
Source electrode is connected with the drain electrode of MN10 and Vg nodes, and the source electrode of MN10 is connected with the drain electrode of MN11, and the source electrode and MN8 of MN11~
The substrate of MN11 is connected with ground potential AGND.VTHPrecompensation module 204 is used to extract the threshold voltage of the negative temperature of NMOS
VTH, and use a positive temperature coefficient voltage (drain-source voltage V of linear zone NMOS tube MN11DS) to VTHCarry out precompensation operation；
As shown in Fig. 3.
The high temperature electric current compensating module 205 is by PMOS tube MP17~MP22, NMOS tube MN14~MN18 compositions；MP17、
The source electrode of MP18, MP19, MP21 and MP22 and the substrate of MP17~MP22 are connected with supply voltage AVDD, MP17 and MP18's
Grid is connected with the drain electrode of MP17 and MN14, and the drain electrode of MP18, MP21 and MN15 are connected with the grid of MP21 and MP22, MP19's
Grid is connected with the VBP nodes in positive warm current generating module 202, and the drain electrode of MP19 is connected with the source electrode of MP20, the grid of MP20
Pole is connected with the VBP_C nodes in positive warm current generating module 202, the grid phase of the drain electrode and MN15 and MN16 of MP20 and MN16
Even, the drain electrode of MP22, the drain electrode of MN18, the grid of MN17 be connected with the grid of MN18, the source electrode and substrate of MN14~MN18 and
Ground potential AGND is connected, and the grid of MN14 is connected with the VM nodes in diverter module 203；The drain electrode of MN17 and voltage superposition module
In Vout nodes be connected；High temperature electric current compensating module 205 when generating high temperature for compensating electric current；As shown in Fig. 4.
The low-temperature current compensating module 206 is by PMOS tube MP23~MP28, NMOS tube MN19~MN23 compositions；MP23、
The source electrode of MP24, MP25, MP27 and MP28 are connected with supply voltage AVDD, substrate and the supply voltage AVDD phases of MP23~MP28
Even, the grid of MP23 and MP24 is connected with the drain electrode of MP23 and MN19, and the drain electrode of MP24, MN20 and MN22 are with MN22's and MN23
Grid is connected, and the grid of MP25 is connected with the VBP nodes in positive warm current generating module 202, the source of the drain electrode and MP26 of MP25
Extremely be connected, the grid of MP26 is connected with the VBP_C nodes in positive temperature current generating module 202, the drain electrode of MP26 and MN21 and
MN20 is connected with the grid of MN21, and the drain electrode of the grid of MP27, the grid of MP28, MP27 is connected with the drain electrode of MN23, MP28's
Drain electrode and the V in voltage superposition module 207NMNode is connected, and the source electrode and substrate of MN19~MN23 are connected with ground potential AGND,
The grid of MN19 is connected with the VM nodes in diverter module 203；Compensation electricity when low-temperature current compensating module 206 is for generating low temperature
Stream；As shown in Fig. 4.
The voltage superposition module 207 is by PMOS tube MP11~MP14, NMOS tube MN12, MN13 composition；The source electrode of MP11
It is connected with supply voltage AVDD, the substrate of MP11 and MP12 are connected with supply voltage AVDD, and the grid of MP11 is produced with positive warm electric current
VBP nodes in raw module 202 are connected, and the drain electrode of MP11 is connected with the source electrode of MP12, and the grid of MP12 is generated with positive warm electric current
VBP_C nodes in module 202 are connected, the drain electrode of MP12, the substrate of MP13, MP14 substrate and MP13 and MP14 source electrode with
And VK nodes are connected, the grid and V of MP13THThe Vg nodes pre-compensated in module 204 are connected, the drain electrode of MP13 and MN12 and MN12
With the grid and V of MN13NMNode is connected, and the grid of MP14 is connected with the drain electrode of MP14 and MN13 and Vout nodes, MN12
It is connected with ground potential AGND with the source electrode of MN13 and substrate.Voltage superposition module 207 is used for positive temperature voltage MT and VTH
It is superimposed to pre-compensate for the negative temperature voltage that module 204 generates, to generate reference voltage V out.As shown in Fig. 3.
The present invention shunts PTAT current using simple shunt circuit, to generate a CTAT current, significantly
CTAT current generation circuit is simplified, chip area and design difficulty are reduced.Gate pmos source difference in voltage (△ is used alone
VGS) temperature coefficient of NMOS tube threshold voltage is compensated, it can lead to two kinds of situations：1) the electric current difference that two flows through PMOS tube
It is excessive；2) two PMOS tube areas of have big difference.And this can all increase chip area and may promoting flow through low current or
The PMOS tube of the big branch of pipe area enters subthreshold region.
Invention introduces a new positive temperature voltages (drain-source voltage for being operated in linear zone NMOS tube) to threshold voltage
It is pre-compensated for, weakens the demand to the compensation ability of rear class compensation circuit, this can guarantee that two PMOS tube are all operated in normally
Saturation state；And segmented current curvature correction technology is utilized, obtain the output reference voltage of a high-order curvature correction.Start
Module 201, positive warm current generating module 202, VTHIt pre-compensates for module 204 and voltage superposition module 207 generates a single order and mends
The reference voltage V out repaid, diverter module 203, high temperature electric current compensating module 205 and low-temperature current compensating module 206 are to benchmark
Voltage Vout carries out high-order curvature correction.In addition, resistance and amplifier is not used in the reference voltage source of the present invention, effectively reduce
The entire chip area of reference circuit and the complexity of design.
In conclusion while the present invention realizes high-order curvature correction, simplify CTAT current generation circuit, and effectively
Reduce the complexity of the chip area and design of reference voltage source.
Description of the drawings
Fig. 1 is traditional band-gap reference circuit schematic diagram；
Fig. 2 is the principle of the present invention block diagram；
Fig. 3 is the starting module, positive warm current generating module, V of the present inventionTHPre-compensate for module and voltage superposition module
Practical circuit diagram；
Fig. 4 is the actual circuit of the diverter module of the present invention, high temperature electric current compensating module and low-temperature current compensating module
Figure；
Fig. 5 is embodiment output reference voltage analogous diagram when the power supply electrifying time is 1us；
Fig. 6 is embodiment VTHPre-compensating for module, whether there is or not the simulation result diagrams that output voltage Vg is varied with temperature when MN11；
Fig. 7 is three branch current I of embodiment diverter modulePTAT、I1And I2The simulation result diagram varied with temperature；
Fig. 8 is I in embodiment high temperature electric current compensating moduler1The simulation result diagram varied with temperature；
Fig. 9 is I in embodiment low-temperature current compensating moduler2The simulation result diagram varied with temperature；
Figure 10 is that whether there is or not the simulation result diagrams that output reference voltage Vout is varied with temperature when curvature correction circuit for embodiment.
Specific implementation mode
Below in conjunction with the accompanying drawings and specific implementation mode is described in further detail the present invention.
High-order curvature correction reference voltage source framework is as shown in Fig. 2, including starting module 201, and positive temperature electric current generates mould
Block 202, diverter module 203, VTHPre-compensate for module 204, high temperature electric current compensating module 205, low-temperature current compensating module 206 and electricity
Press laminating module 207.
As shown in Fig. 3, start-up circuit 201 is made of MSP1, MSN1 and MSN2, when the supply voltage of circuit powers on it
Before, reference voltage circuit is in " 0 " degeneracy bias point, and VQ node potentials are low, and VBP node potentials are height, MSP1 and MSN2 structures
At phase inverter, VQ current potentials are detected, so that MSN1 pipes is connected, VBP node potentials is dragged down, circuit " 0 " degeneracy bias point is broken.Work as electricity
After road starts, VQ node potentials are got higher, and MSN1 is closed, and start-up circuit no longer influences circuit normal work.Start simulation result
Such as attached drawing 5, simulation result shows that reference voltage circuit can normally start.
As shown in Fig. 3, the principle of positive warm current generating module 202 is as follows：MAP1~MAP5, MAN1~MAN5 and QB structures
At bias voltage circuit, it provides two bias voltages for positive warm current generating circuit：VBP_C node voltages and VBN nodes
Voltage.MP3, MP4, MN1 and MN2 are cascade pipe, their effect is to increase loop gain and power supply rejection ratio.
As negative-feedback branch, their effect is to ensure that VQ nodes are identical as VBN_C node potentials by Q3, MP5, MP6, MN6 and MN7,
MNC ensures loop stability as compensating electric capacity.MN5 pipes are in linear zone, and positive temperature current generating circuit main thought is：MN3
It is operated in saturation region with MN4, ensures that the drain-source voltage of MN5 penetrates difference in voltage equal to two bipolar transistor bases, this value
Size can be indicated with following formula：
VDS, MN5=VBE, Q2-VBE,Q1=VT In N (2)
Meanwhile MN5 pipes, as a linear resistance, resistance value is：
The PTAT current finally generated is：
IPTAT=VTInN×μnCOX(W/L)MN5(VGS, MN5-VTHn)~μnT2 (4)
Wherein, N is the area ratio of PNP pipe Q1 and Q2, μnIt is electron mobility, COXIt is gate oxide unit area electricity
Hold, VTHnIt is the threshold voltage of NMOS tube, in this secondary design, it is assumed that all NMOS tube threshold voltages are identical and all PMOS
Pipe threshold voltage is identical, ignores channel-length modulation.Because of μn~T-1.5, then finally obtained electric current is PTAT current.
As shown in Fig. 3, VTHThe principle for pre-compensating for module 204 is as follows：MP7, MP8 and MP9, MP10 constitute current mirror,
In, (W/L)MP7,8/(W/L)MP9,10=2: 1, (W/L)MN10=3 (W/L)MN9=3 (W/L)MN8, MN9, MN11 are all in linear zone.
Its current formula is expressed as：
Abbreviation (5), (6), (7) formula, we can obtain：
Vg=VTHn+V3 (8)
Meanwhile MN11 is in linear zone：
V3=3VTInN×[(W/L)MN5/(W/L)MN11]×[(VGS, MN5-VTHn)/(VGS, MN11-VTHn)]~T (9)
Whether there is or not V when MN11THIt is as shown in Fig. 6 that the output voltage Vg of precompensation module 204 varies with temperature simulation curve, imitates
It is true the result shows that：There are MN11 relative to there is no MN11, VTHThe temperature coefficient for pre-compensating for the output voltage Vg of module 204 is opposite
Reduce, rear class compensation circuit is more easy to realize.
As shown in Fig. 4, the principle of diverter module 203 is as follows：MP15 and MP16 mirror image PTAT currents, MNR and MPR are
Diode connection type, their conducting resistances are indicated with following formula respectively：
Wherein, μnIt is electron mobility, μpIt is hole mobility, VTHnIt is the threshold voltage of NMOS tube, VTHpIt is PMOS tube
Threshold voltage, they have different temperatures coefficient, and pipe sizing is arranged, and can obtain two electricity with different temperature coefficients
Resistance.PTAT current is shunted using MNR and MPR, there is opposite temperature coefficient, to generate between their conducting resistances
Another electric current I opposite with the temperature coefficient of PTAT current2。IPTAT、I2With I3Electric current vary with temperature trend such as attached drawing 7
It is shown.Finally, I2Electric current is provided to subsequent high temperature electric current compensating module 205 and low-temperature current compensating module 206, emulation
The result shows that：I2The temperature coefficient of electric current and the temperature coefficient of PTAT current are exactly the opposite.
As shown in Fig. 4, the principle of high temperature electric current compensating module 205 is as follows：MP19, MP20 mirror image PTAT current, MN14
Mirror image MNR electric currents, MP17 generate electric current I with MP18 current mirrorsq1, MN16 and MN15 current mirrors generation electric current Iq2, two electric currents with
Electric current Ir1Between there are following relationships：
Wherein Ir1When equal to 0, MP18 is in linear zone, and MP18 can only mirror image I with MP17 current mirrorsq2The electric current of size.It is high
Wen Shi, it is assumed that Ir1Transition temperature when being not zero is T1.Pipe sizing is adjusted, the electric current I of an arbitrary size can be obtainedr1
With the T1 of arbitrary size.Obtaining electric current Ir1Later, the size of current mirror MP21 and MP22, MN18 and MN17 are adjusted, it is final to obtain
To compensation electric current at high temperature.Electric current Ir1Temperature characteristics it is as shown in Fig. 8, electric current Ir1It is zero in low-temperature zone, and
High temperature section is not zero, which can carry out temperature curvature correction in high temperature section to output reference voltage.
As shown in Fig. 4, the principle of low-temperature current compensating module 206 is as follows：MP25 and MP26 mirror image PTAT currents, and
MN19 mirror image MNR electric currents, MP23 generate electric current I with MP24 current mirror mirror imagesp1, MN20 and MN21 current mirror mirror images generate electric current
Ip2, there are following relationships with electric current Ir2 for two electric currents：
Wherein, Ir2When equal to 0, MN20 can be in linear zone, and MN20 can only mirror image I with MN21 current mirrorsp1Current.
When low temperature, it is assumed that Ir2Transition temperature when being zero is T2.Pipe sizing is adjusted, the electric current I of an arbitrary size can be obtainedr2
With the T2 of arbitrary size.Obtaining electric current Ir2Later, the size of current mirror MN22 and MN23, MP27 and MP28 are adjusted, it is final to obtain
To the compensation electric current in low temperature.Ir2Temperature characteristics it is as shown in Fig. 9, electric current Ir2It is not zero in low-temperature zone, and in height
Temperature section is zero, which can carry out temperature curvature correction in low-temperature zone to output reference voltage.
As shown in Fig. 3, the principle of voltage superposition module 207 is as follows：MP11 and MP12 mirror images PTAT current (its value direct ratio
In μnT2), due to (W/L)MP14/(W/L)MP13=SK1；(W/L)MN12/(W/L)MN13=SK2, simultaneously because MP13, MP14 locate
It can be obtained by the current formula of PMOS tube saturation region in saturation region：
I simultaneouslyMP13/IMP14=SK2, then abbreviation above-mentioned formula (13) (14), can obtain：
Wherein, Vg is the threshold voltage V of NMOSTHBy the output voltage of pre- curvature correction.Due to IMP13It is proportional to μnT2,
Ignore μnWith μpTemperature difference, thenIt is proportional to absolute temperature T.High temperature and low temp compensating are used respectively
The method that electric current carries out curvature correction：Voltage of reference voltage when voltage is significantly greater than medium temperature in low temperature and high temperature,
The value for reducing above formula (15) Section 2 in high temperature and low temperature respectively (reducesValue), make defeated
The reference voltage V out gone out realizes the effect of single order temperature-compensating in low temperature and high temperature section, finally achieves the mesh of high-order compensation
Mark.Whether there is or not when curvature correction circuit reference voltage source output reference voltage simulation result it is as shown in Fig. 10, temperature
Coefficient is reduced to 3.18ppm/ DEG C from 28ppm/ DEG C.
In conclusion relative to traditional reference voltage source, the present invention does not use amplifier and resistance, efficiently reduces
The area of reference voltage source.And reference voltage source proposed by the present invention utilizes the NMOS tube drain-source voltage pair for being operated in linear zone
The threshold voltage of NMOS carries out precompensation operation, simplifies rear class compensation circuit design.The present invention utilizes diode connection simultaneously
The characteristic of the mutual difference of NMOS and PMOS conducting resistance temperatures coefficient, it is proposed that shunt circuit has obtained one using shunt circuit
A CTAT current, without complicated CTAT current generation circuit.The present invention uses segmented current curvature correction technology, most
A high-order curvature correction reference voltage source has been obtained eventually.
Claims (1)
1. a kind of high-order curvature correction reference voltage source, including starting module, positive warm current generating module, diverter module, VTHIn advance
Compensating module, high temperature electric current compensating module, low-temperature current compensating module and voltage superposition module, it is characterised in that：
The starting module is for making entire reference circuit break away from " 0 " degeneracy bias point, by PMOS tube MSP1 and NMOS tube MSN1
~MSN2 is formed；
The source electrode and substrate of MSP1 is connected with supply voltage AVDD, and the drain electrode of MSP1 and MSN2 are connected with the grid of MSN1, MSP1
It is connected with the grid of MSN2 with the VQ nodes of positive warm current generating module, the VBP of the drain electrode of MSN1 and positive warm current generating module
Node is connected, and the source electrode and substrate of MSN1 and MSN2 are connected with ground potential AGND；
The positive temperature current generating module is for generating a PTAT current, the PTAT current and μnT2It is directly proportional, wherein μnIt is electricity
Transport factor, T are absolute temperature, by PMOS tube MAP1~MAP5, MP1~MP6, NMOS tube MAN1~MAN5, MN1~MN7,
MNC and PNP pipe Q1~Q3, QB composition；
The source electrode of MAP1, MAP2, MAP3, MAP4, MP1, MP2, MP5 are connected with supply voltage AVDD, and MAP1~MAP5 and MP1~
The substrate of MP6 is connected with supply voltage AVDD, and the grid of MAP1, MP1, MP2 and MP5 are saved with the drain electrode of MP6 and MN6 and VBP
Point is connected, and the drain electrode of MAP1 and MAN1 are connected with the grid of MAN1, MAN2 and MAN3, the grid of MAP2 and MAP3 and MAP2 and
The drain electrode of MAN2 is connected, and the drain electrode of MAP3 and MAN4 are connected with the grid of MAN4, MAN5, MN1, MN2 and MN6 and VBN nodes,
The grid of MAP4, MAP5, MP3, MP4 and MP6 are connected with the drain electrode of MAP5 and MAN3 and VBP_C nodes, the drain electrode of MAP4 with
The source electrode of MAP5 is connected, and the drain electrode of MP1 is connected with the source electrode of MP3, and the drain electrode of MP2 is connected with the source electrode of MP4, the drain electrode of MP5 and
The source electrode of MP6 is connected, and the drain electrode of MP3 and MN1 are connected with the grid of MN7 and MNC and VQ nodes, the drain electrode of MP4 and MN2 and
MN3, MN4 are connected with the grid of MN5 and VBN_C nodes；
The collector and base stage of QB, Q1, Q2 and Q3 are connected with ground potential AGND, source electrode and the ground electricity of MAN1, MAN2 and MAN3
Position AGND be connected, the source electrode of MAN4 is connected with the drain electrode of MAN5, and the source electrode of MAN5 is connected with the emitter of QB, the source electrode of MN1 and
The drain electrode of MN3 is connected, and the source electrode of MN2 is connected with the drain electrode of MN4, and the source electrode of MN3 is connected with the emitter of Q2, the source electrode of MN4 and
The drain electrode of MN5 is connected, and the source electrode of MN5 is connected with the emitter of Q1, and the source electrode of MN6 is connected with the drain electrode of MN7, the source electrode of MN7 and
The emitter of Q3 is connected, and the drain electrode of MNC and source electrode and substrate are connected with ground potential AGND, MN1~MN7 and MAN1~MAN5's
Substrate is connected with ground potential AGND；
The diverter module is used to carry out shunting function to the PTAT current that positive warm current generating module generates, to generate one
CTAT current is made of PMOS tube MP15, MP16, MPR and NMOS tube MNR；
The source electrode of MP15 is connected with supply voltage AVDD, and the grid of MP15 is connected with the VBP nodes in positive warm current generating module,
The drain electrode of MP15 is connected with the source electrode of MP16, and the grid of MP16 is connected with the VBP_C nodes in positive warm current generating module, MP16
It is connected with the source electrode of MPR, the grid of MNR and VM nodes with the drain electrode of MNR, the drain electrode of the source electrode of MNR, the grid of MPR and MPR
And ground potential AGND is connected, the substrate of MP15 and MP16 are connected with supply voltage AVDD, substrate and the ground potential AGND phases of MNR
Even, the substrate of MPR is connected with VM nodes；
The VTHPrecompensation module is used to extract the threshold voltage V of the negative temperature of NMOSTH, and use a positive temperature coefficient electricity
Pressure is to VTHCarry out precompensation operation；It is made of PMOS tube MP7~MP10 and NMOS tube MN8~MN11；Positive temperature coefficient voltage is
The drain-source voltage V of linear zone NMOS tube MN11DS；
The source electrode of MP7 and MP9 and the substrate of MP7~MP10 are connected with supply voltage AVDD, the grid of MP7 and MP9 and positive temperature
VBP nodes in current generating module are connected, and the drain electrode of MP7 is connected with the source electrode of MP8, the source electrode phase of the drain electrode and MP10 of MP9
Even, the grid of MP8 and MP10 is connected with the VBP_C nodes in positive warm current generating module, the drain electrode of MP8 and MN9, the source of MN8
Pole is connected with the grid of MN10 and MN11 and V2 nodes, the grid and V1 nodes of the drain electrode and MN8 and MN9 of MP10 and MN8
It is connected, the source electrode of MN9 is connected with the drain electrode of MN10 and Vg nodes, and the source electrode of MN10 is connected with the drain electrode of MN11, the source of MN11
The substrate of pole and MN8~MN11 are connected with ground potential AGND；
The high temperature electric current compensating module when generating high temperature for compensating electric current, by PMOS tube MP17~MP22 and NMOS tube MN14
~MN18 is formed；
The source electrode of MP17, MP18, MP19, MP21 and MP22 and the substrate of MP17~MP22 are connected with supply voltage AVDD,
The grid of MP17 and MP18 is connected with the drain electrode of MP17 and MN14, the grid of the drain electrode and MP21 and MP22 of MP18, MP21 and MN15
Extremely it is connected, the grid of MP19 is connected with the VBP nodes in positive warm current generating module, the source electrode phase of the drain electrode and MP20 of MP19
Even, the grid of MP20 is connected with the VBP_C nodes in positive warm current generating module, drain electrode and the MN15 and MN16 of MP20 and MN16
Grid be connected, the drain electrode of MP22, the drain electrode of MN18, the grid of MN17 are connected with the grid of MN18, the source electrode of MN14~MN18
It is connected with substrate with ground potential AGND, the grid of MN14 is connected with divergent die VM nodes in the block；The drain electrode of MN17 is folded with voltage
Mould Vout nodes in the block are added to be connected；
The low-temperature current compensating module when generating low temperature for compensating electric current, by PMOS tube MP23~MP28 and NMOS tube MN19
~MN23 is formed；
The source electrode of MP23, MP24, MP25, MP27 and MP28 are connected with supply voltage AVDD, the substrate and power supply of MP23~MP28
Voltage AVDD be connected, the grid of MP23 and MP24 are connected with the drain electrode of MP23 and MN19, the drain electrode of MP24, MN20 and MN22 and
MN22 is connected with the grid of MN23, and the grid of MP25 is connected with the VBP nodes in positive warm current generating module, the drain electrode of MP25 and
The source electrode of MP26 is connected, and the grid of MP26 is connected with the VBP_C nodes in positive temperature current generating module 202, MP26 and MN21's
Drain electrode is connected with the grid of MN20 and MN21, and the drain electrode of the grid of MP27, the grid of MP28, MP27 is connected with the drain electrode of MN23,
The drain electrode of MP28 and voltage superposition mould V in the blockNMNode is connected, source electrode and substrate and the ground potential AGND phases of MN19~MN23
Even, the grid of MN19 is connected with divergent die VM nodes in the block；
The voltage superposition module is used for positive temperature voltage MT and VTHIt is superimposed to pre-compensate for the negative temperature voltage that module generates,
To generate reference voltage V out；It is made of PMOS tube MP11~MP14 and NMOS tube MN12, MN13；
The source electrode of MP11 is connected with supply voltage AVDD, and the substrate of MP11 and MP12 are connected with supply voltage AVDD, the grid of MP11
Pole is connected with the VBP nodes in positive warm current generating module, and the drain electrode of MP11 is connected with the source electrode of MP12, the grid of MP12 and just
VBP_C nodes in warm current generating module are connected, the drain electrode of MP12, the substrate of MP13, the substrate of MP14 and MP13 and MP14
Source electrode and VK nodes be connected, the grid and V of MP13THIt pre-compensates for mould Vg nodes in the block to be connected, the drain electrode of MP13 and MN12
With the grid and V of MN12 and MN13NMNode is connected, the grid of MP14 and the drain electrode of MP14 and MN13 and Vout node phases
Even, the source electrode and substrate of MN12 and MN13 are connected with ground potential AGND.
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| CN201710711170.4A CN107390769B (en) | 2017-08-18 | 2017-08-18 | A kind of high-order curvature correction reference voltage source |
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| KR20090014559A (en) * | 2007-08-06 | 2009-02-11 | 신코엠 주식회사 | A bandgap reference circuit using a comparator |
| CN102147632A (en) * | 2011-05-11 | 2011-08-10 | 电子科技大学 | Resistance-free bandgap voltage reference source |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN103049032A (en) * | 2012-12-27 | 2013-04-17 | 东南大学 | Resistance-free CMOS (complementary metal oxide semiconductor) bandgap reference voltage source |
| CN103399606A (en) * | 2013-07-10 | 2013-11-20 | 电子科技大学 | Low-voltage bandgap-free reference voltage source |
| CN104199509B (en) * | 2014-09-17 | 2016-06-08 | 电子科技大学 | A kind of temperature-compensation circuit for band gap reference |
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| KR20090014559A (en) * | 2007-08-06 | 2009-02-11 | 신코엠 주식회사 | A bandgap reference circuit using a comparator |
| CN102147632A (en) * | 2011-05-11 | 2011-08-10 | 电子科技大学 | Resistance-free bandgap voltage reference source |
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN103049032A (en) * | 2012-12-27 | 2013-04-17 | 东南大学 | Resistance-free CMOS (complementary metal oxide semiconductor) bandgap reference voltage source |
| CN103399606A (en) * | 2013-07-10 | 2013-11-20 | 电子科技大学 | Low-voltage bandgap-free reference voltage source |
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