CN107331736A - LED component and its manufacture method having improved properties - Google Patents
LED component and its manufacture method having improved properties Download PDFInfo
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- CN107331736A CN107331736A CN201610273024.3A CN201610273024A CN107331736A CN 107331736 A CN107331736 A CN 107331736A CN 201610273024 A CN201610273024 A CN 201610273024A CN 107331736 A CN107331736 A CN 107331736A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
Abstract
The present invention provides a kind of method for manufacturing LED component having improved properties, including：1) LED chip of surface passivating treatment is not done in preparation；2) in step 1) the surface deposit passivation layer of LED chip that is prepared；3) photoresist is coated on the passivation layer, then nano-dot matrix is made on coated photoresist；4) using step 3) obtained by photoresist as mask, etch nano-structure array in the passivation layer, obtain patterned passivation layer；5) hole is etched on the patterned passivation layer to expose the P electrode region and N electrode region of LED chip, corresponding electrode metal is deposited in the hole etched.Present invention also offers corresponding LED component.The present invention can significantly improve LED chip light extraction efficiency simultaneously and significantly improve LED chip electric property, and strengthen LED reliability；Preparation method is simple and practical, suitable for industrial production；It is compatible with routine techniques；It can be used for the LED of multiple material system.
Description
Technical field
The present invention relates to light emitting diode (LED) technical field, specifically, the present invention relates to one
Plant LED component having improved properties and its manufacture method.
Background technology
Light emitting diode (LED) is due to its variable emission wavelength (from ultraviolet band to red spectral band)
And it is widely used in the field such as general illumination and display backlight source.But for preparing LED's
The refractive index difference of semi-conducting material (such as GaN, GaAs etc.) and air is big, and this causes LED core
There are Fresnel reflection losses and critical angle loss in the light produced in piece active area, in turn result in the overwhelming majority
Light is absorbed by multiple reflections and finally inside LED, and an only seldom part can be from LED chip
Leave on surface.At present frequently with graph substrate technology, photonic crystal technology and surface graphics technology
To improve LED light extraction efficiency.Wherein surface graphics technology simple possible, can be effectively improved
Light extraction efficiency, thus widely studied.
Chinese patent CN201210310976.X discloses a kind of GaN base LED transparent electrode figure
The preparation method of change, it is a kind of typical surface graphics technology.In this method, moved back using high temperature
Fiery SiO2It is allowed to recrystallization to form nanoscale dry etching mask, then etching transparency electrode makes its figure
Shape, so as to improve light extraction efficiency.Its main technological steps is as follows：1) in GaN base epitaxial layer
Transparency electrode of the upper evaporation thickness in 100nm~200nm；2) deposit thickness is on the transparent electrodes
1nm~10nm SiO2Layer；3) at 250~400 DEG C, annealing 5~10 minutes is carried out under condition of nitrogen gas,
SiO2Layer crystallization forms SiO2Graphic mask；The figure of the graphic mask includes rhombus, trapezoidal, round
Shape, triangle；4) exposed transparency electrode is removed with dry etching；5) gone with HF solution
Except SiO2Graphic mask.This surface graphics technology can improve light extraction efficiency, however, due to
Need to utilize high annealing SiO2Mode allow SiO2Recrystallization is covered to form nano level dry etching
Film, the method for this raising light extraction efficiency may influence the electric conductivity and translucency of transparency electrode.
Chinese patent CN201410168482.1 discloses another surface graphics technology, specific next
Say, Chinese patent CN201410168482.1 discloses the epitaxial wafer surface coarsening technique of LED a kind of,
The method that it is mixed using dry and wet is directly performed etching to GaN surfaces, forms nano level micro-structural,
Increase LED light extraction efficiency using this micro-structural.This scheme is improving light extraction efficiency
While, it is to avoid because too high annealing temperature and caused by transparency electrode electric conductivity reduced with translucency
The problem of.However, the program can not improve the electric property of LED chip.
With the continuous extension of LED component in the application, reliability to device and such as reverse
The requirement more and more higher of index in terms of the electric properties such as leakage current, breakdown reverse voltage.Prior art
In, generally it is passivated processing to improve the reliability and electricity of device by the surface to LED chip
Performance is learned, for example, according to circumstances can prepare corresponding passivating film on LED chip surface, for example, exist
LED chip surface prepares SiO2, SiNx, SiONx, Al2O3Film or corresponding composite multilayer membrane are made
For passivating film.However, Passivation Treatment scheme of the prior art is generally difficult to improve LED chip
Light extraction efficiency.Carry out Fine design to reduce luxuriant and rich with fragrance alunite even by the thickness to passivating film and refractive index
Ear loses and critical angle loss, and the raising of its light extraction efficiency is also difficult to more than 10%.
Therefore, currently in the urgent need to one kind can improve LED chip light extraction efficiency and improvement simultaneously
The solution of LED chip electric property.
The content of the invention
The task of the present invention is to provide one kind can be while improve LED chip light extraction efficiency and improvement
The solution of LED chip electric property.
The invention provides a kind of method for manufacturing LED component having improved properties, including it is following
Step：
1) LED chip of surface passivating treatment is not done in preparation；
2) in step 1) the LED chip surface deposit passivation layer that is prepared；
3) photoresist is coated on the passivation layer, then nanometer is made on coated photoresist
Dot matrix；
4) using step 3) obtained by photoresist as mask, etch nanostructured in the passivation layer
Array, obtains patterned passivation layer；
5) etch hole on the patterned passivation layer to expose the P electrode area of LED chip
Domain and N electrode region, deposit corresponding electrode metal in the hole etched.
Wherein, the step 1) in, the LED chip that surface passivating treatment is not done is from the bottom to top
Include successively：Substrate, N-type region, active area, p type island region and the electrically conducting transparent of GaN epitaxy growth
Layer.
Wherein, the step 2) in, the material of the passivation layer is SiO2、SiNxOr SiONx。
Wherein, the step 2) in, using plasma strengthens chemical vapour deposition technique in LED
Chip surface deposit passivation layer, and the passivation layer is covered the LED in deposit passivation layer
The side wall of chip；The passivation layer thickness is in the range of 250nm~600nm.
Wherein, the step 3) in, the nano-dot matrix made on a photoresist is nanometer periodic lattice.
Wherein, the step 4) in, the nano-structure array is the nanostructured of truncate pyramid pattern
Array.
Wherein, the step 4) in, the nano-structure array is columnar nano-structure array.
Wherein, the step 5) in, with reference to photoetching technique and dry etching technology described graphical
Passivation layer etching hole.
Present invention also offers a kind of LED component, including LED chip and patterned passivation layer；
The patterned passivation layer is fabricated on the surface of the LED chip, and with nanostructured
Array.
Wherein, the material of the passivation layer is SiO2、SiNxOr SiONx；The nanostructured battle array
It is classified as the nano-structure array or columnar nano-structure array of truncate pyramid pattern.
Compared with prior art, the present invention has following technique effect：
1st, the present invention can significantly improve LED chip light extraction efficiency simultaneously and significantly improve LED core
Piece electric property, and strengthen LED reliability.
2nd, preparation method of the present invention is simple and practical, suitable for industrial production.
3rd, the solution of the present invention and conventional raising light extraction efficiency method (such as graph substrate technology,
Transparency electrode coarsening technique etc.) it is compatible.
4th, the present invention's is applied widely, can be used for the LED of multiple material system, such as GaN
System, GaAs systems, AlGaInP systems etc..
Brief description of the drawings
Hereinafter, embodiments of the invention are described in detail with reference to accompanying drawing, wherein：
Fig. 1 shows the LED chip before the surface passivating treatment used in one embodiment of the invention
Diagrammatic cross-section；
Fig. 2 is shown deposits the section after certain thickness passivation layer on chip shown in Fig. 1 using conventional method
Schematic diagram；
Fig. 3 shows the diagrammatic cross-section after spin coating photoresist in LED chip sample shown in Fig. 2；
Fig. 4 shows that the section after photoresist nano-dot matrix is made in LED chip sample shown in Fig. 3 to be shown
It is intended to；
Fig. 5 is shown by the use of photoresist as mask in LED chip sample shown in Fig. 4, using dry method
Etching obtains the diagrammatic cross-section after periodicity truncate pyramid nanostructured；
Fig. 6 is shown by the use of photoresist as mask in LED chip sample shown in Fig. 4, using dry method
Etching obtains the diagrammatic cross-section after periodic nanometer post；
Fig. 7 show in LED chip sample shown in Fig. 5 using photoetching technique and electron beam evaporation or
The diagrammatic cross-section of sample after magnetron sputtering deposition metal contact layer；
Fig. 8 show in LED chip sample shown in Fig. 6 using photoetching technique and electron beam evaporation or
The diagrammatic cross-section of sample after magnetron sputtering deposition metal contact layer；
Fig. 9 shows the SiON on GaN base LED chip surface in the present embodimentxMade on passivation layer
Periodicity truncate pyramid nano-structure array surface (overlook visual angle under surface) and cross-sectional scans electricity
Mirror (SEM) figure；
Figure 10 shows the SiN on GaN base LED chip surfacexThe periodicity post made on passivation layer
Surface (surface overlooked under visual angle) and cross-sectional scans Electronic Speculum (SEM) figure of shape nano-structure array.
Wherein 1 is the substrate of GaN epitaxy growth, and 2 be N-type GaN, and 3 be LED active area, 4
It is p-type GaN, 5 be transparency conducting layer, and 6 be passivation layer, and 7 be photoresist layer, and 8 be P and N areas
Metal contact layer.
Embodiment
The present invention is further described through with reference to the accompanying drawings and examples.
Embodiment 1：Make the GaN base LED with nanometer truncate pyramid SiONx passivation layers
Step 100：Prepare the GaN base LED chip for not doing surface passivating treatment.Fig. 1 shows this
The diagrammatic cross-section of LED chip before the surface passivating treatment used in embodiment；Wherein, 1 is GaN
The substrate of epitaxial growth, 2 be N-type GaN, and 3 be LED active area, and 4 be p-type GaN, 5
It is transparency conducting layer, otherwise referred to as transparent conductive electrode herein.In the present embodiment, LED N
Area is obtained by ICP dry etchings, and transparent conductive electrode is by electron beam evaporation plating or magnetic control
What sputtering sedimentation was realized, in one example, transparent conductive electrode is in P using magnetically controlled sputter method
Type GaN surfaces make transparent conductive electrode tin indium oxide (ITO).
Step 200：Using such as plasma enhanced chemical vapor deposition technology (PECVD) in chip
Surface deposit passivation layer.It is well known that LED chip n-type GaN layer generally some directly it is naked
At the same time dew, then make successively as N electrode region on another part of N-type GaN layer
LED active area, p-type GaN layer and transparency conducting layer, wherein transparency conducting layer is used as P electrode area
Domain.In this step, chip surface both includes transparency conducting layer upper surface, also including directly exposed work
For the surface of the N-type GaN layer in N electrode region.
In the present embodiment, passivation layer can be about 400nm SiONxLayer, process gas can be SiH4、
NH3With NO2.Fig. 2, which is shown, is using conventional method deposition certain thickness blunt on chip shown in Fig. 1
Change the diagrammatic cross-section after layer, wherein 6 be the certain thickness passivation layer that conventional method is deposited.It is existing
In technology, passivation layer is divided into two classes, and a class is Al of the thickness in 30nm or so2O3Passivation layer, it is another
Class is SiO of the thickness in 50nm~200nm2Or SiNxPassivation layer.Passivation layer thickness it is general not over
200nm, because for the conventional passivation layer that existing preparation method is formed, if its thickness
It is excessive to reduce the light extraction efficiency of LED chip.And the present invention breaches this understanding, in chip list
Face deposits about 400nm SiONxLayer, the SiONxLayer can preferably be adapted to after graphical place
Reason, meanwhile, the SiONxLayer can also effectively protect the side wall of LED chip.
Step 300：Photoresist is coated over the passivation layer.Fig. 3 is shown in the present embodiment shown in Fig. 2
LED chip sample on coating photoresist 7 after diagrammatic cross-section.In one alternate embodiment,
Photoresist can be coated using following concrete mode：The table of chip after it deposited passivation layer
Face spin coating thickness about 100nm anti-reflecting layer and on the hot plate that temperature is 180 DEG C carry out the time be 2.5
The baking of minute；Chip cooling technique is treated to room temperature, positive photoresist that thickness is 300nm is then spin coated onto simultaneously
The baking that the time is 2 minutes is carried out on the hot plate that temperature is 90 DEG C, room temperature is then cooled to.
Step 400：Photoresist nano-dot matrix, such as nanometer are prepared using such as laser interference photolithography technology
Periodic lattice.Fig. 4 is shown makes the photoresist nanometer cycle on the LED chip sample shown in Fig. 3
Diagrammatic cross-section after dot matrix, wherein 7 be photoresist layer.This nanometer of periodic lattice can be cardinal points
Battle array, it refers to that the arrangement mode of photoresist dot matrix is cubic dot matrix.In the present embodiment, lattice period can
To be about 650nm, laser interference exposure is using 325nm He-Cd LASER Light Sources, and light path is using double
Beam configuration, takes double exposure technique during exposure, sample is rotated by 90 ° along normal during second of exposure.
Step 500：Using the photoresist of gained as mask, receiving for truncate pyramid pattern is etched in passivation layer
Rice array of structures (such as periodic nano-structure array), obtains patterned passivation layer.Specifically,
ICP lithographic techniques etching SiON can be utilized for example using obtained photoresist nano-dot matrix as maskx
(unit type that the present embodiment is used is System100 ICP 180, Oxford Instruments)；It is logical
Cross control etch process parameters (such as reative cell air pressure, gaseous species are matched) and etch rescinded angle taper
The array of the nanostructured of looks.In the present embodiment, during etching nanostructured, gaseous species proportioning is
C4F8/ Ar=1:3, reative cell air pressure is 12 person of outstanding talent's supports (mtorr), and substrate bias power is 30W.Fig. 5 is shown
Periodically cut using dry etching by the use of photoresist as mask on LED chip sample shown in Fig. 4
Diagrammatic cross-section after pyramid nanostructured.Fig. 9 is shown in the present embodiment in GaN base LED chip
The SiON on surfacex(vertical view is regarded on the surface of the periodicity truncate pyramid nano-structure array made on passivation layer
Surface under angle) and cross-sectional scans Electronic Speculum (SEM) figure.
Step 600：With reference to such as ultraviolet photolithographic technology and dry etching technology, GaN base LED is etched
The P of chip and N electrode region and deposit corresponding electrode metal, such as multilayer metallic electrode
Cr/Pt/Au (20nm/20nm/200nm) etc..Fig. 7 shows sharp in LED chip sample shown in Fig. 5
With the diagrammatic cross-section after photoetching technique and electron beam evaporation or magnetron sputtering deposition metal contact layer.
Wherein, 8 be metal contact layer.In the present embodiment, the metal contact layer of metal contact layer including P areas and
The metal contact layer in N areas.
In the present embodiment, passivation layer can effectively reduce chip surface, the leak channel of side wall, thus carry
High chip electric property.And the nanostructured on passivation layer can greatly increase light extraction efficiency.Also,
This patterned passivation layer of the present embodiment is adapted to industrialized production, can strengthen LED component simultaneously
Electric property and optical property, and can also apply in the device such as solar cell and detector.
Performance test discovery is carried out to LED chip prepared by this implementation：When reverse bias voltage is -5v,
Reverse leakage current is reduced to 1.1 microamperes, and the reverse leakage current for the sample not being passivated is 6 microamperes.Can be with
Find out, the scheme of the present embodiment can significantly improve the breakdown reverse voltage of LED chip, and then improve
The reliability of LED chip.Meanwhile, the LED prepared relative to the LED chip without passivation layer, this implementation
The light extraction efficiency of chip is lifted at more than 60%.
Embodiment 2：Making has nano-pillar SiNxThe GaN base LED of passivation layer
Step 10：LED n areas are etched using such as ICP dry etching methods, using such as magnetic
Control sputtering method and make transparent conductive electrode tin indium oxide (ITO) on p-type GaN surfaces, such as Fig. 1 institutes
Show.
Step 20：Using such as plasma enhanced chemical vapor deposition technology (PECVD) in chip
Surface deposits e.g., from about 300nm SiNxLayer, process gas can be SiH4With NH3, such as Fig. 2 institutes
Show, this SiNxThe side wall that layer can etch LED is effectively protected.
Step 30：In SiNxPhotoresist is coated on layer.Specifically, can be in chip surface spin coating thickness
About 100nm anti-reflecting layer simultaneously carries out the baking that the time is 2.5 minutes on the hot plate that temperature is 180 DEG C
It is roasting；Chip cooling technique is treated to room temperature, positive photoresist that thickness is 300nm is then spin coated onto and is in temperature
The baking that the time is 2 minutes is carried out on 90 DEG C of hot plate, room temperature is then cooled to, as shown in Figure 3.
Step 40：Photoresist nano-dot matrix, preferably nanometer are prepared using such as laser interference photolithography technology
Periodic lattice, such as cubic dot matrix (Fig. 4).Lattice period may be about 650nm, laser interference exposure
Using 325nm He-Cd LASER Light Sources, light path is configured using dual-beam, takes and expose twice during exposure
Light technology, sample is rotated by 90 ° along normal during second of exposure.
Step 50：Using the photoresist of gained as mask, in SiNxIt is (such as all that layer etches nano-pillar
Phase property nano-pillar), obtain patterned passivation layer.Specifically, the photoresist that can for example obtain is received
Rice dot matrix is mask, and SiN is etched using ICP lithographic techniquesx(unit type is System100 ICP 180,
Oxford Instruments)；By controlling etch process parameters, such as reative cell air pressure, gaseous species are matched somebody with somebody
Than etc. etch columnar nano-structure array.Wherein, the gaseous species proportioning used is CHF3/ Ar=1:1,
Reative cell air pressure is 12 person of outstanding talent's supports (mtorr), and substrate bias power is 100W.Fig. 6 shows Fig. 4 institutes sample
By the use of photoresist as mask on product, the signal of the section after periodic nanometer post is obtained using dry etching
Figure.Figure 10 shows the SiN on GaN base LED chip surfacexThe periodicity post made on passivation layer
Surface (surface overlooked under visual angle) and cross-sectional scans Electronic Speculum (SEM) figure of shape nano-structure array.
Step 60：With reference to such as ultraviolet photolithographic technology and dry etching technology, GaN base LED is etched
The P of chip and N electrode region and deposit corresponding electrode metal, such as Multilayer Film Electrode
Cr/Pt/Au (20nm/20nm/200nm) etc..Fig. 8 shows and utilized in LED chip sample shown in Fig. 6
Photoetching technique and the section of the sample after electron beam evaporation or magnetron sputtering deposition metal contact layer are illustrated
Figure.
The LED chip prepared for this implementation, when reverse bias voltage is -5v, reverse leakage current reduces
To 0.9 microampere, and the reverse leakage current for the sample not being passivated is 6 microamperes.As can be seen that the present embodiment
Scheme can significantly improve the breakdown reverse voltage of LED chip, and then improve the reliable of LED chip
Property.Meanwhile, relative to the LED chip without passivation layer, LED chip prepared by this implementation goes out light efficiency
Rate is lifted at more than 30%.
It should be noted that in the present invention, the passivation layer thickness is general in 250nm~600nm scopes
Interior, it is because too the meeting of thick film increases film in itself to light that 600nm or so is limited on thickness range
Absorption, cause transmissivity to decline, be unfavorable for light extraction.The nanostructured etched on passivation layer is not
Be limited to rescinded angle taper or column, in some other embodiment, the nanostructured can also be it is hemispherical or
Person is the other shapes such as taper.In the present invention, LED chip is not limited to GaN base LED chip, example
Such as：In other embodiments, LED chip can also be the LED of GaAs bases or AlGaInP bases
Chip.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for this
For the technical staff in field, the present invention can have various modifications and variations.It is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc. such as, are joined to the technique in example
Number has carried out simple change, should be included in the scope of the protection.
Claims (10)
1. a kind of method for manufacturing LED component having improved properties, comprises the following steps：
1) LED chip of surface passivating treatment is not done in preparation；
2) in step 1) the surface deposit passivation layer of LED chip that is prepared；
3) photoresist is coated on the passivation layer, then nanometer is made on coated photoresist
Dot matrix；
4) using step 3) obtained by photoresist as mask, etch nanostructured in the passivation layer
Array, obtains patterned passivation layer；
5) etch hole on the patterned passivation layer to expose the P electrode area of LED chip
Domain and N electrode region, deposit corresponding electrode metal in the hole etched.
2. the method for manufacture LED component having improved properties according to claim 1, its
It is characterised by, the step 1) in, the LED chip that surface passivating treatment is not done is from the bottom to top
Include successively：Substrate, N-type region, active area, p type island region and the transparency conducting layer of epitaxial growth.
3. the method for manufacture LED component having improved properties according to claim 1, its
It is characterised by, the step 2) in, the material of the passivation layer is SiO2、SiNxOr SiONx。
4. the method for manufacture LED component having improved properties according to claim 3, its
It is characterised by, the step 2) in, using plasma strengthens chemical vapour deposition technique in LED
The surface deposit passivation layer of chip, and the passivation layer is covered the LED in deposit passivation layer
The side wall of chip；The passivation layer thickness is in the range of 250nm~600nm.
5. the method for manufacture LED component having improved properties according to claim 4, its
It is characterised by, the step 3) in, the nano-dot matrix made on a photoresist is photoresist nanometer week
Phase dot matrix.
6. according to manufacture LED component having improved properties according to any one of claims 1 to 4
Method, it is characterised in that the step 4) in, the nano-structure array be truncate pyramid pattern
Nano-structure array.
7. according to manufacture LED component having improved properties according to any one of claims 1 to 4
Method, it is characterised in that the step 4) in, the nano-structure array be columnar nanometer knot
Structure array.
8. according to manufacture LED component having improved properties according to any one of claims 1 to 4
Method, it is characterised in that the step 5) in, exist with reference to photoetching technique and dry etching technology
Described hole is etched on the patterned passivation layer.
9. a kind of LED component, including：
LED chip；With
Patterned passivation layer, the patterned passivation layer is fabricated on the table of the LED chip
On face, and with nano-structure array.
10. LED component according to claim 9, it is characterised in that the passivation layer
Material is SiO2、SiNxOr SiONx；The nano-structure array is the nano junction of truncate pyramid pattern
Structure array or columnar nano-structure array.
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| CN109119436A (en) * | 2018-09-29 | 2019-01-01 | 华南理工大学 | Nano-pore LED array chip of roughing in surface and preparation method thereof |
| CN109166878A (en) * | 2018-09-29 | 2019-01-08 | 华南理工大学 | Nano-pore LED array chip and preparation method thereof with anti-reflection passivation layer |
| CN109119436B (en) * | 2018-09-29 | 2024-04-09 | 华南理工大学 | Surface roughened nano-pore LED array chip and preparation method thereof |
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Application publication date: 20171107 |