CN107293626A - LED chip, LED core chip package and preparation method - Google Patents
LED chip, LED core chip package and preparation method Download PDFInfo
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- CN107293626A CN107293626A CN201610197321.4A CN201610197321A CN107293626A CN 107293626 A CN107293626 A CN 107293626A CN 201610197321 A CN201610197321 A CN 201610197321A CN 107293626 A CN107293626 A CN 107293626A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Abstract
The present invention proposes a kind of LED chip, including：Have to be provided with the first positive pole and the first negative pole, the second electrode region in first electrode area and the second electrode region, the first electrode area on epitaxial wafer, the epitaxial wafer and be provided with the second positive pole and the second negative pole；The epitaxial wafer is provided with the groove for being electrically isolated, and first positive pole and the second negative pole are located at the side of the groove, and first negative pole and the second positive pole are located at the opposite side of the groove；Eutectic Layer, the Eutectic Layer includes the first Eutectic Layer and the second Eutectic Layer, and first Eutectic Layer is arranged at first electrode area and covers the first positive pole and the first negative pole, and second Eutectic Layer is arranged at the second electrode region and covers the second positive pole and the second negative pole.The LED chip, without direct current driving power supply, can improve electric work conversion efficiency directly using exchange electric drive, compared to direct-current LED chip, and radiating effect is more preferably, adds the service life and reliability of LED chip.
Description
Technical field
The present invention relates to LED technical field, more particularly to a kind of LED chip, LED core chip package and system
Make method.
Background technology
Blue-ray LED（Light emitting diode）Chip is all that, using sapphire as substrate, typical structure is included with bottom mostly
Point：(1), in sapphire substrates deposited on materials epitaxial layer, the epitaxial layer is followed successively by cushion, N-type GaN layer, lighted from top to bottom
Layer, p-type GaN layer；(2), in p-type GaN layer formation P electrode, N-type GaN is etched to from p-type GaN layer in chip surface local location
Layer, and making forms N electrode on this region.
The LED chip of this conventional levels structure contains a positive pole and a negative metal contact layer, and direct current is from positive pole
Being capable of normal luminous after being passed through.And the device made with LED generally all can be comprising a driving power supply, for alternating current to be changed
For available direct current.
What is used under daily life lighting environment is all 220V alternating currents, and conventional LED chip can only be driven with direct current
It is dynamic, so LED chip needs to increase a direct current driving power supply when the later stage encapsulating to form device, thus can be daily friendship
Stream electricity is converted to the direct current used in LED by rectified action.But the volume of direct current driving power supply in itself is bigger than normal, in LED devices
Part occupies excessive volume in formation.And driving power supply can consume part electrical power when energy is changed in itself, consumption
Electrical power can produce substantial amounts of heat again, increase the radiating burden of device, the luminous efficiency of final influence LED component；Drive simultaneously
Dynamic power source life is generally more much lower than LED chip, and caused result is that LED component chips are not bad, and driving power supply is first damaged,
So the service life of whole device can be substantially reduced.
In other scenes, what is produced when for example automobile current generator generates electricity is alternating current, and it will also pass through rectifier by electricity
Circulation is changed to direct current, then supplies automobile indicator and instrument panel lamp is used, the rectifier during this can also consume power,
Space-consuming.
The chip of DC powered is after long-time is lighted, because electric current congestion effect can occur for negative electrode area, occurs
During electric current congestion, electric current is by diffusion aggregation in negative regions.And negative regions only one of which, therefore negative electrode area can produce
Substantial amounts of heat, chip overheating will aging, the performance of influence chip.
The content of the invention
It is contemplated that at least solving one of above-mentioned technical problem to a certain extent.Therefore, the present invention proposes one kind
LED chip, the LED chip, compared to direct-current LED chip, without direct current driving power supply, can be improved directly using exchange electric drive
Electric work conversion efficiency, and radiating effect is more preferably, adds the service life and reliability of LED chip.
To solve the above problems, the present invention proposes a kind of LED chip, including：Have first on epitaxial wafer, the epitaxial wafer
The first positive pole and the first negative pole, the second electrode are provided with electrode zone and the second electrode region, the first electrode area
The second positive pole and the second negative pole are provided with region；The epitaxial wafer be provided with for be electrically isolated groove, first positive pole and
Second negative pole is located at the side of the groove, and first negative pole and the second positive pole are located at the opposite side of the groove；Eutectic
Layer, the Eutectic Layer includes the first Eutectic Layer and the second Eutectic Layer, and first Eutectic Layer is arranged at first electrode area and covered
The positive pole of lid first and the first negative pole, second Eutectic Layer are arranged at the second electrode region and cover the second positive pole and second negative
Pole.
The present invention also proposes a kind of LED core chip package, including：Electrode is provided with substrate, the substrate；As above institute
The LED chip stated, the LED chip is inverted on the substrate, first Eutectic Layer and the second Eutectic Layer and the substrate
On electrode pair should connect.
The structure of LED chip based on above-described embodiment, another aspect of the present invention embodiment proposes a kind of system of LED chip
Make method, including：
Epitaxial wafer is formed, the epitaxial wafer includes substrate and the cushion sequentially formed on substrate, n type semiconductor layer, lighted
Layer and p type semiconductor layer；
The groove for being etched to substrate, and the fill insulant in groove are formed on epitaxial wafer, the groove divides epitaxial wafer
Two parts are segmented into, the both sides of groove set first electrode area and the second electrode region respectively；
First electrode area and the second electrode region on epitaxial wafer form negative electrode hole respectively, and the negative electrode hole is etched to
N type semiconductor layer；
Conductive layer is formed on p type semiconductor layer；
The first positive pole and the second positive pole are formed respectively on the conductive layer of first electrode area and the second electrode region, in the first electricity
The second negative pole and the second positive pole are formed respectively in polar region domain and the negative electrode hole of the second electrode region；
Insulating barrier is formed between the side wall and the first negative pole and the second negative pole in negative electrode hole；
Eutectic Layer is formed, the Eutectic Layer includes the first Eutectic Layer and the second Eutectic Layer, and the first Eutectic Layer formation is first
Electrode zone simultaneously covers the first positive pole and the first negative pole, and the second Eutectic Layer formation is in the second electrode region and covers second just
Pole and the second negative pole.
LED chip according to embodiments of the present invention, alternating current can be selected from the first electrode area of LED chip or the second electricity
The positive pole in polar region domain is flowed into, and is flowed out from the negative pole of another electrode zone, therefore can be compared directly using exchange electric drive
Direct-current LED chip, without direct current driving power supply, improves electric work conversion efficiency；Secondly, the LED chip of the embodiment of the present invention exists
Electrode zone is provided with Eutectic Layer, improves the radiating effect of LED chip；Meanwhile, the both sides of LED chip are respectively provided with a negative electricity
Pole, in the cycle of alternating current, the sense of current of chip both sides alternately changes, and the electric current congestion effect of negative electrode area is just divided
The both sides of LED chip are dispersed in, whole LED chip heating is uniform, adds the service life and reliability of LED chip.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
Substantially and be readily appreciated that, wherein：
Fig. 1 is the structural representation of the LED chip according to one embodiment of the present of invention；
Fig. 2 is the top view of the LED chip according to one embodiment of the present of invention；
Fig. 3-Figure 10 is the structural representation of the LED chip manufacturing process according to one embodiment of the present of invention；
Figure 11 is the structural representation of the LED core chip package according to one embodiment of the present of invention.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.For letter
Change disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only merely illustrative, and
Purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or letter.It is this heavy
It is the relation between itself not indicating discussed various embodiments and/or setting for purposes of simplicity and clarity again.This
Outside, the invention provides various specific techniques and material example, but those of ordinary skill in the art can be appreciated that
The applicable property of other techniques and/or the use of other materials.In addition, fisrt feature described below second feature it
" on " structure can include the first and second features and be formed as the embodiment that directly contacts, other feature shape can also be included
Into the embodiment between the first and second features, such first and second feature may not be direct contact.
In the description of the invention, it is necessary to explanation, unless otherwise prescribed and limit, term " installation ", " connected ",
" connection " should be interpreted broadly, for example, it may be mechanically connect or electrical connection or the connection of two element internals, can
To be to be joined directly together, it can also be indirectly connected to by intermediary, for the ordinary skill in the art, can basis
Concrete condition understands the concrete meaning of above-mentioned term.
With reference to following description and accompanying drawing, it will be clear that these and other aspects of embodiments of the invention.In these descriptions
In accompanying drawing, some particular implementations in embodiments of the invention are specifically disclosed, to represent the implementation for implementing the present invention
Some modes of the principle of example, but it is to be understood that the scope of embodiments of the invention is not limited.On the contrary, the present invention
Embodiment includes all changes, modification and the equivalent fallen into the range of the spirit and intension of attached claims.
LED chip, LED core chip package and the LED core proposed according to embodiments of the present invention is described with reference to the accompanying drawings
The preparation method of piece.
First, the LED chip to the embodiment of the present invention is illustrated, and the LED chip of the embodiment of the present invention is particularly suitable for use in
Flip LED chips structure.As shown in Figure 1, Figure 2 with shown in Figure 10, the LED chip 100 of the embodiment of the present invention, including epitaxial wafer 10, institute
State on epitaxial wafer 10 to have and first is being provided with first electrode area 110 and the second electrode region 120, the first electrode area just
The second positive pole 121 and the second negative pole 122 are provided with the negative pole 112 of pole 111 and first, the second electrode region 120；The extension
Piece 10 is provided with the groove 101 for being electrically isolated, and the negative pole 122 of the first positive pole 111 and second is located at the one of the groove 101
Side, the positive pole 121 of the first negative pole 112 and second is located at the opposite side of the groove 101；Eutectic Layer 20, the Eutectic Layer 20
Including the first Eutectic Layer 21 and the second Eutectic Layer 22, first Eutectic Layer 21 is arranged at first electrode area 110 and covers the
One positive pole 111 and the first negative pole 112, second Eutectic Layer 22 are arranged at the second electrode region 120 and cover the second positive pole 121
With the second negative pole 122.
Specifically, first electrode area 110 and the second electrode region 120, two electrode districts are defined on the surface of epitaxial wafer 10
Domain is located at the both sides on epitaxial wafer 10 respectively, is preferably symmetric, the shape of electrode zone is not construed as limiting, in the present embodiment
In be set to rectangle, each electrode zone is respectively provided with a positive pole and a negative pole.It is additionally provided with epitaxial wafer 10 with electric isolution
The groove 101 of effect, the first positive pole 111 and the second negative pole 122 are located at the side of the groove 101, the He of the first negative pole 121
Second positive pole 112 is located at the opposite side of the groove 101.In other words, electric isolution here refers to that groove 101 has cut-off electricity
The effect of stream so that electric current can not circulate between the electrode of the both sides of groove 101, in order that groove 101 is acted on electric isolution, institute
The depth for stating groove 101 extends to the substrate of epitaxial wafer 10.
The material of the Eutectic Layer 20 selects conductive material, is closed such as from Cr/Ti/Au, Ti/ Al, Ti/Au
One kind in gold, the thickness of Eutectic Layer 20 is 0.8-1.5 um.The area on the covering epitaxial wafer 10 of Eutectic Layer 20 surface accounts for epitaxial wafer
The 50%-70% of 10 total surface areas, the spacer between the first Eutectic Layer 21 and the second Eutectic Layer 22 of the both sides of epitaxial wafer 10
From 50-200 um, the Edge Distance 20-40um of Eutectic Layer 20 and epitaxial wafer 10.
Compared with existing direct-current LED chip, the LED chip of the embodiment of the present invention can directly use exchange electric drive, to
When Eutectic Layer is passed through alternating current, the sense of current of alternating current alternately changes, due to the electrology characteristic of light emitting diode, alternating current meeting
Select to flow into from the first electrode area of LED chip or the positive pole of the second electrode region, from the negative pole of another electrode zone
Outflow, therefore without extra direct current driving power supply, it is to avoid alternating current is converted into the energy loss of direct current, improves electric work
Conversion efficiency, can also reduce the volume of LED component, cost-effective.
Secondly, the LED chip of the embodiment of the present invention is provided with Eutectic Layer, Eutectic Layer covering on epitaxial wafer in electrode zone
Capping product is larger, can effectively improve the radiating effect of LED chip.Meanwhile, the electrode district of the LED chip both sides of the embodiment of the present invention
Domain is respectively provided with a negative electrode, in the cycle of alternating current, and the sense of current of chip both sides alternately changes, the electricity of negative electrode area
Stream congestion effect has just been dispersed in the both sides of LED chip so that whole LED chip heating is uniform, adds making for LED chip
Use life and reliability.
In one embodiment of the invention, the LED chip also includes conductive layer 16, and the epitaxial wafer 10 includes substrate
11st, on substrate 11 cushion 12, n type semiconductor layer 13, luminescent layer 14 and p type semiconductor layer 15, the conductive layer
16 on the p type semiconductor layer 15, the positive electrode 121 of the first positive electrode 111 and second set on conductive layer 16 and with
Conductive layer 16 is electrically connected；The first electrode area 110 and the second electrode region 120, which are provided with, extends to n type semiconductor layer 13
Negative electrode hole 102, the negative electrode 122 of the first negative electrode 112 and second is arranged in negative electrode hole 102 and partly led with N-type
Body layer 13 is electrically connected, provided with insulation between the side wall in the negative electrode hole 102 and the first negative electrode 112 and the second negative electrode 122
Layer 18.
Specifically, the epitaxial wafer 10 is the GaN base epitaxial wafer using sapphire as substrate, and n type semiconductor layer 13 is N-type
GaN layer, luminescent layer 14 is multiple quantum well layer, and p type semiconductor layer 15 is p-type GaN layer.In the electricity of first electrode area 110 and second
First positive pole and the second positive pole are set on the conductive layer 16 in polar region domain 120, divided in first electrode area and the second electrode region
Not She You a negative electrode hole 102, the negative electrode hole 102 extends to N-type GaN layer, is then deposited in negative electrode hole 102 negative
Pole, in order that negative pole is not electrically connected with multiple quantum well layer, p-type GaN layer and conductive layer, in the side wall in negative electrode hole 102 and the
Insulating barrier 18 is set between one negative pole and the second negative pole so that negative pole can not be connected with multiple quantum well layer with p-type GaN layer, only be
The bottom of negative pole is electrically connected with N-type GaN layer.The insulating barrier 18 can be SiO2Layer, the conductive layer is ITO（Tin indium oxide）
Layer, thickness is 100-300 nm.
Preferably, insulating materials is filled with the groove 101, insulating materials can be SiO2Deng with insulation characterisitic
Material, can so be further ensured that groove 101 has the effect of cut-off electric current.The depth of the groove 101 is 4-6um, groove
101 width is 3-8um.
Preferably, in order to improve the luminosity of flip LED chips, can select to deposit on conductive layer 16 one layer it is anti-
Layer 17 is penetrated, the material in reflecting layer 17 can be Ag, Al either DBR（Bragg reflecting layer）.Further, the reflecting layer 17
On can also be provided with protective layer 19, for protecting reflecting layer 17, the Eutectic Layer 20 is located above protective layer 19, protective layer can be with
For SiO2Layer, thickness is 300-600 um.
As shown in figure 11, another aspect of the present invention also provides a kind of LED core chip package, including substrate 200 and above
Electrode is provided with described LED chip 100, the substrate 200, the LED chip 100 is upside down on substrate 200, described
One Eutectic Layer 21 and the second Eutectic Layer 22 should be connected with the electrode pair on the substrate 200.Specifically, by the LED completed
The technology that chip 100 is welded using eutectic is upside down on substrate 200 and is packaged, the first Eutectic Layer 21 after the completion of welding and
Two Eutectic Layers 22 need not distinguish both positive and negative polarity, can be directly using exchange electric drive.The inverted structure of the LED chip is due to setting altogether
Crystal layer is conducive to the radiating of LED chip, and the alternating of alternating current current direction in LED chip changes so that chip generates heat more
Uniformly, it is to avoid single region overheat, the life-span of LED chip is extended, the reliability of chip is improved.
The structure of LED chip based on above-mentioned aspect embodiment, with reference to the accompanying drawings 1- Figure 11 descriptions propose a kind of LED core
The preparation method of piece.
The preparation method of the LED chip of the embodiment of the present invention comprises the following steps：
S1, formation epitaxial wafer 10, the epitaxial wafer 10 include substrate 11 and the cushion 12 sequentially formed on the substrate 11, N-type
Semiconductor layer 13, luminescent layer 14 and p type semiconductor layer 15.
Specifically, using sapphire as substrate, using MOCVD（Metal organic chemical vapor deposition）Equipment prepares the outer of LED
Prolong layer, include upwards successively from Sapphire Substrate：Cushion such as gallium nitride, n type semiconductor layer such as N-GaN（N-type is nitrogenized
Gallium）, luminescent layer such as MQW（Multiple-quantum hydrazine layer）Structure, p type semiconductor layer such as P-GaN（P-type gallium nitride）.
S2, formed on epitaxial wafer 10 and be etched to the groove 101 of substrate 11, and the fill insulant in groove 101, institute
State groove 101 and epitaxial wafer 10 is divided into two parts, the both sides of groove 101 set the electricity of first electrode area 110 and second respectively
Polar region domain 120.
Specifically, using ICP（Inductively coupled plasma is etched）Mode linear type groove, ditch are etched on epitaxial wafer
Groove is etched to Sapphire Substrate from P-GaN, then uses insulating materials SiO2Fill groove, it is ensured that the chip insulation of groove both sides,
It is unable to circulating current.Epitaxial wafer is divided into two parts by the groove, defined respectively in the both sides of groove first electrode area and
The second electrode region.In an embodiment of the invention, epitaxial wafer is averagely divided into two parts by groove, and the depth of groove is 4-
6um, the width of groove is 3-8 um.
S3, the first electrode area 110 on epitaxial wafer 10 and the second electrode region 120 form negative electrode hole 102 respectively,
The negative electrode hole 102 is etched to n type semiconductor layer 13.
Specifically, dry etching epitaxial wafer, the first electrode area on epitaxial wafer and second are carried out using ICP etching machines
Electrode zone forms negative electrode hole respectively, exposes n type semiconductor layer.ICP etch periods are about 15 minutes, the quarter in negative electrode hole
Erosion depth is 1.2-1.5 um, and glue is removed in immersion after etching terminates, to remove surface residual photoresist.
S4, the formation conductive layer 16 on p type semiconductor layer 15.
Specifically, using the method for evaporation or sputter coating, transparency conducting layer is made on epitaxial wafer surface, composition is
ITO, the thickness 100-300 nm of conductive layer.Carry out gold-tinted photoetching again after completing ITO plated films, retain the region that needs, it is necessary to
ITO layer is only covered in above P-type semiconductor surface, the groove and does not cover ITO layer, and preferably in negative electrode hole, boundary leaves
3-5 um distance does not have ITO layer.Wet etching, time 10-20 point are carried out to ITO using ITO etching liquids after the completion of photoetching
Clock.After the completion of etching, residual photoresist is removed, then epitaxial wafer is put into annealing furnace annealed, annealing temperature 450-540
DEG C, 30 minutes time.
S5, form the first positive pole 111 respectively on the conductive layer 16 of first electrode area 110 and the second electrode region 120
With the second positive pole 121, it is negative in the negative electrode hole 102 of first electrode area 110 and the second electrode region 120 to form first respectively
The negative pole 122 of pole 112 and second.
Specifically, in gold-tinted condition, photoetching is carried out using negative photoresist, exposing needs the region of plated electrode, then
It is placed in evaporator and makes electrode in conductive layer and negative electrode hole.Electrode material selects Cr/Ti/Au, Ti/ Al, Ti/Au
Deng alloy material, the thickness of electrode is 1.5-2 um.Residual photoresist and residual gold, Ran Houyong are removed after the completion of electrode fabrication
Annealing furnace is in N2Annealed alloy processing is carried out under atmosphere to electrode, annealing time is 16 minutes, and temperature is 300-350 DEG C.
S6, the formation insulating barrier 18 on the side wall in negative electrode hole 102.
Specifically, the insulating barrier is located between negative electrode hole side wall and the first negative electrode or the second negative electrode, described exhausted
The material of edge layer can be SiO2。
S7, formation Eutectic Layer 20, the Eutectic Layer 20 include the first Eutectic Layer 21 and the second Eutectic Layer 22, and described first is total to
Crystal layer 21 forms in first electrode area 110 and covers the first positive pole 111 and the first negative pole 121, the shape of the second Eutectic Layer 22
Into in the second electrode region 120 and the second positive pole 121 of covering and the second negative pole 112.
Specifically, under the conditions of gold-tinted, photoetching is carried out using negative photoresist, expose needs to plate Eutectic Layer on epitaxial wafer
Region, then epitaxial wafer is placed in evaporator and makes Eutectic Layer, residual photoresist and residual gold are removed after the completion of evaporation.
So far LED chip is completed to make.The material of Eutectic Layer selects conductive material, such as from Cr/Ti/Au, Ti/ Al, Ti/
One kind in the alloys such as Au, the area on Eutectic Layer covering epitaxial wafer surface accounts for the 50%-70% of epitaxial wafer total surface area.In this hair
In bright embodiment, the thickness of Eutectic Layer is 0.8-1.5 um, positioned at epitaxial wafer both sides the first Eutectic Layer and the second Eutectic Layer it
Between spacing distance 50-200 um, the Edge Distance 20-40um of Eutectic Layer and epitaxial wafer.
Further, after the completing of step S5 positive and negative electrodes, in addition to step S51, on conductive layer 16 successively
Form reflecting layer 17 and protective layer 19.
Specifically, using gold-tinted photoetching technique, membrane of conducting layer region is exposed, remaining is covered by photoresist, likewise,
Reflecting layer can not be covered above groove, epitaxial wafer is put into one layer of reflection of deposition in evaporation or sputter coating machine after the completion of photoetching
Layer, reflector thickness is 50-150nm, and the material in reflecting layer can be Ag, Al either DBR（Bragg reflecting layer）.Then adopt
Use PECVD（Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition）If
Standby, 300 DEG C of cavity temperature deposits one layer of SiO on completed LED chip surface2Protective layer, protective layer thickness is 300-600
um.Then the photoetching under gold-tinted environment, wet etching falls the SiO of electrode contact locations2Protective layer, that is, SiO2Layer covering LED
All regions of the chip in addition to both positive and negative polarity, after the completion of immersion go glue remove residual photoresist.It should be noted that because of protective layer and
Insulating barrier can use the insulating barrier in identical material, step S6 together to be formed while protective layer is made.
The present invention also provides a kind of preparation method of LED core chip package, including：
There is provided and be provided with electrode on substrate 200, the substrate 200,；
The above-mentioned LED chip 100 completed is upside down on substrate 200, by the Eutectic Layer of the first Eutectic Layer 21 and second
22 should be connected with the electrode pair on substrate 200.
Specifically, the technology LED chip completed welded using eutectic is upside down on substrate and is packaged, welding
After the completion of the first Eutectic Layer and the second Eutectic Layer need not distinguish both positive and negative polarity, can directly using exchange electric drive.The LED chip
Inverted structure due to setting Eutectic Layer to be conducive to the radiating of LED chip, and the friendship of alternating current current direction in LED chip
Cause chip heating evenly for change, it is to avoid single region overheat, extend the life-span of LED chip, improve the reliable of chip
Property.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or the spy that the embodiment or example are described
Point is contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be any
One or more embodiments or example in combine in an appropriate manner.
Although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of changes, modification can be carried out to these embodiments, replace without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is by appended claims and its equivalent limits.
Claims (10)
1. a kind of LED chip, it is characterised in that including：
Have on epitaxial wafer, the epitaxial wafer in first electrode area and the second electrode region, the first electrode area and be provided with
The second positive pole and the second negative pole are provided with first positive pole and the first negative pole, the second electrode region；The epitaxial wafer is provided with
For the groove of electric isolution, first positive pole and the second negative pole are located at the side of the groove, first negative pole and second
Positive pole is located at the opposite side of the groove；
Eutectic Layer, the Eutectic Layer includes the first Eutectic Layer and the second Eutectic Layer, and first Eutectic Layer is arranged at first electrode
Region simultaneously covers the first positive pole and the first negative pole, second Eutectic Layer be arranged at the second electrode region and cover the second positive pole and
Second negative pole.
2. LED chip as claimed in claim 1, it is characterised in that also including conductive layer；The epitaxial wafer includes substrate, position
In the cushion of substrate, n type semiconductor layer, luminescent layer and p type semiconductor layer, the conductive layer is located at p type semiconductor layer
On, first positive pole and the second positive pole set on the electrically conductive and electrically connected with conductive layer；The first electrode area and
The second electrode region is provided with the negative electrode hole for extending to n type semiconductor layer, and first negative pole and the second negative pole are arranged on negative
Electrically connect, be provided between the side wall and the first negative pole and the second negative pole in the negative electrode hole in electrode hole and with n type semiconductor layer
Insulating barrier.
3. LED chip as claimed in claim 2, it is characterised in that the depth of the groove extends to substrate.
4. LED chip as claimed in claim 1, it is characterised in that insulating materials is filled with the groove.
5. LED chip as claimed in claim 2, it is characterised in that reflecting layer, protection are also sequentially provided with the conductive layer
Layer, the Eutectic Layer is located on protective layer.
6. LED chip as claimed in claim 1, it is characterised in that the area on the Eutectic Layer covering epitaxial wafer surface accounts for outer
Prolong the 50%-70% of piece total surface area.
7. LED chip as claimed in claim 1, it is characterised in that the material of the Eutectic Layer be Cr/Ti/Au, Ti/ Al or
One kind in Ti/Au alloys.
8. a kind of LED core chip package, it is characterised in that including：
Electrode is provided with substrate, the substrate；
LED chip as described in claim any one of 1-7, the LED chip is inverted on the substrate, first eutectic
Layer and the second Eutectic Layer should be connected with the electrode pair on the substrate.
9. a kind of preparation method of LED chip, it is characterised in that including：
Epitaxial wafer is formed, the epitaxial wafer includes substrate and the cushion sequentially formed on substrate, n type semiconductor layer, lighted
Layer and p type semiconductor layer；
The groove for being etched to substrate, and the fill insulant in groove are formed on epitaxial wafer, the groove divides epitaxial wafer
Two parts are segmented into, the both sides of groove are respectively formed with first electrode area and the second electrode region；
First electrode area and the second electrode region on epitaxial wafer form negative electrode hole respectively, and the negative electrode hole is etched to
N type semiconductor layer；
Conductive layer is formed on p type semiconductor layer；
The first positive pole and the second positive pole are formed respectively on the conductive layer of first electrode area and the second electrode region, in the first electricity
The first negative pole and the second negative pole are formed respectively in polar region domain and the negative electrode hole of the second electrode region；
Insulating barrier is formed on the side wall in negative electrode hole；
Eutectic Layer is formed, the Eutectic Layer includes the first Eutectic Layer and the second Eutectic Layer, and the first Eutectic Layer formation is first
Electrode zone simultaneously covers the first positive pole and the first negative pole, and the second Eutectic Layer formation is in the second electrode region and covers second just
Pole and the second negative pole.
10. the preparation method of LED chip as claimed in claim 9, it is characterised in that in first electrode area and second electrode
The negative electrode hole of the first positive pole and the second positive pole, first electrode area and the second electrode region is formed on the conductive layer in region respectively
It is middle to be formed respectively after the first negative pole and the second negative pole, in addition to：
Reflecting layer and protective layer are sequentially formed on the electrically conductive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610197321.4A CN107293626A (en) | 2016-03-31 | 2016-03-31 | LED chip, LED core chip package and preparation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610197321.4A CN107293626A (en) | 2016-03-31 | 2016-03-31 | LED chip, LED core chip package and preparation method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110012137A1 (en) * | 2004-08-31 | 2011-01-20 | Industrial Technology Research Institute | Structure of ac light-emitting diode dies |
| CN202487570U (en) * | 2012-01-16 | 2012-10-10 | 徐志锋 | Positive and negative pole reversal connection parallel LED packaging structure |
| CN203674215U (en) * | 2014-01-07 | 2014-06-25 | 圆融光电科技有限公司 | Light emitting diode |
-
2016
- 2016-03-31 CN CN201610197321.4A patent/CN107293626A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110012137A1 (en) * | 2004-08-31 | 2011-01-20 | Industrial Technology Research Institute | Structure of ac light-emitting diode dies |
| CN202487570U (en) * | 2012-01-16 | 2012-10-10 | 徐志锋 | Positive and negative pole reversal connection parallel LED packaging structure |
| CN203674215U (en) * | 2014-01-07 | 2014-06-25 | 圆融光电科技有限公司 | Light emitting diode |
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Application publication date: 20171024 |