KR101281081B1 - Vertical Light emitting diode cell array and method of manufacturing the same - Google Patents

Abstract

The present invention relates to an LED cell array and a method of manufacturing the same, the support substrate having an insulating layer, a plurality of first conductive patterns provided on the insulating layer spaced apart from each other, and provided on the plurality of first conductive patterns, respectively And a plurality of second unit electrically connecting the plurality of vertical unit light emitting cells including the P-type semiconductor layer, the active layer, and the N-type semiconductor layer, and the plurality of first conductive patterns and the plurality of vertical unit light emitting cells adjacent to each other. A vertical LED cell array including a conductive pattern and a method of manufacturing the same are presented.

Description

Vertical light emitting diode cell array and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode cell array, and more particularly, to a vertical light emitting diode cell array and a method of manufacturing the same, which operate at high voltage and low current.

Light emitting diodes (LEDs) are photoelectric conversion elements that emit light by applying a forward current to both ends of a P-N junction. In general, LEDs are released into commercial products in the form of modules through epi wafer fabrication process, chip production process, packaging process and module process. Recently, as LEDs are applied to devices requiring high power, such as lighting fixtures, researches on LEDs are being actively conducted in the field of increasing the efficiency of LEDs such as internal quantum efficiency and light extraction efficiency.

In an effort to increase the efficiency of LEDs, vertical LED structures have been developed in which two electrodes are placed above and below the semiconductor layer. Vertical LEDs include a P-type semiconductor layer, an active layer, and an N-type semiconductor layer sequentially disposed on a support substrate that is a conductor. The vertical LED includes an N-type electrode layer disposed above the N-type semiconductor layer and a P-type electrode layer disposed below the P-type semiconductor layer as the electrode layer.

In such a vertical LED structure, the current flows in the vertical direction according to the voltage provided from the outside, so the current flows well. Therefore, the current uniformity is relatively good in the active layer region and the light emission characteristic to the upper surface N-type semiconductor layer is relatively higher than that of the horizontal LED structure. Accordingly, in applications such as LED lighting requiring high power, efforts have been continuously made to employ vertical LED structures.

On the other hand, vertical LEDs typically operate at a driving voltage of 5V or less in a single chip state, and receive driving voltages and driving currents from separate driving units. The conventional driving unit for driving a vertical LED includes a converter for converting direct current from alternating current to apply alternating current power, and a dc / dc converter for lowering the converted direct current power to a level applied to the vertical led. However, when converting DC power in the DC / DC converter, a problem of lowering conversion efficiency may occur. In addition, high current is provided to the vertical LEDs to increase reactive power lost to heat.

In addition, in the field of LED lighting, and the like to try to obtain a more efficient product by connecting a plurality of vertical LED in series. Connecting a vertical LED in series has the advantage of lowering the energy loss consumed by heat by maintaining a DC voltage of a high voltage and a low current relative to a single vertical LED. However, there is a limit to the number of vertical LEDs that can be mounted in a package with a limited volume. In addition, there is a difficulty that the process of forming the package is complicated.

Korean Patent Laid-Open Publication No. 2009-0038193 discloses a vertical light emitting device that can be driven by an AC power source by connecting a plurality of light emitting device cells in series. This prior patent forms a thick N-type semiconductor layer, and proceeds with the primary etching process for defining the unit cell and the secondary etching process for exposing the N-type semiconductor layer. Therefore, since the etching process increases, there is a problem that the process becomes complicated. In addition, the prior patent has a problem that the light emitting area is reduced because a pad is provided on one of the light emitting cells, that is, the outermost light emitting cells, and light is not emitted from the light emitting cells. In addition, since the unit cells are embedded between the unit cells to separate the unit cells, an insulation layer forming process may be added, thereby increasing the complexity of the process. As described above, the prior patent has many problems such as complicated process and low luminous efficiency.

The present invention provides a vertical LED cell array operating at high voltage and low current and a method of manufacturing the same.

The present invention provides a vertical LED cell array and a method of manufacturing the same that can minimize the reduction of the light emitting area and improve the light emitting efficiency.

Vertical LED cell array according to an embodiment of the present invention comprises a support substrate having an insulating layer; A plurality of first conductive patterns spaced apart from each other on the insulating layer; A plurality of vertical unit light emitting cells each provided on the plurality of first conductive patterns, the plurality of vertical unit light emitting cells including a P-type semiconductor layer, an active layer, and an N-type semiconductor layer; And a plurality of second conductive patterns electrically connecting the plurality of first conductive patterns and a plurality of adjacent vertical unit light emitting cells.

Each of the plurality of first conductive patterns is provided to correspond to each of the plurality of vertical unit light emitting cells, and a portion of the plurality of vertical unit light emitting cells is exposed to the outside of the vertical unit light emitting cell.

The semiconductor device may further include at least one of an ohmic contact layer pattern and a reflective metal layer pattern provided between the P-type semiconductor layer and the plurality of first conductive patterns.

The first conductive pattern is formed to surround the reflective metal layer pattern, and the reflective metal layer pattern is formed to surround the ohmic contact layer pattern.

The insulating layer further includes a contact portion electrically connecting the support substrate and a portion of the first conductive pattern to each other.

The apparatus further includes a eutectic metal layer provided between the insulating layer and the support substrate.

The eutectic metal layer is formed to bury the contact portion.

The eutectic metal layer uses an alloy of Au and Sn.

The adhesive layer may further include an adhesive layer formed between the insulating layer and the eutectic metal layer, and between the eutectic metal layer and the support substrate.

The adhesive layer uses at least one of Ti, Cr, and Ni.

According to another aspect of the present invention, a method of manufacturing a vertical LED cell array includes sequentially forming an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on a growth substrate; Forming a plurality of first conductive patterns on the P-type semiconductor layer; Forming an insulating layer and a support substrate over the entirety including the plurality of first conductive patterns; Separating the growth substrate from the N-type semiconductor layer; Forming a plurality of vertical unit light emitting cells by patterning the N-type semiconductor layer, the active layer, and the P-type semiconductor layer so that a portion of the first conductive pattern is exposed; And forming a plurality of second conductive patterns electrically connecting a portion of the N-type semiconductor of the plurality of vertical unit light emitting cells and the plurality of first conductive patterns to each other.

The method may further include forming at least one of an ohmic contact layer pattern and a reflective electrode layer pattern on the P-type semiconductor layer prior to forming the first conductive pattern.

The first conductive pattern is formed to surround the reflective electrode layer pattern, and the reflective electrode layer pattern is formed to surround the ohmic contact layer pattern.

The insulating layer is formed to include a contact portion exposing at least one of the first conductive patterns.

In the forming of the supporting substrate on the insulating layer, after forming a eutectic metal layer on each of the insulating layer and the supporting substrate, the eutectic metal layer is bonded.

The eutectic metal layer is formed to bury the contact portion.

And forming a first adhesive layer between the insulating layer and the eutectic metal layer, and forming a second adhesive layer between the eutectic metal layer and the support substrate.

The first adhesive layer is formed on the insulating layer and the eutectic metal layer, respectively, and then bonded to each other, and the second adhesive layer is formed on the eutectic metal layer and the support substrate, respectively, and then bonded to each other.

The forming of the second conductive pattern may include forming an insulating layer pattern exposing a portion of the N-type semiconductor layer of the plurality of unit light emitting cells; And forming a conductive thin film on the entire upper portion and patterning the conductive thin film to be connected to the first conductive pattern below the other unit light emitting cell from the N-type semiconductor layer of the one unit light emitting cell.

According to embodiments of the present invention, there is provided a vertical LED cell array in which a plurality of unit light emitting cells, which are vertical LEDs, are connected in series. Since the vertical LEDs emit most of the light toward the upper surface of the device, when a cell array including the vertical LEDs as the unit light emitting cells is configured, light reabsorption between neighboring unit light emitting cells can be prevented and the light emission efficiency can be maximized. In addition, there is an advantage that the size of the DC power provided to the unit light emitting cell can be adjusted by changing the number of unit light emitting cells constituting the LED cell array. In addition, compared to the conventional single vertical LED chip, the power provided to the vertical unit light emitting cell maintains a relatively high voltage and low current state, thereby increasing the light conversion efficiency while reducing energy loss consumed by heat when high current flows. It has the advantage of being.

In addition, according to embodiments of the present invention, the vertical LED cell array is formed in the chip production process step through the semiconductor process. By applying the semiconductor process, a plurality of mounted vertical unit light emitting cells can be integrally formed, and the number of vertical unit light emitting cells can be more easily adjusted. When the serial connection is performed during the packaging process, an additional process such as wiring and LED chip bonding, which is required, is simplified, thereby simplifying the process.

In addition, the structure and the process can be simplified and the light emitting cells can be increased as compared with the conventional vertical LED cell array.

1 is a schematic diagram of an LED cell array in accordance with one embodiment of the present invention.
2 to 7 are cross-sectional views in order of a process for explaining a method of manufacturing a vertical LED cell array according to an embodiment of the present application.
8 is a schematic plan view of a vertical LED cell array in accordance with one embodiment of the present invention.
9 is a view schematically illustrating an example of a driver for driving a vertical LED cell array according to an embodiment of the present invention.
10 to 14 are cross-sectional views in order of a process for explaining a method of manufacturing a vertical LED cell array according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the thickness is enlarged to clearly illustrate the various layers and regions, and the same reference numerals denote the same elements in the drawings. Also, where a portion such as a layer, film, region, or the like is referred to as being "on top" or "on" another portion, it is not necessarily the case that each portion is "directly above" And the case where there is another part between the parts.

In addition, the terms of the vertical LED, the vertical unit light-emitting cell, the vertical light-emitting cell used in the present specification, the N-type electrode and the P-type electrode of the LED element is the upper portion of the N-type semiconductor layer and the P-type semiconductor layer of the LED element It means an LED, a unit light emitting cell or a light emitting cell structure respectively disposed below, and is interpreted as a structure that is different from a conventional horizontal LED.

1 is a view schematically showing an LED cell array according to an embodiment of the present invention. The LED cell array 100 includes a plurality of unit light emitting cells 110, and at least some of the plurality of unit light emitting cells 110 are electrically connected in series. Referring to FIG. 1A, the unit light emitting cell 110 is a vertical LED, and a plurality of unit light emitting cells 110 are connected to each other in series. In the drawing, six unit light emitting cells 110 are illustrated for convenience, but the present invention is not limited thereto. The driver 120 supplies DC power to drive the LED cell array 100. The size of the DC power provided to the unit light emitting cell 110 may be adjusted by changing the number of unit light emitting cells 110 constituting the LED cell array 100. As an example, when six unit light emitting cells 110 are connected in series when a DC power of about 240 V is supplied, a DC voltage of about 40 V may be supplied to each of the unit light emitting cells 110. As another example, when 12 unit light emitting cells 110 are connected in series, a DC voltage of about 20 V may be supplied to each of the unit light emitting cells 110. Referring to FIG. 1B, the unit light emitting cells 110 are vertical LEDs, at least some of the plurality of unit light emitting cells 110 are connected in series with each other, and other portions are connected in parallel. For convenience, the two unit light emitting cells 110 are connected in parallel to form one light emitting unit, and the three light emitting units are connected to each other in series. The number and the number of light emitting units are not limited thereto. The driver 120 supplies DC power to drive the LED cell array 150. The size of the DC power supplied to the unit light emitting cell 110 may be adjusted by changing the number of light emitting units connected in series constituting the LED cell array 100. As an example, when a DC power of about 240V is supplied, two unit light emitting cells 110 may be connected in parallel to each other to form one light emitting unit. In addition, the three light emitting units may be connected to each other in series. In this case, a voltage of about 80 V is applied to each light emitting unit, and thus, a voltage of about 80 V may be applied to each of the unit light emitting cells 110 connected in parallel. As described above, a DC voltage having a relatively high voltage may be applied to each of the unit light emitting cells 110 as compared with the related art.

Accordingly, the driver 120 may not include a DC / DC converter compared to the conventional driver, or may reduce the loss of conversion by lowering the burden of the DC / DC converter even when the DC / DC converter is provided. In addition, compared to the conventional single vertical LED chip, the vertical LED cell array of the present embodiment has a relatively high voltage and low current state of power provided to the vertical unit light emitting cell, so that energy loss consumed by heat when high current flows is reduced. Is reduced.

According to an embodiment of the present invention, a plurality of unit light emitting cells, which are vertical LEDs, are disposed, and an LED cell array in which at least a portion of the plurality of unit light emitting cells is connected in series is manufactured on a substrate. An LED cell array including a plurality of vertical unit light emitting cells forms a single light emitting device chip. Since the vertical LEDs emit most of the light toward the upper surface of the device, when a cell array including the vertical LEDs as the unit light emitting cells is configured, light reabsorption between neighboring unit light emitting cells can be prevented and the light emission efficiency can be maximized. In addition, since the current flow of the unit light emitting cell is vertical, electrical characteristics such as withstand voltage or current spreading are good. The packaging process is relatively simple by using one wire in the packaging process.

Meanwhile, a single light emitting device chip is formed in a chip production step through a semiconductor process described later. In general, the manufacturing process of the LED chip is composed of epi wafer manufacturing step, chip production step, packaging step and module step, LED cell array in one embodiment of the present invention is manufactured in the chip production step Compared to mounting vertical LED chips in series at package stage, the number of mounted vertical LED chips can be adjusted more easily, and no additional process such as wiring and LED chip bonding applied during the packaging process is required. There is an advantage that the process is simplified.

Hereinafter, a method of manufacturing a vertical LED cell array according to an embodiment of the present invention will be described.

2 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a vertical LED cell array according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 are sequentially formed on the growth substrate 210. When the growth substrate 210 is a sapphire single crystal substrate, the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 may use gallium nitride (GaN) -based compound semiconductors having different doping levels. have. In addition, when the growth substrate 210 is a GaP single crystal substrate, the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 may be formed of an aluminum gallium indium (AlGaInP) compound semiconductor having different doping levels. It is available. In addition to the above materials, the growth substrate 210, the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 may be applied with various known materials constituting a light emitting device.

Referring to FIG. 3, a plurality of first conductive patterns 250 are formed on the P-type semiconductor layer 240 of the growth substrate 210. The plurality of first conductive patterns 250 may be patterned to be spaced apart from each other. For example, the process of forming the plurality of first conductive patterns 250 may include the process of forming a plurality of P-type ohmic contact layer patterns (not shown) in electrical contact with the P-type semiconductor layer 240 and the plurality of Ps. Forming a plurality of reflective metal layer patterns on the type ohmic contact layer. The plurality of reflective metal layer patterns perform a function of re-reflecting light incident to a plurality of vertical unit light emitting cells formed thereafter.

The process of forming the plurality of first conductive patterns 250 on the P-type semiconductor layer 240 is performed by depositing a conductive thin film on the P-type semiconductor layer 240 and patterning the conductive thin film using a lithography and etching process. Can be achieved. Lithography and etching processes can be applied to a variety of known methods, so the detailed description thereof will be omitted.

Referring to FIG. 4, an insulating layer 260 and a support substrate 270 are formed on the plurality of first conductive patterns 250. The insulating layer 260 may be achieved by forming an insulating film on the plurality of first conductive patterns 250 and the P-type semiconductor layer 240. In this case, as illustrated, the contact portion 265 may be formed by partially etching the insulating layers 260 formed on the plurality of first conductive patterns 250 and the P-type semiconductor layer 240. The contact portion 265 electrically connects a portion of the supporting substrate 270 formed thereafter and a portion of the plurality of first conductive patterns 250 to each other. In addition, the insulating layer 260 may be formed using nitride or oxide, and at least one of Si ₃ N ₄ , SixNy (0 ≦ x ≦ 2, 0 ≦ y ≦ 1), and amorphous Al ₂ O ₃ may be used. It is also possible to use ceramic materials such as AlN. At this time, Si ₃ N ₄ is the most preferable because it uses the best adhesion.

The support substrate 270 is formed on the plurality of first conductive patterns 250 and the insulating layer 260. The support substrate 270 may use a metal or a semiconductor, or may use an insulator. The insulator used as the support substrate 270 may be a material having a heat transfer coefficient of 50 W / m · K or more. Meanwhile, the support substrate 270 may be formed by coating or depositing a conductive or semiconductor material on the plurality of first conductive patterns 250 and the insulating layer 260 using known wet and dry semiconductor processes. In addition, the support substrate 250 may be separately prepared and bonded to the plurality of first conductive patterns 250 and the insulating layer 260. In this case, a eutectic metal may be applied as a medium to the junction between the supporting substrate 250, the plurality of first conductive patterns 250, and the insulating layer 260.

Referring to FIG. 5, the growth substrate 210 is separated from the N-type semiconductor layer 220 on the support substrate 270. A laser lift off (LLO) or chemical lift off (CLO) process may be applied to separate the growth substrate 210 from the N-type semiconductor layer 220.

Referring to FIG. 6, a plurality of vertical unit light emitting cells 280 electrically insulated from each other by patterning the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 on the support substrate 270. To form. That is, a space 285 is provided between the plurality of vertical unit light emitting cells 280 to insulate the spaces therebetween. The patterning process is performed such that the plurality of vertical unit light emitting cells 280 are electrically insulated from each other by performing an etching process to partially expose the first conductive pattern 250 and the insulating layer 260. Therefore, the plurality of vertical unit light emitting cells 280 and the plurality of first conductive patterns 250 corresponding thereto are electrically connected to the support substrate 270. In this case, the first conductive pattern 250 is formed at least the same size as the vertical unit light emitting cell 280. That is, the first conductive pattern 250 is formed to be larger than or the same size as the unit light emitting cell 280, and a portion of the first conductive pattern 250 is exposed to the outside of the unit light emitting cell 280. As the size of the first conductive pattern 250 increases, the contact area between the vertical unit light emitting cell 280 and the support substrate 270 increases, thereby improving current spreading into the vertical unit light emitting cell 280. . In this case, the size of the first conductive pattern 250 may be adjusted within a range not overlapping with the adjacent vertical unit light emitting cell 280.

Referring to FIG. 7, a plurality of second conductive patterns 295 electrically connecting a portion of the N-type semiconductor 220 of the plurality of vertical unit light emitting cells 280 and the plurality of first conductive patterns 250 to each other. To form. Here, the plurality of second conductive patterns 295 includes a plurality of vertical unit light emitting cells neighboring any one of the plurality of first conductive patterns 250 on which one of the plurality of vertical unit light emitting cells 280 is disposed. Electrical connection with the other of 280. Therefore, at least a portion of the plurality of vertical unit light emitting cells 280 are electrically connected to each other in series.

A process of forming the plurality of second conductive patterns 295 will be described. An insulating film is formed on the plurality of vertical unit light emitting cells 280 of the support substrate 270, and the insulating film is etched to form a plurality of vertical unit light emission. An insulating layer pattern 290 exposing a portion of the N-type semiconductor layer 220 of the cell 280 is formed. Subsequently, a conductive thin film is formed to cover a portion of the N-type semiconductor layer 220, the insulating layer pattern 290, and the plurality of first conductive patterns 250 of the plurality of unit light emitting cells 280 exposed on the support substrate 270. In addition, the conductive thin film may be patterned such that at least a portion of the plurality of vertical unit light emitting cells 280 are electrically connected in series. In this way, the plurality of vertical unit light emitting cells 280 are separated by the separation space 285 and insulated by the insulating film pattern 290, thereby simplifying the insulating film structure and the forming process thereof.

8 is a plan view schematically illustrating a vertical LED cell array according to an embodiment of the present invention. As shown in the drawing, the vertical LED cell array 1100 is disposed on the support substrate 270 having the insulating layer 260 and a plurality of spaced apart from each other on the insulating layer by the manufacturing method illustrated in FIGS. 2 to 7. The first conductive pattern 250 includes a plurality of vertical unit light emitting cells 280 and a plurality of second conductive patterns 295 disposed on the plurality of first conductive patterns 250, respectively. The plurality of second conductive patterns 295 may include any one of the plurality of first conductive patterns 250 in which one of the plurality of vertical unit light emitting cells 280 is disposed. Electrically connect with another neighbor. As a result, at least some of the plurality of vertical unit light emitting cells 280 are electrically connected in series with each other.

FIG. 9 is a diagram schematically illustrating an example of a driving unit for driving a vertical LED cell array according to an embodiment of the present invention, which is an internal block diagram of the driving unit 1200. According to an embodiment of the present invention, the AC power supply 1210 is a vertical LED cell via the EMI filter 1220, full-wave rectifier circuit 1230, clamping circuit 1240, smoothing circuit 1250 and the constant current supply unit 1260. The array 1270 is provided with a direct current power source. The vertical LED cell array is composed of a plurality of vertical unit light emitting cells 1275. The size of the direct current power provided to each of the plurality of vertical unit light emitting cells 1275 is vertically connected in series in the LED cell array 1270. The number of type unit light emitting cells 1275 may be adjusted. Although the drawings show that the two vertical unit light emitting cells 1275 are connected in series for convenience of description, the number of the vertical unit light emitting cells 1275 connected in series may be changed without being limited thereto. As an example, when a DC power of about 240V is supplied, when six unit light emitting cells 1275 are connected in series, a DC voltage of about 40V may be supplied to each of the unit light emitting cells 1275. As another example, when 12 unit light emitting cells 1275 are connected in series, a DC voltage of about 20 V may be supplied to each of the unit light emitting cells 1275. As another example, a direct current power of about 240V is supplied, and as shown in FIG. 1B, two unit light emitting cells 410 are connected in parallel to each other to form one light emitting unit, and three light emission units are provided. The units can be connected in series with each other. In this case, a voltage of about 80 V is applied to each light emitting unit, and thus, a voltage of about 80 V may be applied to each of the unit light emitting cells 410 connected in parallel. As described above, a DC voltage having a relatively high voltage may be applied to each of the unit light emitting cells 410 as compared with the related art.

Therefore, the driver 1200 according to an exemplary embodiment of the present invention may not include a DC / DC converter as compared to the conventional driver. In addition, although the driving unit 1200 may include a DC / DC converter, in this case, the burden of the DC / DC converter may be lowered to reduce the conversion loss rate. In addition, compared to the conventional single vertical LED chip, the vertical LED cell array 1270 according to the present invention is because the power provided to the vertical unit light-emitting cell 1275 is a relatively high voltage and low current state, the high current is provided There is an advantage that the energy dissipated by the heat generated when is reduced.

10 to 14 are cross-sectional views in order of a process for explaining a method of manufacturing a vertical LED cell array according to another embodiment of the present invention. In the following description of the overlapping content and the manufacturing method of an embodiment of the present invention will be omitted.

Referring to FIG. 10, the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 are sequentially formed on the growth substrate 210. Subsequently, a plurality of ohmic contact layer patterns 310, a reflective metal layer pattern 320, and a first conductive pattern 250 spaced apart from each other are formed in a predetermined region on the P-type semiconductor layer 240. Here, only one of the ohmic contact layer pattern 310 or the reflective metal layer pattern 320 may be formed.

The ohmic contact layer pattern 310 is formed to facilitate ohmic contact between the P-type semiconductor layer 240 and the reflective metal layer 320. The ohmic contact layer pattern 310 may be formed of metal oxide, Ni / Au, or Pd / Ag. have. In addition, the reflective metal layer pattern 320 performs a function of re-reflecting light incident to the plurality of vertical unit light emitting cells, and may be formed of Al, Ag, or an alloy thereof. Meanwhile, the ohmic contact layer pattern 310, the reflective metal layer pattern 320, and the first conductive pattern 250 may be formed in different sizes and patterns, but the reflective metal layer pattern 320 may be formed rather than the ohmic contact layer pattern 310. The first conductive pattern 250 may be greater than or equal to and greater than or equal to the reflective metal layer pattern 320. To this end, the ohmic contact layer is formed and then patterned by a predetermined lithography process and an etching process to form an ohmic contact layer pattern 310, and after forming the reflective metal layer, the ohmic contact layer pattern 310 by a predetermined lithography process and an etching process. The reflective metal layer pattern 320 may be formed by patterning the same as or greater than). Subsequently, after the conductive layer is formed, the first conductive pattern 250 may be formed by patterning the conductive layer greater than or equal to the reflective metal layer 320 by a predetermined lithography process and an etching process. In this case, the reflective metal layer pattern 320 may be formed larger than the ohmic contact layer pattern 310, and the first conductive pattern 250 may be formed larger than the reflective metal layer pattern 320. Accordingly, the reflective metal layer pattern 320 is formed to surround the ohmic contact layer pattern 310, and the first conductive pattern 250 is formed to surround the reflective metal layer pattern 320. By forming the lower layer so as to surround the upper layer, it is possible to prevent the metal migration phenomenon and surface morphology deformation generated at the interface between the lower layer and the upper layer by the heat of the subsequent process. That is, the ohmic contact layer pattern 310 may be dissolved by the thermal process, and thus, metal migration and deformation of the surface morphology may occur at the interface between the reflective metal layer pattern 320 and the ohmic contact layer pattern 310. In this case, the ohmic contact layer pattern 310 may be formed to surround the reflective metal layer pattern 320, thereby preventing the ohmic contact layer pattern 310. In addition, the ohmic contact layer pattern 310 or the reflective metal layer pattern 320 may be dissolved by a thermal process, and thus deformation of the surface morphology may be caused at the interface between the first conductive pattern 250 and the reflective metal layer pattern 320. The reflective metal layer pattern 320 may be formed to surround the first conductive pattern 320, thereby preventing the reflective metal layer pattern 320.

Referring to FIG. 11, an insulating layer 260, an eutectic metal layer 330, and a support substrate 270 are formed on the entire top including the plurality of first conductive patterns 250. The insulating layer 260 may partially form the contact portion 265 to expose one region of the first conductive pattern 250. In addition, the eutectic metal layer 330 is formed on the insulating layer 260 including the contact portion 265, and the eutectic metal layer 330 may be formed of, for example, an alloy of Au and Sn. In this case, the contact portion 265 may be formed to have a narrow width, whereby the contact portion 265 is buried by the eutectic metal layer 330. Of course, the contact portion 265 may be buried by the support substrate 270 instead of being buried by the eutectic metal layer 330. The eutectic metal layer 330 allows the insulating layer 260 and the support substrate 270 to be firmly bonded to each other, and at the same time, fills the contact portion 265. Here, in order to bond the insulating layer 260 and the support substrate 270 by the utero metal layer 330, one side of the insulating layer 260 and the one surface of the support substrate 270 adhered to each other may be used. After the 330 is formed, the two eutectic metal layers 330 are bonded to each other. Meanwhile, an adhesive layer (not shown) may be formed between the eutectic metal layer 330 and the insulating layer 260, and an adhesive layer (not shown) may be formed between the eutectic metal layer 330 and the support substrate 270. That is, since the adhesive strength between the eutectic metal layer 330 and the insulating layer 260, and the eutectic metal layer 330 and the support substrate 270 may be lowered, an adhesive layer may be formed to improve their adhesive strength. Even when the adhesive layer is formed, an adhesive layer is formed on one surface of the insulating layer 260 and one surface of the eutectic metal layer 330 which are bonded to each other, and then the two adhesive layers are adhered to each other. In addition, an adhesive layer is formed on one surface of the eutectic metal layer 330 and one surface of the support substrate 270 to be bonded to each other, and then the two adhesive layers are adhered to each other. At this time, the adhesive layer may be used Ti, Cr, Ni and the like.

Referring to FIG. 12, the growth substrate 210 is separated from the N-type semiconductor layer 220 using a lift process.

Referring to FIG. 13, a plurality of vertical unit light emitting cells 280 electrically insulated from each other by patterning the N-type semiconductor layer 220, the active layer 230, and the P-type semiconductor layer 240 on the support substrate 270. To form. In this case, the patterning process is performed so that the plurality of vertical unit light emitting cells 280 are electrically insulated from each other by performing an etching process to partially expose the first conductive pattern 250 and the insulating layer 260. Therefore, the plurality of vertical unit light emitting cells 280 and the plurality of first conductive patterns 250 corresponding thereto are electrically connected to the support substrate 270.

Referring to FIG. 14, a plurality of second conductive patterns 295 electrically connecting portions of the N-type semiconductor 220 of the plurality of vertical unit light emitting cells 280 and the plurality of first conductive patterns 250 to each other. To form. Here, the plurality of second conductive patterns 295 includes a plurality of vertical unit light emitting cells neighboring any one of the plurality of first conductive patterns 250 on which one of the plurality of vertical unit light emitting cells 280 is disposed. Electrical connection with the other of 280. Therefore, at least a portion of the plurality of vertical unit light emitting cells 280 are electrically connected to each other in series.

According to the above-described embodiments of the present invention, a plurality of unit light emitting cells which are vertical LEDs are disposed, and a vertical type LED cell array in which at least a portion of the plurality of unit light emitting cells is connected in series is manufactured on a substrate. In addition, the vertical LED cell array including the plurality of vertical unit light emitting cells forms a single light emitting device chip. Since the vertical LEDs emit most of the light toward the upper surface of the device, when a cell array including the vertical LEDs as the unit light emitting cells is configured, light reabsorption between neighboring unit light emitting cells can be prevented and the light emission efficiency can be maximized. In addition, since the current flow of the unit light emitting cell is vertically implemented, electrical characteristics such as withstand voltage or current spreading are good. In addition, by using one wire in the packaging process, the packaging process is relatively simple.

In addition, the vertical LED cell array according to the embodiments of the present invention is formed in the chip production step through the semiconductor process. Therefore, a plurality of mounted vertical unit light emitting cells can be integrally formed and the number of vertical unit light emitting cells can be more easily adjusted as compared with mounting a vertical LED chip in series in a conventional package process step. have. In addition, an additional process such as wiring and LED chip bonding, which are required when the serial connection is performed during the package process, is not required, thereby simplifying the process.

On the other hand, various embodiments of the present application described above are described for illustrative purposes only, and it will be understood that various modifications may exist without departing from the scope and spirit of the present disclosure. And the various embodiments disclosed are not intended to limit the present disclosure, the true spirit and scope will be presented from the following claims.

100, 150: LED cell array 110: unit light emitting cell
120:
210: growth substrate 220: N-type semiconductor layer
230: active layer 240: P-type semiconductor layer
250: first conductive pattern 260: insulating layer
265: contact portion 270: support substrate
280: vertical unit light emitting cell 290: insulating film pattern
295: second conductive pattern

Claims (19)

A support substrate;
An insulating layer provided on the support substrate;
A plurality of first conductive patterns spaced apart from each other on the insulating layer;
A plurality of vertical unit light emitting cells each provided on the plurality of first conductive patterns, the plurality of vertical unit light emitting cells including a P-type semiconductor layer, an active layer, and an N-type semiconductor layer; And
A plurality of second conductive patterns electrically connecting the plurality of first conductive patterns to a plurality of adjacent vertical unit light emitting cells;
And a contact portion for removing a portion of the insulating layer to electrically connect the support substrate and a portion of the first conductive pattern to each other.
The method of claim 1,
Each of the plurality of first conductive patterns is provided to correspond to each of the plurality of vertical unit light emitting cells, and a vertical type is provided such that a part of the plurality of vertical unit light emitting cells is exposed to the outside of the vertical unit light emitting cell. LED cell array.
The method of claim 1,
And at least one of an ohmic contact layer pattern and a reflective metal layer pattern provided between the P-type semiconductor layer and the plurality of first conductive patterns. The method of claim 3, wherein
And the first conductive pattern is formed to surround the reflective metal layer pattern, and the reflective metal layer pattern is formed to surround the ohmic contact layer pattern.
The method of claim 1,
And the plurality of vertical unit light emitting cells are connected in series.
The method of claim 1,
The vertical type LED cell array further comprises a eutectic metal layer provided between the insulating layer and the support substrate.
The method according to claim 6,
And the eutectic metal layer is formed such that the contact portion is buried. The method of claim 7, wherein
The eutectic metal layer is a vertical type LED cell array using an alloy of Au and Sn.
8. The vertical LED cell array of claim 7, further comprising an adhesive layer formed between the insulating layer and the eutectic metal layer, and between the eutectic metal layer and the support substrate.
The vertical type LED cell array of claim 9, wherein the adhesive layer uses at least one of Ti, Cr, and Ni.
Sequentially forming an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the growth substrate;
Forming a plurality of first conductive patterns on the P-type semiconductor layer;
Forming an insulating layer on an entire top including the plurality of first conductive patterns;
Removing a portion of the insulating layer to form a contact portion exposing at least one of the first conductive patterns;
Forming a support substrate on the insulating layer such that the support substrate is connected to at least one of the first conductive patterns through the contact portion;
Separating the growth substrate from the N-type semiconductor layer;
Forming a plurality of vertical unit light emitting cells by patterning the N-type semiconductor layer, the active layer, and the P-type semiconductor layer so that a portion of the first conductive pattern is exposed; And
Forming a plurality of second conductive patterns electrically connecting a portion of the N-type semiconductor of the plurality of vertical unit light emitting cells and the plurality of first conductive patterns to each other; .
The method of claim 11,
And stacking the ohmic contact layer pattern and the reflective electrode layer pattern on the P-type semiconductor layer and forming the first conductive pattern on the reflective electrode layer pattern.
13. The method of claim 12,
The first conductive pattern is formed to surround the reflective electrode layer pattern, and the reflective electrode layer pattern is formed to surround the ohmic contact layer pattern.
The method of claim 11,
And a plurality of vertical unit light emitting cells are connected in series.
The method of claim 11, wherein forming the support substrate on the insulating layer comprises:
The method of manufacturing a vertical LED cell array to form a eutectic metal layer on the insulating layer and the support substrate, respectively, and then to join the eutectic metal layer.
The method of claim 15, wherein the eutectic metal layer is formed to bury the contact portion.
17. The method of claim 16, further comprising forming a first adhesive layer between the insulating layer and the eutectic metal layer, and forming a second adhesive layer between the eutectic metal layer and the support substrate. .
The method of claim 17, wherein the first adhesive layer is formed on the insulating layer and the eutectic metal layer, and then bonded to each other, and the second adhesive layer is formed on the eutectic metal layer and the support substrate, and then bonded to each other. Method of manufacturing the LED cell array formed.
The method of claim 11,
Forming the second conductive pattern,
Forming an insulating film over the entire surface and patterning the insulating film to expose a portion of the N-type semiconductor layer of the plurality of unit light emitting cells; And
Manufacturing a vertical LED cell array including forming a conductive thin film over the entire surface and patterning the conductive thin film to be connected to the first conductive pattern below the other unit light emitting cell from above the N-type semiconductor layer of the unit light emitting cell Way.

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