WO2015022013A1 - Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component - Google Patents
Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component Download PDFInfo
- Publication number
- WO2015022013A1 WO2015022013A1 PCT/EP2013/066856 EP2013066856W WO2015022013A1 WO 2015022013 A1 WO2015022013 A1 WO 2015022013A1 EP 2013066856 W EP2013066856 W EP 2013066856W WO 2015022013 A1 WO2015022013 A1 WO 2015022013A1
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- WIPO (PCT)
- Prior art keywords
- optoelectronic
- circuit
- contact pad
- semiconductor wafer
- row
- Prior art date
Links
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 436
- 239000004065 semiconductor Substances 0.000 title claims abstract description 142
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 5
- 239000000306 component Substances 0.000 description 115
- 239000002184 metal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Definitions
- the first interconnect is formed by a metallic plating arranged on a surface of the chip die.
- a metallic plating arranged on a surface of the chip die.
- the second contact pad of the second optoelectronic circuit is arranged next to the first contact pad of the third optoelectronic circuit.
- this allows for a space-saving arrangement of the optoelectronic circuits on the chip die. This makes it possible to obtain the optoelectronic component at low production costs.
- the second bond wire 460 provides an electrically conductive connection between the second contact pad 202 of the last optoelectronic circuit 260 and the second bond pad 440.
- the series connection of the optoelectronic circuits 200 of the first semicon- ductor chip die 410 of the first optoelectronic component 400 is thus arranged between the first bond pad 430 and the second bond pad 440 of the first optoelectronic component 400. This allows to use the external contact elements of the first optoelectronic component 400 to electrically contact the se ⁇ ries connection of the optoelectronic circuits 200 of the first semiconductor chip die 410 of the first optoelectronic component 400.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Led Device Packages (AREA)
Abstract
A semiconductor wafer comprises a first row of optoelectronic circuits. The first row comprises a first optoelectronic circuit and a second optoelectronic circuit. The semiconductor wafer comprises a first interconnect that electrically connects a second contact pad of the first optoelectronic circuit to a first contact pad of the second optoelectronic circuit.
Description
Description
Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component
The present invention relates to a semiconductor wafer according to claim 1, to an optoelectronic component according to claim 6 and to a method for producing an optoelectronic component according to claim 14.
Optoelectronic devices that comprise one or more optoelectronic chips arranged on a carrier substrate are known in the state of the art. The optoelectronic chips of such optoelec- tronic devices may for example be light-emitting diodes
(LEDs) or laser diodes. It is known in the state of the art to attach each optoelectronic chip individually to the carrier substrate using a die attach process or a glue attach process. In a following step, the optoelectronic chips are electrically contacted individually, using for example bond wires. The optoelectronic chips of an optoelectronic device can for example be arranged in a series connection. This usu¬ ally requires at least one bond wire per optoelectronic chip. The large number of die attach and wire bond processes makes the production of conventional optoelectronic devices slow and expensive. Bond wires are also known to block and reduce light output in conventional electronic devices. Furthermore, each bond wire adds a certain risk of failure to a conventional optoelectronic device.
It is an object of the present invention to provide a semi¬ conductor wafer. This objective is achieved by a semiconductor wafer with the features of claim 1. It is a further object of the present invention to provide an optoelectronic component. This objective is achieved by an optoelectronic component comprising the features of claim 6. It is a further object of the present invention to provide a method for producing an optoelectronic component. This objective is
achieved by a method with the features of claim 14. Preferred embodiments are disclosed in the dependent claims.
A semiconductor wafer comprises a first row of optoelectronic circuits. The first row comprises a first optoelectronic circuit and a second optoelectronic circuit. The semiconductor wafer furthermore comprises a first interconnect that electrically connects a second contact pad of the first optoelectronic circuit to a first contact pad of the second optoelec- tronic circuit. Advantageously, the interconnect of this semiconductor wafer electrically connects the first optoelectronic circuit and the second optoelectronic circuit. The first optoelectronic circuit and the second optoelectronic circuit together may be arranged in an optoelectronic compo- nent . The first optoelectronic circuit and the second optoelectronic circuit are then electrically connected by means of the first interconnect. The first interconnect thus replaces a bond wire. In an embodiment of the semiconductor wafer, the semiconductor wafer comprises a second row of optoelectronic circuits that is arranged adjacent to the first row. The second row comprises a third optoelectronic circuit and a fourth opto¬ electronic circuit. The semiconductor wafer comprises a sec- ond interconnect that electrically connects a first contact pad of the third optoelectronic circuit to a second contact pad of the fourth optoelectronic circuit. Advantageously, the second interconnect renders a bond wire to electrically connect the third optoelectronic circuit and the fourth opto- electronic circuit unnecessary. The second interconnect may be split in case that an electrical connection between the third optoelectronic circuit and the fourth optoelectronic circuit is not desired. In an embodiment of the semiconductor wafer, the semiconduc¬ tor wafer comprises a third row of optoelectronic circuits that is arranged adjacent to the second row. The semiconductor wafer furthermore comprises a fourth row of optoelec-
tronic circuits that is arranged adjacent to the third row. The third row is constructed like the first row and the fourth row is constructed like the second row. Optoelectronic circuits arranged in the third row may thus be electrically connected by interconnects. Optoelectronic circuits arranged in the fourth row may also be electrically connected by in¬ terconnects. Advantageously, the semiconductor wafer provides a large number of optoelectronic circuits that are partially electrically connected via interconnects. The interconnects strongly reduce a number of bond wires reguired to electri¬ cally connect a number of optoelectronic circuits of the semiconductor wafer.
In an embodiment of the semiconductor wafer, the first opto- electronic circuit is arranged in a first column of optoelectronic circuits. The second optoelectronic circuit is arranged in a second column of optoelectronic circuits. The semiconductor wafer comprises a third column of optoelec¬ tronic circuits that is arranged adjacent to the second col- umn . The third column is constructed like the first column. The semiconductor wafer furthermore comprises a third interconnect that electrically connects a second contact pad of the second optoelectronic circuit to a first contact pad of an optoelectronic circuit of the third column. Advanta- geously, the first optoelectronic circuit, the second optoelectronic circuit and the optoelectronic circuit of the third column of the semiconductor wafer are electrically connected in a serial configuration via the first interconnect and the third interconnect. This allows for employing the first optoelectronic circuit, the second optoelectronic circuit and the optoelectronic circuit of the third column in an optoelectronic component without reguiring to electrically connect the first optoelectronic circuit, the second optoelectronic circuit and the optoelectronic circuit of the third column via bond wires.
In an embodiment of the semiconductor wafer, the semiconductor wafer comprises a fourth column of optoelectronic cir-
cuits that is arranged adjacent to the third column. The fourth column is constructed like the second column. Advanta¬ geously, the semiconductor wafer thus provides a regular array of optoelectronic circuits. Optoelectronic circuits ar- ranged in rows of this array are electrically connected in serial configurations. The semiconductor wafer can be diced into smaller semiconductor chip dies, each comprising a defined number of optoelectronic circuits. The optoelectronic circuits of each semiconductor chip die are then arranged in one or more groups of electrically connected optoelectronic circuits, rendering bond wires at least partially unnecessary. Each semiconductor chip die can be processed in its entirety, thereby strongly reducing the number of required individual die attach processes.
An optoelectronic component comprises a semiconductor chip die, wherein the chip die comprises a first optoelectronic circuit and a second optoelectronic circuit. The chip die comprises a first interconnect that electrically connects a second contact pad of the first optoelectronic circuit to a first contact pad of the second optoelectronic circuit. Advantageously, the first optoelectronic circuit and the second optoelectronic circuit of the optoelectronic component are arranged on the one common semiconductor chip die. This al- lows for assembling the first optoelectronic circuit and the second optoelectronic circuit in the optoelectronic component in one common process step, for example a die attach process. The first optoelectronic circuit and the second optoelectronic circuit are electrically connected in a serial con- figuration via the first interconnect. This renders a bond wire to electrically connect the first optoelectronic circuit and the second optoelectronic circuit unnecessary. Consequently, the optoelectronic component may be manufactured in a cost-efficient manner.
In an embodiment of the optoelectronic component, the first interconnect is formed by a metallic plating arranged on a surface of the chip die. Advantageously, this allows for ere-
ating the first interconnect at a wafer level, allowing for a cost-efficient production of the optoelectronic component.
In an embodiment of the optoelectronic component, the second contact pad of the first optoelectronic circuit is arranged next to the first contact pad of the second optoelectronic circuit. Advantageously, this allows for arranging the first optoelectronic circuit and the second optoelectronic circuit on the semiconductor chip die in a space-saving manner. This allows for a cost-efficient production of the optoelectronic component. Furthermore, the optoelectronic component can be constructed with small spatial dimensions.
In an embodiment of the optoelectronic component, the first contact pad and the second contact pad of the first optoelectronic circuit are arranged at diagonally opposite corners of the first optoelectronic circuit. Advantageously, this allows for an effective spreading of current driven through the first optoelectronic circuit during operation of the first optoelectronic component.
In an embodiment of the optoelectronic component, the chip die comprises a third optoelectronic circuit and a second in¬ terconnect that electrically connects a second contact pad of the second optoelectronic circuit to a first contact pad of the third optoelectronic circuit. Advantageously, the chip die of the optoelectronic component comprises three optoelec¬ tronic circuits and may thus comprise a high output power. The three optoelectronic circuits are arranged on one common chip die, allowing for a simple and cost-efficient production of the optoelectronic component.
In an embodiment of the optoelectronic component, the second contact pad of the second optoelectronic circuit is arranged next to the first contact pad of the third optoelectronic circuit. Advantageously, this allows for a space-saving arrangement of the optoelectronic circuits on the chip die.
This makes it possible to obtain the optoelectronic component at low production costs.
In an embodiment of the optoelectronic component, the chip die comprises a fourth optoelectronic circuit. A bond wire electrically connects a first contact pad of the first opto¬ electronic circuit to a second contact pad of the fourth optoelectronic circuit. The fourth optoelectronic circuit may for example be arranged in a second row of optoelectronic circuits, while the first optoelectronic circuit and the sec¬ ond optoelectronic circuit are arranged in a first row of optoelectronic circuits on the semiconductor chip die. Advantageously, this makes it possible to provide the optoelectronic component with an even higher number of optoelectronic cir- cuits, enabling an even higher output power of the optoelectronic component. Still, all optoelectronic circuits of the optoelectronic component may be arranged on the one common semiconductor chip die, enabling a fast, simple and cost- efficient production of the optoelectronic component.
In an embodiment of the optoelectronic component, the chip die comprises a further optoelectronic circuit. A further bond wire electrically connects a contact pad of the further optoelectronic circuit to a bond pad of the optoelectronic component. The bond pad of the optoelectronic component thus provides an electric connection to the optoelectronic circuits of the optoelectronic component, allowing to apply electric voltage to the optoelectronic circuits and to drive electric current through the optoelectronic circuits.
A method for producing an optoelectronic component comprises steps for producing a semiconductor wafer comprising a first optoelectronic circuit, a second optoelectronic circuit and a first interconnect that electrically connects a second con- tact pad of the first optoelectronic circuit to a first con¬ tact pad of the second optoelectronic circuit, for dicing the semiconductor wafer to obtain a semiconductor chip die, and for arranging the chip die on a carrier. Advantageously, this
method allows for producing an optoelectronic component that comprises only one semiconductor chip die. The semiconductor chip die of the optoelectronic component may however comprise a flexible number of optoelectronic circuits. At least two of the optoelectronic circuits arranged on the semiconductor chip die of the optoelectronic component are electrically connected by a first interconnect arranged on the semiconductor chip die. This first interconnect makes it unnecessary to electrically connect the optoelectronic circuits with a bond wire. The method for producing the optoelectronic component can thus be carried out in a simple and cost-efficient manner .
In an embodiment of the method, the chip die comprises the first optoelectronic circuit and a third optoelectronic circuit. The method further comprises a step for arranging a bond wire between a first contact pad of the first optoelectronic circuit and a second contact pad of the third opto¬ electronic circuit. Advantageously, the method for producing the optoelectronic component allows to electrically connect optoelectronic circuits arranged on the chip die that are not electrically connected by interconnects arranged on the chip die . In an embodiment of the method, the method further comprises a step for arranging a bond wire between a contact pad of an optoelectronic circuit of the chip die and a bond pad of the optoelectronic component. The bond wire may serve to electrically connect the optoelectronic circuit of the chip die of the optoelectronic component. Since some or all of the optoelectronic circuits of the chip die of the optoelectronic component may be electrically connected internally by interconnects arranged on the chip die, it may be sufficient to electrically connect one or a few of the optoelectronic cir- cuits to bond pads of the optoelectronic component.
The accompanying drawings are included in order to provide a further understanding of the present invention and are incor-
porated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they will be better understood by reference to the following detailed description. The elements of the drawings are not to scale with regard to each other .
Fig. 1 shows a schematic view of a part of a first semiconductor wafer;
Fig. 2 shows a schematic view of a first optoelectronic com- ponent;
Fig. 3 shows a schematic view of a second optoelectronic com ponent ;
Fig. 4 shows a schematic view of a third optoelectronic component; and
Fig. 5 shows a schematic view of a part of a second semicon¬ ductor wafer.
Fig. 1 shows a schematic topview of a part of a first semiconductor wafer 100. The first semiconductor wafer 100 comprises a plurality of optoelectronic circuits 200. The optoelectronic circuits 200 are designed to absorb or emit electromagnetic radiation, for example visible light. The optoelectronic circuits 200 may for example be light-emitting di odes (LEDs) . Each optoelectronic circuit 200 comprises an ap proximately rectangular shape.
The first semiconductor wafer 100 comprising the plurality of optoelectronic circuits 200 may be produced using conventional techniques of semiconductor technology.
The optoelectronic circuits 200 of the first semiconductor wafer 100 are arranged in a regular grid pattern comprising a first row 101, a second row 102, a third row 103, a fourth row 104, a first column 111, a second column 112, a third column 113 and a fourth column 114. The regular grid pattern of the optoelectronic circuits 200 of the first semiconductor wafer 100 may comprise more rows and/or more columns.
A first optoelectronic circuit 210 of the plurality of opto- electronic circuits 200 is arranged in the first row 101 and the first column 111. A second optoelectronic circuit 220 of the plurality of optoelectronic circuits 200 is arranged in the first row 101 and the second column 112. A third optoelectronic circuit 230 of the plurality of optoelectronic circuits 200 is arranged in the second row 102 and the first column 111. A fourth optoelectronic circuit 240 of the plurality of optoelectronic circuits 200 is arranged in the second row 102 and the second column 112. A fifth optoelectronic circuit 250 of the plurality of optoelectronic circuits 200 is arranged in the first row 101 and the third column 113.
Each optoelectronic circuit 200 comprises a first contact pad 201 and a second contact pad 202. Both the first contact pad
201 and the second contact pad 202 of each optoelectronic circuit 200 are arranged on the upper surface of the first semiconductor wafer 100 visible in the schematic drawing of Fig. 1. The first contact pad 201 and the second contact pad
202 of each optoelectronic circuit 200 are provided for electrically connecting the respective optoelectronic circuit 200. The first contact pad 201 may for example be connected to a p-doped region of the respective optoelectronic circuit 200. The second contact pad 202 may for example be electrically connected to an n-doped region of the respective optoelectronic circuit 200. The first contact pad 201 and the second contact pad 202 of each optoelectronic circuit 200 are arranged at diagonally opposite corners of the respective optoelectronic circuit 200.
Compared to the first optoelectronic circuit 210, the second optoelectronic circuit 220 is mirrored along an axis that is parallel to the first row 101. Accordingly, the fourth optoelectronic circuit 240 is mirrored along an axis parallel to the second row 102 with respect to the third optoelectronic circuit 230. All other optoelectronic circuits 200 of the second column 112 are mirrored along an axis parallel to the respective row 101, 102, 103, 104 with respect to an optoelectronic circuit 200 in the first column 111 of the same row 101, 102, 103, 104. Optoelectronic circuits 200 of the second column 112 are, in other words, mirrored along horizontal axes parallel to the rows 101, 102, 103, 104 with respect to neighboring optoelectronic circuits 200 of the first column 111.
The optoelectronic circuits 200 of the third column 113 are oriented like the optoelectronic circuit 200 of the first column 111. Optoelectronic circuits 200 of the fourth column 114 are oriented like the optoelectronic circuits 200 of the second column 112. The orientations of optoelectronic circuits 200 of any further columns of the first semiconductor wafer 100 follows this pattern.
Compared to the first optoelectronic circuit 210, the third optoelectronic circuit 230 is mirrored both along a horizontal axis parallel to the second row 102 and along a vertical axis parallel to the first column 111. Consequently, the po¬ sitions of the first contact pad 201 and the second contact pad 202 of the third optoelectronic circuit 230 are inter- changed with respect to the positions of the first contact pad 201 and the second contact pad 202 of the first optoelec¬ tronic circuit 210.
Accordingly, the positions of the contact pads 201, 202 of all other optoelectronic circuits 200 of the second row 102 are interchanged with respect to the positions of the contact pads 201, 202 of the respective neighboring optoelectronic circuits 200 of the first row 101.
The optoelectronic circuits 200 of the third row 103 are ori¬ ented like the optoelectronic circuits 200 of the first row 101. The optoelectronic circuits 200 of the fourth row 104 are oriented like the optoelectronic circuits 200 of the second row 102. Any further rows of the first semiconductor wafer 100 follow this pattern.
The first contact pad 201 of the second optoelectronic cir- cuit 220 is arranged directly adjacent to the second contact pad 202 of the first optoelectronic circuit 210. The second contact pad 202 of the second optoelectronic circuit 220 is arranged directly adjacent to the first contact pad 201 of the fifth optoelectronic circuit 250. The first contact pad 201 of the third optoelectronic circuit 230 is arranged directly adjacent to the second contact pad 202 of the fourth optoelectronic circuit 240.
In summary, the first contact pad 201 of each optoelectronic circuit 200 is arranged directly adjacent to a second contact pad 202 of a first neighboring optoelectronic circuit 200 of the same row 101, 102, 103, 104. The second contact pad 202 of each optoelectronic circuit 200 is arranged directly adja¬ cent to a first contact pad 201 of a second neighboring opto- electronic circuit 200 of the same row 101, 102, 103, 104. Only optoelectronic circuits 200, 210, 230 arranged in marginal columns comprise contact pads 201, 202 without direct neighbours . Adjacently arranged contact pads 201, 202 of neighboring optoelectronic circuits 200 of the same row 101, 102, 103, 104 each are electrically connected by a respective interconnect 300. The second contact pad 202 of the first optoelectronic circuit 210 is electrically connected to the first contact pad 201 of the second optoelectronic circuit 220 by a first interconnect 300, 310. The second contact pad 202 of the second optoelectronic circuit 220 is electrically connected to the first contact pad 201 of the fifth optoelectronic circuit
250 by a second interconnect 300, 320. The first contact pad 201 of the third optoelectronic circuit 230 is electrically connected to the second contact pad 202 of the fourth optoelectronic circuit 240 by a third interconnect 300, 330.
The interconnects 300 comprise an electrically conductive ma¬ terial. Preferentially, the interconnects 300 comprise a material that is suitable for wire bonding. The interconnects 300 may for example be formed by metal platings arranged on the surface of the first semiconductor wafer 100. The inter¬ connects 300 may for example be formed integrally with metal platings covering the first contact pad 201 and the second contact pad 202 of the optoelectronic circuits 200 of the first semiconductor wafer 100.
The optoelectronic circuits 200 of the first semiconductor wafer 100 are arranged in a slightly spaced relationship. This allows to separate the rows 101, 102, 103, 104 and/or the columns 111, 112, 113, 114 of the first semiconductor wa- fer 100 by cutting (dicing) the first semiconductor wafer 100 along sawing streets arranged between the individual rows 101, 102, 103, 104 and column 111, 112, 113, 114. The sawing streets run across the interconnects 300. Dicing of the first semiconductor wafer 100 may for example be carried out by sawing or laser dicing.
The first semiconductor wafer 100 may be diced into a plural¬ ity of smaller semiconductor chips dies. Each semiconductor chip die may comprise one or more of the optoelectronic cir- cuits 200 of the first semiconductor wafer 100. The optoelectronic circuits 200 arranged on one semiconductor chip die may be arranged in one or more rows 101, 102, 103, 104 and in one or more columns 111, 112, 113, 114. Fig. 2 shows a schematic topview of a part of a first opto¬ electronic component 400. The first optoelectronic component 400 may for example be a light-emitting component, for example a LED component.
The first optoelectronic component 400 comprises a carrier 420. The carrier 420 may be arranged in a housing of the first optoelectronic component 400. The carrier 420 may also be referred to as a substrate or a board. The carrier 420 comprises a surface visible in the schematic view of Fig. 2. The surface of the carrier 420 may be optical highly reflective . A first semiconductor chip die 410 is arranged on the surface of the carrier 420 of the first optoelectronic component 400. The first semiconductor chip die 410 is formed by a part of the first semiconductor wafer 100 of Fig. 1. The first semiconductor chip die 410 has been created by dicing the first semiconductor wafer 100.
The first semiconductor chip die 410 of the first optoelectronic component 400 comprises a plurality of optoelectronic circuits 200. In the particular example of Fig. 2, the first semiconductor chip die 410 of the first optoelectronic component 400 comprises the first five columns 111, 112, 113, 114 of the first row 101 of the first semiconductor wafer 100. Conseguently, the first semiconductor chip die 410 of the first optoelectronic component 400 comprises the first opto- electronic circuit 210, the second optoelectronic circuit 220, the fifth optoelectronic circuit 250, a further optoelectronic circuit 200 arranged in the fourth column 114 and a last optoelectronic circuit 260 arranged in the fifth column. It is however, obviously, possible to provide the first optoelectronic component 400 with a semiconductor chip die comprising consecutive optoelectronic circuits 200 from an¬ other position of the first semiconductor wafer 100.
The optoelectronic circuits 200 of the first semiconductor chip die 410 of the first optoelectronic component 400 are arranged in a series connection by means of the interconnects 300. The first interconnect 310 electrically connects the second contact pad 202 of the first optoelectronic circuit
210 to the first contact pad 201 of the second optoelectronic circuit 220. The third interconnect 330 electrically connects the second contact pad 202 of the second optoelectronic circuit 220 to the first contact pad 201 of the fifth optoelec- tronic circuit 250. Further interconnects 300 continue this series connection up to the last optoelectronic circuit 260.
The carrier 420 of the first optoelectronic component 400 comprises a first bond pad 430 and a second bond pad 440. The first bond pad 430 and the second bond pad 440 are arranged on the surface of the carrier 420. The first bond pad 430 and the second bond pad 440 may for example be designed as metal platings arranged on the surface of the carrier 420. The first bond pad 430 and the second bond pad 440 may be elec- trically connected to external electric contact elements of the first optoelectronic component 400, for example to solder pads or to contact pins of the first optoelectronic component 400. A first bond wire 450 is arranged between the first bond pad 430 of the first optoelectronic component 400 and the first contact pad 201 of the first optoelectronic circuit 210 of the first semiconductor chip die 410 of the first optoelec¬ tronic component 400. The first bond wire 450 provides an electrically conductive connection between the first bond pad 430 and the first contact pad 201 of the first optoelectronic circuit 210. A second bond wire 460 is arranged between the second contact pad 202 of the last optoelectronic circuit 260 of the first semiconductor chip die 410 and the second bond pad 440 of the first optoelectronic component 400. The second bond wire 460 provides an electrically conductive connection between the second contact pad 202 of the last optoelectronic circuit 260 and the second bond pad 440. The series connection of the optoelectronic circuits 200 of the first semicon- ductor chip die 410 of the first optoelectronic component 400 is thus arranged between the first bond pad 430 and the second bond pad 440 of the first optoelectronic component 400. This allows to use the external contact elements of the first
optoelectronic component 400 to electrically contact the se¬ ries connection of the optoelectronic circuits 200 of the first semiconductor chip die 410 of the first optoelectronic component 400.
Since the optoelectronic circuits 200 of the first semicon¬ ductor chip die 410 of the first optoelectronic component 400 are arranged in a series connection by means of the interconnects 300, it is unnecessary to arrange bond wires between the individual optoelectronic circuits 200 of the first opto¬ electronic component 400. This allows for a simple and economic production of the first optoelectronic component 400. Additionally, the low number of bond wires of the first optoelectronic component 400 ensures a low risk of failure of the first optoelectronic component 400.
The first semiconductor chip die 410 of the first optoelectronic component 400 may for example be arranged on the car¬ rier 420 of the first optoelectronic component 400 by means of a die attach process or a glue attach process. Since all optoelectronic circuits 200 of the first optoelectronic component 400 are arranged on the common first semiconductor chip die 410, production of the first optoelectronic compo¬ nent 400 requires only one attach process. This also allows for a simple and economic production of the first optoelectronic component 400.
Fig. 3 shows a schematic topview of a second optoelectronic component 500. The second optoelectronic component 500 com- prises similarities with the first optoelectronic component
400 of Fig. 2. Elements of the first optoelectronic component 400 that are also present in the second optoelectronic component 500 are labeled with the same numerals in Fig. 3 as in Fig. 2 and will not be explained in detail again. In the fol- lowing, only the differences between the second optoelec¬ tronic component 500 and the first optoelectronic component 400 will be elaborated.
The second optoelectronic component 500 comprises a second semiconductor chip die 510 that replaces the first semicon¬ ductor chip die 410 of the first optoelectronic component 400. The second semiconductor chip die 510 is formed out of a part of the first semiconductor wafer 100 of Fig. 1. The second semiconductor chip die 510 comprises a plurality of the optoelectronic circuits 200 of the first semiconductor wafer 100 of Fig. 1. In particular, the second semiconductor chip die 510 comprises the first five columns 111, 112, 113, 114 of the first row 101 and the second row 102 of the first semiconductor wafer 100. In the first row 101, the second semiconductor chip die 510 comprises the first optoelectronic circuit 210, the second optoelectronic circuit 220, the fifth optoelectronic circuit 250, the further optoelectronic cir- cuit 200 and the last optoelectronic circuit 260. In the second row 102, the second semiconductor chip die 510 comprises the third optoelectronic circuit 230, the fourth optoelectronic circuit 240 and three more optoelectronic circuits 200, among them a foremost optoelectronic circuit 270 ar- ranged in the fifth column, neighboring the last optoelectronic circuit 260 in the fifth column of the first row 101.
The optoelectronic circuits 200 of the first row 101 of the second semiconductor chip die 510 are arranged in a first se- ries connection. The optoelectronic circuits 200 of the second row 102 of the semiconductor chip die 510 are arranged in a second series connection. Additionally, the first contact pad 201 of the first optoelectronic circuit 210 is electrically connected to the second contact pad 202 of the third optoelectronic circuit 230 arranged in the first column 111 of the second row 102 of the semiconductor chip die 510 by means of a third bond wire 470. The third bond wire 470 thus connects the first series connection and the second series connection to form one series connection that comprises all ten optoelectronic circuits 200 of the semiconductor chip die 510.
The first contact pad 201 of the foremost optoelectronic cir¬ cuit 270 in the fifth column of the second row 102 is elec¬ trically connected to the first bond pad 430 of the second optoelectronic component 500 by means of the first bond wire 450. The second contact pad 202 of the last optoelectronic circuit 260 in the fifth column of the first row 101 of the second semiconductor chip die 510 is electrically connected to the second bond pad 440 of the second optoelectronic component 500 by means of the second bond wire 460. The series connection of the optoelectronic circuits 200 of the second semiconductor chip die 510 is thus electrically arranged between the first bond pad 430 and the second bond pad 440 of the second optoelectronic component 500. The first bond pad 430 and the second bond pad 440 of the second optoelectronic component 500 are not arranged on the carrier 420 of the second optoelectronic component 500 but at another position of the second optoelectronic component 500. It is however possible to arrange the bond pads 430, 440 on the surface of the carrier 420 of the second optoelectronic component 500.
The optoelectronic circuits 200 of the second semiconductor chip die 510 of the second optoelectronic component 500 are all arranged on the one common second semiconductor chip die 510. Consequently, the production of the second optoelectronic component 500 requires only one die attach process to attach the second semiconductor chip die 510 to the surface of the carrier 420. Afterwards, the third bond wire 470 may be arranged to connect the series connections of optoelectronic circuits 200 of the first row 101 and the second row 102.
Fig. 4 shows a schematic topview of a third optoelectronic component 600. The third optoelectronic component 600 com¬ prises similarities with the first optoelectronic component 400 of Fig. 2. Elements of the first optoelectronic component 400 that are also present in the third optoelectronic compo-
nent 600 are designated with the same reference numbers in Figs. 2 and 4 and will not be explained in detail again. In the following, only the differences between the first optoelectronic component 400 and the third optoelectronic compo- nent 600 are explained.
The third optoelectronic component 600 comprises a third semiconductor chip die 610 that replaces the first semiconductor chip die 410. The third semiconductor chip die 610 is formed out of a part of the first semiconductor wafer 100 of Fig. 1. The third semiconductor chip die 610 comprises only one optoelectronic circuit 200.
The first bond wire 450 electrically connects the first con- tact pad 201 of the optoelectronic circuit 200 to the first bond pad 430 arranged on the carrier 420 of the third optoelectronic component 600. The second bond wire 460 electrically connects the second contact pad 202 of the optoelec¬ tronic circuit 200 to the second bond pad 440 arranged on the carrier 420 of the third optoelectronic component 600. The optoelectronic circuit 200 of the third semiconductor chip die 610 of the third optoelectronic component 600 can thus be electrically contacted via external contact pads of the third optoelectronic component 600, that are electrically connected to the bond pads 430, 440 of the third optoelectronic component 600.
As can be understood from the examples shown in Figs. 2, 3 and 4, the first semiconductor wafer 100 can be diced into semiconductor chip dies of variable size comprising a variable number of optoelectronic circuits 200 arranged in a variable number of rows and a variable number of columns. The diced semiconductor chip dies can be used to produce optoelectronic components. The more optoelectronic circuits a semiconductor chip die comprises, the higher is the resulting optoelectronic power of the optoelectronic component. The interconnects 300 that electrically connect at least some of the optoelectronic circuits 200 arranged on one semiconductor
chip die advantageously reduce the number of bond wires nec¬ essary to electrically connect the optoelectronic circuits
200. It is also possible to provide an optoelectronic component with more than one semiconductor chip die. Each of these semiconductor chip dies may comprise one or more optoelectronic circuits arranged in one or more rows and one or more columns .
Fig. 5 shows a schematic top view of a part of a second semiconductor wafer 700. The second semiconductor wafer 700 is partially similar to the first semiconductor wafer 100 of Fig. 1. Elements of the first semiconductor wafer 100 that are also present in the second semiconductor wafer 700 are designated with the same reference numbers in both Figs. 1 and 5 and will not be explained in detail again. In the following, only the differences between the first semiconductor wafer 100 and the second semiconductor wafer 700 are ex- plained.
The second semiconductor wafer 700 comprises a plurality of optoelectronic circuits 200 arranged in a regular grid pat¬ tern of rows and columns. Each optoelectronic circuit 200 comprises an approximately rectangular shape.
Each optoelectronic circuit 200 comprises a first contact pad
201 and a second contact pad 202. The first contact pad 201 is arranged in a first corner of the optoelectronic circuit 200. The second contact pad 202 is arranged in a second corner of the optoelectronic circuit 200. The first corner com¬ prising the first contact pad 201 and the second corner comprising the second contact pad 202 are arranged along one common edge of the optoelectronic circuit 200.
The first contact pad 201 of each optoelectronic circuits 200 is arranged adjacent to a second contact pad 202 of a first neighboring optoelectronic circuit 200. The second contact
pad 202 of each optoelectronic circuit 200 is arranged next to a first contact pad 201 of a second neighboring optoelec¬ tronic circuit 200. Only optoelectronic circuits 200 arranged in marginal columns comprise contact pads 201, 202 without direct neighbours.
The first contact pad 201 of each optoelectronic circuit 200 is electrically connected to the second contact pad 202 of a neighboring optoelectronic circuit 200 by means of an inter- connect arranged on the surface of the second semiconductor wafer 700. Only contact pads 201, 202 of optoelectronic circuits 200 arranged on a border of the grid pattern of optoelectronic circuits 200 are not arranged adjacent to contact pads 201, 202 of neighboring optoelectronic circuits 200 and are not electrically connected to contact pads 201, 202 of neighboring optoelectronic circuits 200.
All optoelectronic circuits 200 of the second semiconductor wafer 700 are designed and oriented egually. Optoelectronic circuits 200 arranged in neighboring rows or columns of the second semiconductor wafer 700 are not mirrored or rotated with respect to each other.
The first contact pad 201 and the second contact pad 202 of each optoelectronic circuit 200 could also be arranged at the center of opposite outside edges of the optoelectronic circuits 200. The second contact pad 210 of each optoelectronic circuit 200 would then be arranged at the center of an edge of the optoelectronic circuit that is arranged adjacent to an edge of a neighboring optoelectronic circuit 200. The first contact pad 201 would be arranged at the center of an oppo¬ site outside edge that is arranged adjacent to an outside edge of another neighboring optoelectronic circuit 200. While the invention has been described in detail with refer¬ ence to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes in modification can be made therein without departing from the
spirit and scope thereof. Accordingly it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Reference numbers
100 first semiconductor wafer
101 first row
102 second row
103 third row
104 fourth row
111 first column
112 second column
113 third column
114 fourth column
200 optoelectronic circuit
201 first contact pad
202 second contact pad
210 first optoelectronic circuit
220 second optoelectronic circuit
230 third optoelectronic circuit
240 fourth optoelectronic circuit 250 fifth optoelectronic circuit
260 last optoelectronic circuit
270 foremost optoelectronic circuit
300 interconnect
310 first interconnect
320 second interconnect
330 third interconnect
400 first optoelectronic component 410 first semiconductor chip die
420 carrier
430 first bond pad
440 second bond pad
450 first bond wire
460 second bond wire
470 third bond wire
second optoelectronic component second semiconductor chip die third optoelectronic component third semiconductor chip die second semiconductor wafer
Claims
1. A semiconductor wafer (100, 700)
comprising a first row (101) of optoelectronic circuits (200),
wherein the first row (101) comprises a first optoelec¬ tronic circuit (200, 210) and a second optoelectronic circuit (200, 220),
wherein the semiconductor wafer (100, 700) comprises a first interconnect (300, 310) that electrically connects a second contact pad (202) of the first optoelectronic circuit (200, 210) to a first contact pad (201) of the second optoelectronic circuit (200, 220).
2. The semiconductor wafer (100, 700) according to claim 1, wherein the semiconductor wafer (100, 700) comprises a second row (102) of optoelectronic circuits (200) that is arranged adjacent to the first row (101),
wherein the second row (102) comprises a third optoelec- tronic circuit (200, 230) and a fourth optoelectronic circuit (200, 240),
wherein the semiconductor wafer (100, 700) comprises a second interconnect that electrically connects a first contact pad (201) of the third optoelectronic circuit (200, 230) to a second contact pad (202) of the fourth optoelectronic circuit (200, 240).
3. The semiconductor wafer (100, 700) according to claim 2, wherein the semiconductor wafer (100, 700) comprises a third row (103) of optoelectronic circuits (200) that is arranged adjacent to the second row (102),
wherein the semiconductor wafer (100, 700) comprises a fourth row (104) of optoelectronic circuits (200) that is arranged adjacent to the third row (103),
wherein the third row (103) is constructed like the first row (101) and the fourth row (104) is constructed like the second row (102) .
The semiconductor wafer (100, 700) according to any one of the previous claims,
wherein the first optoelectronic circuit (200, 210) is arranged in a first column (111) of optoelectronic circuits (200),
wherein the second optoelectronic circuit (200, 220) is arranged in a second column (112) of optoelectronic circuits (200),
wherein the semiconductor wafer (100, 700) comprises a third column (113) of optoelectronic circuits (200) that is arranged adjacent to the second column (112),
wherein the third column (113) is constructed like the first column (111),
wherein the semiconductor wafer (100, 700) comprises a third interconnect (330, 330) that electrically connects a second contact pad (202) of the second optoelectronic circuit (200, 220) to a first contact pad (201) of an optoelectronic circuit (200, 250) of the third column (113) .
The semiconductor wafer (100, 700) according to claim 4, wherein the semiconductor wafer (100, 700) comprises a fourth column (114) of optoelectronic circuits (200) that is arranged adjacent to the third column (113),
wherein the fourth column (114) is constructed like the second column (112) .
An optoelectronic component (400, 500)
comprising a semiconductor chip die (410, 510),
wherein the chip die (410, 510) comprises a first optoelectronic circuit (200, 210) and a second optoelectronic circuit (200, 220),
wherein the chip die (410, 510) comprises a first interconnect (300, 310) that electrically connects a second contact pad (202) of the first optoelectronic circuit (200, 210) to a first contact pad (201) of the second optoelectronic circuit (200, 220).
7. The optoelectronic component (400, 500) according to claim 6,
wherein the first interconnect (300, 310) is formed by a metallic plating arranged on a surface of the chip die (410, 510) .
8. The optoelectronic component (400, 500) according to any one of claims 6 and 7,
wherein the second contact pad (202) of the first opto- electronic circuit (200, 210) is arranged next to the first contact pad (201) of the second optoelectronic circuit (200, 220) .
9. The optoelectronic component (400, 500) according to any one of claims 6 to 8,
wherein a first contact pad (201) and the second contact pad (202) of the first optoelectronic circuit (200, 210) are arranged at diagonally opposite corners of the first optoelectronic circuit (200, 210).
10. The optoelectronic component (400, 500) according to any one of claims 6 to 9,
wherein the chip die (410, 510) comprises a third opto¬ electronic circuit (200, 250),
wherein the chip die (410, 510) comprises a second interconnect (330) that electrically connects a second contact pad (202) of the second optoelectronic circuit (200, 220) to a first contact pad (201) of the third optoelectronic (200, 250) circuit.
11. The optoelectronic component (400, 500) according to
claim 10,
wherein the second contact pad (202) of the second optoelectronic circuit (200, 220) is arranged next to the first contact pad (201) of the third optoelectronic cir¬ cuit (200, 250) .
12. The optoelectronic component (500) according to any one of claims 6 to 11,
wherein the chip die (510) comprises a fourth optoelectronic circuit (200, 230),
wherein a bond wire (470) electrically connects a first contact pad (201) of the first optoelectronic circuit (200, 210) to a second contact pad (202) of the fourth optoelectronic circuit (200, 230).
13. The optoelectronic component (400, 500) according to any one of claims 6 to 12,
wherein the chip die (410, 510) comprises a further optoelectronic circuit (200, 260, 270),
wherein a further bond wire (450, 460) electrically con- nects a contact pad (201, 202) of the further optoelectronic circuit (200, 260, 270) to a bond pad (430, 440) of the optoelectronic component (400, 500) .
14. A method for producing an optoelectronic component (400, 500, 600),
the method comprising:
- producing a semiconductor wafer (100, 700) comprising a first optoelectronic circuit (200, 210), a second opto¬ electronic circuit (200, 220) and a first interconnect (300, 310) that electrically connects a second contact pad (202) of the first optoelectronic circuit (200, 210) to a first contact pad (201) of the second optoelectronic circuit (200, 220);
- dicing the semiconductor wafer (100, 700) to obtain a semiconductor chip die (410, 510, 610);
- arranging the chip die (410, 510, 610) on a carrier (420) .
15. The method according to claim 14,
wherein the chip die (510) comprises the first optoelec¬ tronic circuit (200, 210) and a third optoelectronic circuit (200, 230),
the method further comprising:
- arranging a bond wire (470) between a first contact pad (201) of the first optoelectronic circuit (200, 210) and a second contact pad (202) of the third optoelectronic circuit (200, 230) .
16. The method according to any one of claims 14 and 15,
the method further comprising:
- arranging a bond wire (450, 460) between a contact pad (201, 202) of an optoelectronic circuit (200, 260, 270) of the chip die (410, 510, 610) and a bond pad (430, 440) of the optoelectronic component (400, 500, 600).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2013/066856 WO2015022013A1 (en) | 2013-08-13 | 2013-08-13 | Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component |
| TW103127452A TW201515286A (en) | 2013-08-13 | 2014-08-11 | Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2013/066856 WO2015022013A1 (en) | 2013-08-13 | 2013-08-13 | Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2015022013A1 true WO2015022013A1 (en) | 2015-02-19 |
Family
ID=49054528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2013/066856 WO2015022013A1 (en) | 2013-08-13 | 2013-08-13 | Semiconductor wafer, optoelectronic component and method for producing an optoelectronic component |
Country Status (2)
| Country | Link |
|---|---|
| TW (1) | TW201515286A (en) |
| WO (1) | WO2015022013A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213474A1 (en) * | 2009-02-24 | 2010-08-26 | Shu-Ting Hsu | Array-type light-emitting device and apparatus thereof |
| EP2367203A1 (en) * | 2010-02-26 | 2011-09-21 | Samsung LED Co., Ltd. | Semiconductor light emitting device having multi-cell array and method for manufacturing the same |
| WO2012057482A2 (en) * | 2010-10-25 | 2012-05-03 | 일진머티리얼즈 주식회사 | Vertical-type light-emitting diode cell array, and method for manufacturing same |
| EP2587555A2 (en) * | 2011-10-26 | 2013-05-01 | LG Innotek Co., Ltd. | Light emitting device |
-
2013
- 2013-08-13 WO PCT/EP2013/066856 patent/WO2015022013A1/en active Application Filing
-
2014
- 2014-08-11 TW TW103127452A patent/TW201515286A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213474A1 (en) * | 2009-02-24 | 2010-08-26 | Shu-Ting Hsu | Array-type light-emitting device and apparatus thereof |
| EP2367203A1 (en) * | 2010-02-26 | 2011-09-21 | Samsung LED Co., Ltd. | Semiconductor light emitting device having multi-cell array and method for manufacturing the same |
| WO2012057482A2 (en) * | 2010-10-25 | 2012-05-03 | 일진머티리얼즈 주식회사 | Vertical-type light-emitting diode cell array, and method for manufacturing same |
| EP2587555A2 (en) * | 2011-10-26 | 2013-05-01 | LG Innotek Co., Ltd. | Light emitting device |
Also Published As
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|---|---|
| TW201515286A (en) | 2015-04-16 |
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