CN107204365A - 开关装置以及点火装置 - Google Patents

开关装置以及点火装置 Download PDF

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Publication number
CN107204365A
CN107204365A CN201710117590.XA CN201710117590A CN107204365A CN 107204365 A CN107204365 A CN 107204365A CN 201710117590 A CN201710117590 A CN 201710117590A CN 107204365 A CN107204365 A CN 107204365A
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Prior art keywords
switching device
type
control
igbt
terminal
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Granted
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CN201710117590.XA
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CN107204365B (zh
Inventor
石井宪
石井宪一
逸见徳幸
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02PIGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P3/00Other installations
    • F02P3/02Other installations having inductive energy storage, e.g. arrangements of induction coils
    • F02P3/04Layout of circuits
    • F02P3/055Layout of circuits with protective means to prevent damage to the circuit, e.g. semiconductor devices or the ignition coil
    • F02P3/0552Opening or closing the primary coil circuit with semiconductor devices
    • F02P3/0554Opening or closing the primary coil circuit with semiconductor devices using digital techniques
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    • H01L29/7395Vertical transistors, e.g. vertical IGBT
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种在多芯片型点火器中保护控制电路的开关装置以及点火装置。开关装置,具备:引线框架(10);开关器件(30),其将下表面与引线框架(10)接触,并将该下表面的集电极与上表面的发射极之间进行开关;以及控制器件(50),其将下表面与引线框架(10)接触,并具有设置于上表面的控制开关器件(30)的控制电路以及从施加于引线框架(10)的过电压中保护控制电路的耐压结构部。本发明能够通过在控制器件(50)设置耐压结构部来保护控制电路。

Description

开关装置以及点火装置
技术领域
本发明涉及一种开关装置以及点火装置。
背景技术
汽车等的发动机通过向燃烧室导入燃料和空气的混合气体,并使用火花塞点火,进行燃烧而产生驱动力。在这里,每个火花塞均分配有点火线圈以及开关装置(称为点火器)。
以往,开关器件以及控制器件配置在同一芯片上的单芯片型点火器为众所周知(例如,参照专利文献1)。开关器件包括使通入点火线圈的初级线圈的电流断续的绝缘栅双极型晶体管(IGBT)。控制器件包括控制IGBT的动作的控制电路。在这里,控制电路不仅从发动机控制单元(ECU)接收控制信号而导通或者关断IGBT,还具有检测出IGBT的故障而不依靠ECU的控制信号使IGBT关断的功能。
现有技术文献
专利文献
专利文献1:日本专利文献特开2011-119542号公报
发明内容
技术问题
单芯片型点火器存在以下问题。例如,除了控制信号之外,ECU还向点火器输入用于检测ECU和点火器之间的断开、点火器端子的腐蚀等的检测信号。因此,如果将接收那些检测信号的接口设置在点火器上,则会导致芯片的大型化,乃至制造成本的增加。另外,存在IGBT的寄生电流流入控制器件的情况。因此,如果在开关器件和控制器件之间设置自分离区,则会导致芯片的大型化,乃至制造成本的增加。因此,期望一种将开关器件和控制器件分别配置在不同的芯片上,并从与ECU相独立的电源接收电源电压的多芯片型点火器。
另一方面,多芯片型点火器存在场衰减耐量,即对场衰减浪涌那样的负的浪涌电压(简称为负浪涌)的耐性降低的问题。在这里,点火器在将IGBT设为导通状态而通电以后,将IGBT设为关断状态而断电。在该断电时,通过在点火线圈中生成的高电压而使火花塞放电,对混合气体点火。但是,在火花塞没有放电时(即,没有点火时),高电压作为负浪涌施加到IGBT上,并从IGBT的发射极向集电极流通负的浪涌电流。此时,如果芯片因切割而受到损坏,则浪涌电流会特别集中在n+缓冲层与p+型半导体基板之间的PN结。
在多芯片型点火器中,通过以开关器件以及控制器件来分割芯片,使各个芯片的周边长度变短,浪涌电流更加集中在PN结的一部分,由此可能会导致对负浪涌的耐性的下降。
技术方案
本发明的第1方面,提供一种开关装置,具备:导电体;开关器件,其在第1面与导电体接触,并将第1面侧的第1端子与第2面侧的第2端子之间进行开关,第2面侧为第1面的相反侧;以及控制器件,其在第3面与导电体接触,且具有设置于第4面侧的开关器件的控制电路以及从施加于导电体的过电压中保护控制电路的第1耐压结构部,第4面侧为第3面的相反侧。
本发明的第2方面,提供一种开关装置,具备:导电体;开关器件,其在第1面与导电体接触,并将第1面侧的第1端子与第2面侧的第2端子之间进行开关,第2面侧为第1面的相反侧;以及控制器件,其在第3面与导电体接触,且具有设置于第4面侧的开关器件的控制电路,第4面侧为第3面的相反侧,其中,控制器件与开关器件相比,两面之间的耐压高。
另外,上述发明内容并没有列举出本发明的所有特征。此外,这些特征组的子组合也可以成为发明。
附图说明
图1显示点火器的整体构成。
图2显示开关器件的电路构成。
图3显示开关器件的俯视时的平面布局。
图4是关于图3的基准线AA的剖视图,且显示开关器件的剖面结构。
图5显示控制器件的电路构成。
图6显示控制器件的俯视时的平面布局。
图7是关于图6的基准线BB的剖视图,且显示控制器件的剖面结构。
图8显示点火器的制造流程。
图9显示具备点火器的点火装置的构成。
符号说明
10:引线框架 11:本体
11a:开口 11b、12、13:端子
16、17、18:布线 21:p+型半导体基板(p+型集电极区域)
22:n+型缓冲区域 23:n-型漂移区域
24:绝缘层 25:p+保护环
26:n+沟道截断区域 28:截断电极
29:钝化膜 30:开关器件
31:绝缘栅双极型晶体管(IGBT)
32:集电极-栅极间齐纳二极管(CG间ZD)
33:发射极焊盘 34:电极焊盘
35:耐压结构部 36:电流源
40:p+型区域 41:p型基区
42:n+型发射极区域 43:栅极
44:发射极 45:集电极
50:控制器件 51:感测IGBT
52:栅极-发射极间齐纳二极管(GE间ZD)
53:栅极焊盘 54:电极焊盘
55:耐压结构部 56、57:控制电路
56a、57a:电路部 56b、57b:有源元件
60:p+型区域 61:p型基区
62:n+型发射极区域 63:栅极
64:发射极 65:p型基区
66:n+型源极区域 67:n+型漏极区域
68:n-型区域 69a:栅极
69b:源极 69c:漏极
70:封装 71:p+型半导体基板(p+型集电极区域)
72:n+型缓冲区域 73:n-型漂移区域
74:绝缘层 75:p+保护环
76:n+沟道截断区域 78:截断电极
79:钝化膜 100:点火器
200:点火装置 210:ECU
214:二极管 220:点火线圈
230:火花塞 D2:二极管
L1:初级线圈 L2:次级线圈
R1、R2、RGE:电阻 R51:感测电阻
S1、S3、T1、T3:焊盘
具体实施方式
以下,通过发明的实施方式说明本发明,但以下实施方式并不限定权利要求书所涉及的发明。此外,在实施方式中说明的特征的全部组合不一定是发明的技术方案所必需的。
图1显示点火器100的整体构成。点火器100是开关装置的一个示例,其目的在于,在多芯片型点火器中,使芯片尺寸最小,并且确保场衰减耐量,特别是保护控制电路。
点火器100具备:作为导电体的引线框架10;开关器件30;控制器件50;布线16、17、18以及封装70。
引线框架10搭载并支撑开关器件30以及控制器件50。引线框架10为了使这些器件发出的热量散发,使用例如热导率高的金属而形成为板状。引线框架10具有本体11以及1个或者多个端子11b、12、13。
作为一个示例,本体11具有将单轴方向(即,图1中的上下方向)作为长度方向的矩形形状。对于本体11的长度方向的一侧,在其上支撑开关器件30以及控制器件50,并在这些器件中作为共同的集电极发挥作用。在本体11的长度方向的另一侧,作为一个示例形成有圆形的开口11a。
1个或者多个端子11b、12、13是在安装点火器100时,将包含于点火器100中的开关器件30、控制器件50等电路元件与外部元件连接的端子。在本实施方式中,作为一个示例,包括3个端子11b、12、13。
端子11b具有将单轴方向作为长度方向,但是相对于本体11宽度较窄的矩形形状,端子11b的基端一体地连接在本体11的长度方向的一侧的端部中央。由此,端子11b与本体11,即开关器件30以及控制器件50的集电极连接,并作为集电极端子发挥作用。另外,端子11b可以与本体11分别形成,并通过布线等连接于本体11。
端子12、13具有将单轴方向作为长度方向的矩形形状,并夹着端子11b与端子11b平行且它们的前端与端子11b的前端对齐地配设在图的左右方向的一侧以及另一侧。端子12通过后述的布线17连接到开关器件30(所包括的发射极焊盘33),并作为发射极端子发挥作用。端子13通过后述的布线18连接到控制器件50(所包括的栅极焊盘53),并作为栅极端子发挥作用。
另外,端子11b、12、13的数量并不限于3个,也可为4个以上。例如,也可以将端子13并列地设置2个,并在它们之间连接保护元件。作为保护元件,可以列举出吸收浪涌电压的电容、电阻等。另外,也可以将其他端子连接于控制器件50的接地电位,而将开关器件30以及控制器件50分别地钳位于接地电位。另外,在接收来自ECU以及独立的电源的电源电压时,也可以再增加1个以上的电源用端子,将这些电源用端子连接于各电源,而向控制器件50所包括的控制电路供给电源电压。
开关器件30是将端子11b(即,集电极端子)与端子12(即,发射极端子)之间进行开关的半导体器件。开关器件30构成为包括例如绝缘栅双极型晶体管(IGBT)。另外,并不限于IGBT,也可以包括例如电流从芯片的背面流向表面的纵向型金属氧化物半导体场效应晶体管(纵向型MOSFET)。开关器件30在引线框架10的本体11上,靠近端子12的基端而设置。关于开关器件30的详细构成将在下文中描述。
控制器件50是具有控制开关器件30的动作的控制电路的半导体器件。控制电路构成为包括例如金属氧化物半导体场效应晶体管(MOSFET)。控制器件50在引线框架10的本体11上,靠近端子13的基端而设置。控制器件50通过后述的多个布线16而连接于开关器件30,例如,将用于控制IGBT的控制信号发送给开关器件30、感测IGBT的集电极电位、和/或共有IGBT的发射极电位。关于控制器件50的详细构成将在下文中描述。
布线16、17、18是将开关器件30、控制器件50以及端子11b、12、13电连接的导体,作为一个示例可以使用铝导线。布线16设有多个,分别将开关器件30与控制器件50之间进行连接。布线17将端子12连接到开关器件30(所包括的发射极焊盘33)。布线18将端子13连接到控制器件50(所包括的栅极焊盘53)。
封装70将上述各个构件密封在其内部进行保护。作为一个示例,封装70除了引线框架10所具有的本体11的一侧(即,图1中的上侧)以及3个端子11b、12、13的前端之外,将本体11的另一侧、设置于该另一侧上的开关器件30和控制器件50、以及3个端子11b、12、13的基端密封在其内部。封装70通过使用例如环氧树脂等绝缘性良好的树脂进行模压成型,而形成为长方体形状。
对开关器件30进行更加详细的描述。
图2显示开关器件30的电路构成。开关器件30的电路构成为包括IGBT 31、集电极-栅极间齐纳二极管32以及电流源36。这些各个构件连接在焊盘T1、T3、发射极焊盘33以及前述的引线框架10的本体11(即,集电极45)之间。但是,焊盘T3短接于发射极焊盘33。
IGBT 31是接收来自控制器件50的控制信号而使从集电极流向发射极的电流断续的开关元件。IGBT 31连接在焊盘T1、发射极焊盘33以及引线框架10的本体11之间。也就是说,IGBT 31的栅极端子(G)、发射极端子(E)以及集电极端子(C)分别连接于焊盘T1、发射极焊盘33(以及焊盘T3)、以及引线框架10的本体11。
集电极-栅极间齐纳二极管(称为CG间ZD)32是确保IGBT 31的耐压的齐纳二极管。CG间ZD 32连接在焊盘T1以及引线框架10的本体11之间,即,被配置在IGBT 31的栅极端子(G)与集电极端子(C)之间。CG间ZD 32通过将所需数量的齐纳二极管串联而得到所期望的耐压。据此,在栅极端子(G)与集电极端子(C)之间的电压超过耐压时,通过CG间ZD 32将IGBT 31的栅极上拉,并在集电极端子(C)与发射极端子(E)之间流通电流,使集电极电位下降。
电流源36是用于使IGBT 31的集电极电位稳定的元件。电流源36与CG间ZD 32并列地连接在焊盘T1与引线框架10的本体11之间,即,被配置在IGBT 31的栅极端子(G)与集电极端子(C)之间。电流源36在由于电流量的过量而对点火器100限制电流时,通过使电流从IGBT 31的集电极端子(C)流向栅极端子(G),来抑制由于IGBT 31的急剧的开关而产生的电流量的过冲。
图3显示开关器件30的俯视时的平面布局。开关器件30包括IGBT 31、CG间ZD 32、发射极焊盘33、多个电极焊盘34、耐压结构部35以及电流源36(图3中未图示,参照图2)。
IGBT 31形成于除开关器件30的芯片端部(即,图3中的右端)的中央以外的芯片内部。关于IGBT 31的构成,特别是剖面构成将在下文中描述。
CG间ZD 32设置于在开关器件30的芯片外周设置的截断电极28(参照图4)与IGBT31之间的耐压结构部35上。
发射极焊盘33,如上所述,是连接于IGBT 31的发射极端子(E)的电极焊盘。发射极焊盘33设置于开关器件30的芯片中央的上表面。发射极焊盘33使用上述的布线17(参照图1)连接于端子12。
多个电极焊盘34是用于在与控制器件50之间发送或接收控制信号、检测信号等的电极焊盘。作为一个示例,包括连接于IGBT 31的栅极端子(G)以及发射极端子(E)的上述的焊盘T1、T3。多个电极焊盘34并列地设置于开关器件30的芯片端部(即,图3中的左端)附近的上表面。多个电极焊盘34使用上述的布线16分别连接于设置在控制器件50的对应的电极焊盘54。据此,可以将IGBT 31的栅极端子(G)以及发射极端子(E)连接到控制器件50。
耐压结构部35是从施加于引线框架10的本体11的过电压中保护IGBT 31以及设置于开关器件30的芯片的上表面侧的电路、电路元件等的结构。耐压结构部35设置于包围IGBT 31的开关器件30的芯片周围以及芯片上表面的边缘部。关于耐压结构部35的构成,特别是剖面构成将在下文中描述。
电流源36(图3中未图示,参照图2)可以使用例如耗尽型IGBT来构成。在这里,耗尽型IGBT的集电极端子连接于IGBT 31的集电极端子(C),栅极端子钳位于发射极端子并连接于IGBT 31的栅极端子(G)。
另外,也可以进一步在开关器件30设置测定芯片温度的温度传感器、检测IGBT 31的集电极电流的电流传感器、检测IGBT 31的集电极-发射极间的电压的电压传感器等检测开关器件30的异常的各种传感器。另外,还可以设置以导通信号基准来测量IGBT 31的导通时间的电路,使开关器件30定时动作。
图4是关于图3的基准线AA的剖视图,且显示开关器件30,特别是IGBT 31以及耐压结构部35的剖面结构。开关器件30的芯片包括引线框架10的本体11(即,集电极45)以及在集电极45上依次层叠的成为p+型集电极区域的p+型半导体基板21、n+型缓冲区域22和n-型漂移区域23。在n-型漂移区域23的上表面,即芯片的表面层的中央设有IGBT 31的表面元件结构,并且在芯片周围与表面层的边缘部上设置有耐压结构部35。
IGBT 31的表面元件结构包括p+型区域40、p型基区41、n+型发射极区域42、栅极43、发射极44。p+型区域40是作为IGBT 31的接触区域的p+型阱,被配置在表面元件的中心。p型基区41夹着p+型区域40而配置在两侧(即,图4中的左侧以及右侧)。n+型发射极区域42配置在各个p型基区41与p+型区域40之间。p+型区域40、p型基区41以及n+型发射极区域42的上表面与n-型漂移区域23的上表面共同在同一平面上形成芯片的表面。栅极43被栅极绝缘膜覆盖,并被配置在一个p型基区41之上。发射极44分别与p+型区域40、p型基区41以及n+型发射极区域42相接触,并被配置在p+型区域40、p型基区41以及n+型发射极区域42之上。
另外,集电极45是引线框架10的本体11的一部分,与芯片的整个背面相接触。发射极44配置在芯片的表面侧,与此相对应,包括p+型区域40(即,p+型阱)的IGBT 31的表面元件结构设置在芯片的表面侧。
另外,在开关器件30具有多个IGBT 31时,如图4所示,可以将栅极43配置在经由n-型漂移区域23而相邻的2个IGBT 31的表面元件结构各自所包括的一个p型基区41之上。
另外,在本实施方式中,虽然将IGBT 31的集电极区域、设置有p+型区域40的区域以及基区设为p型,将缓冲区域、漂移区域以及发射极区域设为n型,但这是一个示例,相反地,也可以将IGBT 31的集电极区域、设置有p+型区域40的区域以及基区设为n型,将缓冲区域、漂移区域以及发射极区域设为p型。
耐压结构部35通过在芯片的周围设置包围IGBT 31的表面元件结构的固定宽度的周边区域而形成。在该区域中不包括构成表面元件结构的p+型区域40等载流子区域。据此,在由于产生负浪涌而从发射极44经由芯片外缘向集电极45流通浪涌电流时,特别地,通过使足够宽度的n-型漂移区域23介于发射极44下的p+型区域40和芯片外缘之间,可以得到足够的耐性。
作为一个示例,耐压结构部35通过在芯片上表面的边缘部进一步设置p+保护环25、n+沟道截断区域26、绝缘层24、截断电极28以及钝化膜29而形成。
p+保护环25以包围IGBT 31的表面元件结构的方式在芯片的表面层的周围设置为环状。另外,p+保护环25不限于一个,也可以配设多个,例如,如图4所示,可以配设为双重。n+沟道截断区域26以包围p+保护环25的方式设置在芯片的表面层的最外缘。另外,在介于多个p+保护环25以及n+沟道截断区域26中彼此相邻的它们之间的n-型漂移区域23上设置有绝缘层24。截断电极28设置在n+沟道截断区域26之上。钝化膜29例如使用氮化硅(Si3N4)形成,覆盖p+保护环25、n+沟道截断区域26、绝缘层24以及截断电极28,并保护p+保护环25、n+沟道截断区域26、绝缘层24以及截断电极28。
通过在芯片的周围设置固定宽度的周边区域,或者除此之外还设置上述的结构,在从集电极45经由芯片外缘向发射极44施加浪涌电压时,或者从发射极44经由芯片外缘向集电极45施加浪涌电压时,会经由周边区域、或者多个p+保护环25以及截断电极28,由此使芯片表面上的电位稳定。
以下,对控制器件50进行更加详细的描述。
图5显示控制器件50的电路构成。控制器件50的电路构成为包括:感测IGBT 51(感测电阻R51);栅极-发射极间齐纳二极管52;控制电路56、57(电阻R1、R2、二级管D2);以及电阻RGE。这些各个构件连接在焊盘S1、S3、栅极焊盘53以及上述的引线框架10的本体11(即,集电极45)之间。
感测IGBT 51是模拟开关器件30内的IGBT 31来检测IGBT 31的集电极电流的量的感测用IGBT。感测IGBT 51连接在引线框架10的本体11与焊盘S1、S3之间。即,感测IGBT 51的栅极端子以及集电极端子分别连接于焊盘S1以及引线框架10的本体11,感测IGBT 51的发射极端子经由感测电阻R51连接于焊盘S3。
栅极-发射极间齐纳二极管(称为GE间ZD)52是保护IGBT 31的栅极的齐纳二极管。GE间ZD 52连接在焊盘S1、S3之间。即,如以下所述,经由电极焊盘34、54以及布线16,配置于开关器件30的IGBT 31的栅极端子(G)和发射极端子(E)之间。GE间ZD 52通过将所需数量的齐纳二极管串联而得到所期望的耐压。
控制电路56、57是检测开关器件30内的IGBT 31、或者点火器100的各个构件的异常而保护控制器件50的电路。
控制电路56在IGBT 31的集电极电流的量超过基准时将该集电极电流的量控制为固定。作为一个示例,控制电路56构成为包括电路部56a以及有源元件56b。控制电路56与电阻R1、R2以及二级管D2一同连接在焊盘S1、S3以及栅极焊盘53之间。电路部56a连接在栅极焊盘53与焊盘S3之间,但在电路部56a和栅极焊盘53之间经由电阻R1而连接。此外,在电路部56a连接有感测IGBT 51的发射极端子。有源元件56b连接在焊盘S1、S3之间。此外,有源元件56b的一端(即,漏极)经由并联的电阻R2和二级管D2而连接于电阻R1
电路部56a在从感测IGBT 51接收IGBT 31的集电极电流的量的检测结果,且将该检测结果与基准相比较为大(或者小)的情况下,向有源元件56b发送导通信号(关断信号)。有源元件56b在从电路部56a接收到导通信号时,输出将IGBT 31的栅极下拉(维持)的控制信号。控制电路56的控制信号输入到开关器件30的IGBT 31的栅极端子(G)。IGBT 31通过接收控制信号而导通或关断,据此集电极电流的量增大或减小至基准,从而控制为固定。
控制电路57在开关器件30异常的情况下关断IGBT 31。作为一个示例,控制电路57构成为包括电路部57a以及有源元件57b。电路部57a连接在栅极焊盘53与焊盘S3之间,但在电路部57a和栅极焊盘53之间经由电阻R1而连接。有源元件57b连接在焊盘S1、S3之间。
电路部57a利用例如设置在开关器件30的温度传感器来检测开关器件30的芯片温度。或者,也可以利用设置在控制器件50的温度传感器来检测控制器件50的芯片温度。在芯片温度高于基准的情况下,电路部57a视开关器件30为异常状态,向有源元件57b发送导通信号。有源元件57b在从电路部57a接收到导通信号时,输出将IGBT 31的栅极下拉的控制信号。控制电路57的控制信号输入到开关器件30的IGBT 31的栅极端子(G)。IGBT 31通过接收控制信号而关断,由此切断集电极电流。
另外,对于开关器件30的异常,不限于从芯片温度检测,也可以从其它的芯片的状态量,或者IGBT 31的状态量进行检测。作为IGBT 31的状态量,可以列举出例如:IGBT 31的导通时间的长度、IGBT 31的集电极电流的量,IGBT 31的集电极-发射极间的电压。控制电路57可以从设置在开关器件30的各种传感器获得这些状态量。
另外,控制电路56、57可以将由ECU供给的控制信号的信号电压作为电源电压使用,也可以使用由与ECU独立的电源供给的电源电压。
电阻RGE连接在栅极焊盘53和多个电极焊盘54所包括的焊盘S3之间。
其它,也可以设置防噪用的电容、电源保护用的电阻或者齐纳二极管等。另外,也可以设置与开关器件30独立的接地用的端子。
图6显示控制器件50的俯视时的平面布局。控制器件50包括:感测IGBT 51、栅极-发射极间齐纳二极管52、栅极焊盘53、多个电极焊盘54、耐压结构部55以及控制电路56、57。
感测IGBT 51形成于控制器件50的芯片中央的靠一侧(即,图6中的左侧)的芯片内部。关于感测IGBT 51的构成,特别是剖面构成将在下文中描述。
另外,在本实施方式中,为了有效利用开关器件30的芯片尺寸,并且以免检测出IGBT 31的寄生电流,而将感测IGBT 51设置在控制器件50,但并不限于此,也可以根据需要将感测IGBT 51与切断IGBT 31的寄生电流的结构一同设置在开关器件30,并经由电极焊盘34、54以及布线16将感测IGBT 51的检测结果发送到控制器件50内的控制电路。
GE间ZD 52设置于控制器件50的芯片中央的靠一侧(即,图6中的下侧)的芯片表面上。另外,GE间ZD 52可以设置于开关器件30。
栅极焊盘53是经由电极焊盘34、54以及布线16而连接于开关器件30的IGBT 31的栅极端子(G)的电极焊盘。栅极焊盘53设置于控制器件50的芯片角部(即,图6中的左下角部)附近的上表面。栅极焊盘53使用上述的布线18(参照图1)而连接于端子13。
多个电极焊盘54是用于在与开关器件30之间发送或接收控制信号、检测信号等的电极焊盘。作为一个示例,包括上述的焊盘S1、S3。多个电极焊盘54并列地设置于控制器件50的芯片端部(即,图6中的右端)附近的上表面。多个电极焊盘54(所包括的焊盘S1、S3)通过多个布线16,分别连接于设置在开关器件30的对应的电极焊盘34(即,焊盘T1、T3)。据此,多个电极焊盘54所包括的焊盘S1、S3分别连接于开关器件30所包括的IGBT 31的栅极端子(G)以及发射极端子(E)。
耐压结构部55是从施加于引线框架10的本体11的过电压中保护设置于控制器件50的芯片的上表面侧的各种控制电路等的结构。耐压结构部55设置于包围感测IGBT 51等的控制器件50的芯片周围以及芯片上表面的边缘部。关于耐压结构部55的构成,特别是剖面构成将在下文中描述。
作为一个示例,控制电路56、57形成于控制器件50的芯片中央,即,感测IGBT 51的图右侧的芯片内部。关于构成控制电路56、57的有源元件的构成,特别是剖面构成将在下文中描述。
另外,在从与ECU独立的电源接收电源电压的情况下,可以设置用于连接电源而向控制电路56、57供给电源电压的接口用电极焊盘(未图示)。接口用电极焊盘可以经由布线(未图示)连接到与端子11b、12、13并列地设置的电源用端子。
图7是关于图6的基准线BB的剖视图,且显示控制器件50,特别是感测IGBT 51、构成控制电路56、57的有源元件以及耐压结构部55的剖面结构。控制器件50的芯片与开关器件30的芯片相同,包括引线框架10的本体11(即,集电极45)以及在集电极45上依次层叠的成为p+型集电极区域的p+型半导体基板71、n+型缓冲区域72和n-型漂移区域73。此外,在芯片的表面层的中央右侧,在n-型漂移区域73上设置有p型基区65。在芯片的表面层的左侧,即n-型漂移区域73上设有感测IGBT 51的表面元件结构,在芯片的表面层的右侧,即p型基区65上设有构成控制电路56、57的有源元件、并且在芯片周围与表面层的边缘部上设置有耐压结构部55。
感测IGBT 51的表面元件结构包含p+型区域(即,p+型阱)60、p型基区61、n+型发射极区域62、栅极63、发射极64。除了以下几点之外,这些各部分与开关器件30的IGBT 31相同地形成。
p+型区域60的扩散深度D60小于开关器件30的p+型区域40的扩散深度D40(即,D60<D40)。换言之,在p+型区域60和n+型缓冲区域72之间的n-型漂移区域73的厚度大于开关器件30中的p+型区域40和n+型缓冲区域22之间的n-型漂移区域23的厚度。从而,控制器件50的耐压变得与开关器件30的耐压为相同程度(例如,600V)或者更高(例如,700V)。因此,在产生正的浪涌电压时,与感测IGBT 51相比IGBT 31先击穿,浪涌电流选择性地流向击穿耐量高的开关器件30(即,闩锁),由此保护控制器件50的特别是击穿耐量低的控制电路56、57。这在特别是如静电浪涌(ESD浪涌)那样的施加比CG间ZD 32等保护电路动作更急剧的浪涌电压的情况下有效。
另外,n+型缓冲区域72的杂质浓度低于开关器件30的n+型缓冲区域22的杂质浓度。据此,控制器件50的发射极-集电极间的耐压变得与开关器件30的发射极-集电极间的耐压相同或者更高。因此,在产生负浪涌时,浪涌电流选择性地流向击穿耐量高的开关器件30,由此保护控制器件50的特别是击穿耐量低的控制电路56、57。
控制电路56、57的有源元件例如包括耗尽型MOSFET,具有n+型源极区域66、n+型漏极区域67、n-型区域68、栅极69a、源极69b、漏极69c。n+型源极区域66以及n+型漏极区域67分别配置在p型基区65的表面上的一侧以及另一侧(即,图7的右侧以及左侧)。n-型区域68是与n+型源极区域66以及n+型漏极区域67相比杂质浓度低的n型的区域,配置在p型基区65的表面上,且n+型源极区域66与n+型漏极区域67之间。栅极69a被栅极绝缘膜覆盖而配置在n-型区域68之上。源极69b以与n+型源极区域66接触的方式配置在n+型源极区域66上。漏极69c以与n+型漏极区域67接触的方式配置在n+型漏极区域67上。
另外,集电极45是引线框架10的本体11的一部分,与芯片的整个背面接触。集电极45是与开关器件30共有的。发射极64配置在芯片的表面侧,与此对应地,包括p+型区域60(p+型阱)的感测IGBT 51的表面元件结构以及构成控制电路56、57的有源元件设置在芯片的表面侧。
另外,在本实施方式中,虽然将感测IGBT 51的集电极区域、设置有p+型区域60的区域以及基区设为p型,将缓冲区域、漂移区域以及发射极区域设为n型,但这是一个示例,相反地,也可以将感测IGBT 51的集电极区域、设置有p+型区域60的区域以及基区设为n型,将缓冲区域、漂移区域以及发射极区域设为p型。另外,虽然将控制电路56、57的有源元件的基区设为p型,将源极区域、漏极区域以及设置有n-型区域68的区域设为n型,但这是一个示例,相反地,也可以将控制电路56、57的有源元件的基区设为n型,将源极区域、漏极区域以及设置有n-型区域68的区域设为p型。
在控制器件50中,构成控制电路56、57的有源元件设置于在引线框架10的本体11(即,集电极45)上依次层叠的p+型半导体基板71、n+型缓冲区域72以及n-型漂移区域73之上。这些区域与开关器件30的p+型半导体基板21、n+型缓冲区域22以及n-型漂移区域23是共同的。因此,控制器件50通过具有这些区域,可以得到至少与开关器件30的耐性相同程度的耐性,特别是相对于施加于发射极与集电极之间的过电压的耐性。
耐压结构部55通过在芯片的周围设置包围感测IGBT 51的表面元件结构以及控制电路56、57的有源元件等的固定宽度的周边区域而形成。在该区域中不包括构成表面元件结构的p+型区域60等载流子区域。从而,在由于产生负浪涌而从发射极64经由芯片外缘向集电极45流通浪涌电流时,特别地,通过使足够宽度的n-型漂移区域73介于发射极64下的p+型区域60和芯片外缘之间,可以得到足够的耐性。
作为一个示例,耐压结构部55通过在芯片上表面的边缘部进一步设置p+保护环75、n+沟道截断区域76、绝缘层74、截断电极78以及钝化膜79而形成。这些各部分与开关器件30的耐压结构部35相同地形成。从而,在从集电极45经由芯片外缘向发射极64施加浪涌电压时,或者从发射极64经由芯片外缘向集电极45施加浪涌电压时,会经由周边区域或者多个p+保护环75以及截断电极78,由此使芯片表面上的电位稳定。
通过在控制器件50与开关器件30同样地设置耐压结构部,能够将集电极45在控制器件50与开关器件30中共有,即能够共用集电极电位。从而,不需要用于分离各个芯片的电位的分割框架、绝缘层等,可以简单地构成各个芯片。
进一步地,通过例如将周边区域的宽度规定得大,使耐压结构部55构成为相对于开关器件30的耐压结构部35具有高的耐压。从而,控制器件50与开关器件30相比,相对于施加到发射极64与集电极45之间的过电压的耐性变高,例如在产生负浪涌时,浪涌电流选择性地流向击穿耐量高的开关器件30,由此保护控制器件50的特别是击穿耐量低的控制电路56、57。
另外,CG间ZD 32对于低的浪涌电压发挥作用,由p+型区域40与60的扩散深度之差产生的耐压对于中等程度的浪涌电压发挥作用,耐压结构部35与55的耐压之差对于高的浪涌电压发挥作用,而保护控制电路56、57。
图8显示点火器100所包括的开关器件30以及控制器件50的制造流程。但是,因为开关器件30和控制器件50的制造流程基本相同,因此在这里对开关器件30的制造流程进行说明。
在步骤S1,形成外延基板。外延基板通过在成为p+型集电极区域的p+型半导体基板21的上表面依次外延生长n+型缓冲区域22以及n-型漂移区域23而形成。另外,在外延基板(即,n-型漂移区域23)上,形成IGBT 31的表面元件结构。
在步骤S2,例如通过热氧化,在外延基板的上表面(即,n-型漂移区域23的上表面)上形成初期氧化膜。
在步骤S3,形成p型基区41。对于p型基区41,通过光刻以及蚀刻而形成具有与p型基区41的形状对应的开口的抗蚀剂掩模,并利用该抗蚀剂掩模注入p型杂质,通过热处理(沟道驱动(Channel Drive))使p型杂质活化,从而形成。
在步骤S4,形成p+型区域40。对于p+型区域40,通过对初期氧化膜进行图案化而形成具有与p+型区域40的形状对应的开口的氧化膜掩模,并利用该氧化膜掩模注入p型杂质,通过热处理(阱驱动(Well Drive))使p型杂质活化,从而形成。活化后,去除氧化膜掩模。
在步骤S5,在IGBT 31的各个元件之间,通过LOCOS氧化来形成LOCOS膜。
在步骤S6,在外延基板上形成栅极氧化膜。
在步骤S7,形成栅极43。在栅极氧化膜上沉积未掺杂的多晶硅膜,并将外延基板置于例如三氯氧磷(POCl3)气体氛围下,使多晶硅膜成为n型。另外,例如也可以通过沉积被掺杂为n型的多晶硅来形成n型掺杂的多晶硅膜。通过对该多晶硅膜进行图案化,形成栅极43。
在步骤S8,形成n+型发射极区域42。对于n+型发射极区域42,通过光刻以及蚀刻而形成具有与n+型发射极区域42的形状对应的开口的抗蚀剂掩模,并利用该抗蚀剂掩模注入n型杂质,通过热处理使n型杂质活化,从而形成。
在步骤S9,在外延基板的上表面,形成如BPSG(Boro-phospho silicate glass:硼磷硅玻璃)那样的层间绝缘膜。
在步骤S10,形成表面电极。选择性地去除层间绝缘膜,形成露出p+保护环25等的接触孔。在外延基板的整个上表面沉积例如铝硅(Al-Si)膜。通过对铝硅膜进行图案化,形成IGBT 31的发射极44、截断电极28等表面电极。
在步骤S11,以钝化膜(保护膜)覆盖外延基板的整个上表面。
在步骤S12,研磨外延基板的背面(即,p+型半导体基板21),确定基板的厚度。
在步骤S13,形成背面结构。将外延基板设置于引线框架10的本体11上,在基板的整个背面形成集电极45。从而,完成开关器件30。
图9显示具备点火器100的点火装置200的构成。作为一个示例,点火装置200,设置于汽车发动机的内燃机,并构成为包括点火器100、ECU 210、点火线圈220以及火花塞230。
点火器100是上述的一个示例的开关装置,通过其所包括的开关器件30来切换是否使电流在点火线圈220的初级线圈L1中流通。点火器100的端子(栅极端子)13连接于ECU210,端子(集电极端子)11b连接于点火线圈220的初级线圈L1,端子(发射极端子)12连接于成为接地的车体。
ECU 210向点火器100发送控制信号来控制其动作即发动机的动作。
另外,作为点火器100的接口用电源,可以进一步设置外部电源(未图示)。在ECU的控制信号的信号电压低的情况下、ECU的控制信号的信号电压显著降低的情况下、需要向多个接口供电的情况下等,可以根据需要来使用外部电源。外部电源连接于点火器100的控制器件50的接口用电极焊盘(未图示),向控制电路56、57等供给电源电压。
点火线圈220是生成在火花塞230放电的高电压的变压器。点火线圈220具有初级线圈L1以及次级线圈L2。初级线圈L1的一端连接于电源222,另一端连接于点火器100的端子(集电极端子)11b,即开关器件30。次级线圈L2的一端连接于电源222,另一端经由二级管224连接于火花塞230。
火花塞230设置于内燃机的燃烧室,将由点火线圈220供给的高电压进行放电,对燃料和空气的混合气体点火。
在点火装置200中,点火器100从ECU 210接收控制信号(ON信号),使开关器件30内的IGBT 31导通。从而,点火线圈220的初级线圈L1通电。点火器100从ECU接收控制信号(OFF信号),使IGBT 31关断。从而,点火线圈220的初级线圈L1的通电被切断。在该通电被切断时,在点火线圈220的初级线圈L1产生300V左右的电压,据此在次级线圈L2产生30kV左右的电压,并通过火花塞230放电。
根据本实施方式的点火器100,通过将开关器件30以及控制器件50形成为独立的芯片,开关器件30所包括的IGBT 31的寄生电流不在控制器件50流通,控制器件50所包括的控制电路变得不会由于寄生电流而引起动作不良。另外,不需要用于切断IGBT的寄生电流的自分离区,因此也可以小型地构成芯片。
另外,本实施方式的开关装置,作为一个示例,虽然列举了用于在汽车发动机中使用火花塞对混合气体点火的点火器,但是并不限于此,也可以作为用于例如驱动电机那样的功率器件的开关装置来使用。
以上,使用实施方式对本发明进行了说明,但本发明的技术范围并不限于上述实施方式所述的范围。对本领域的技术人员来说,可以对上述实施方式实施各种变更或者改进是显而易见的。通过权利要求书所述可以明确,实施这种变更或者改进的方式也可以均包含在本发明的技术范围内。
需要注意的是,权利要求书、说明书以及附图中所示的装置、系统、程序以及方法中的动作、顺序、步骤以及阶段等各种处理的执行顺序只要未特别地明示为“比……之前”“先于”等,另外,未将前处理的输出使用于后处理中,则可以通过任意顺序来实现。关于权利要求书、说明书以及附图中的动作流程,为了方便起见,使用“首先”“然后”等进行了说明,但并不意味着必须按照这个顺序实施。

Claims (12)

1.一种开关装置,其特征在于,具备:
导电体;
开关器件,其在第1面与所述导电体接触,并将所述第1面侧的第1端子与第2面侧的第2端子之间进行开关,所述第2面侧为所述第1面的相反侧;以及
控制器件,其在第3面与所述导电体接触,且具有设置于第4面侧的所述开关器件的控制电路以及从施加于所述导电体的过电压中保护所述控制电路的第1耐压结构部,所述第4面侧为所述第3面的相反侧。
2.根据权利要求1所述的开关装置,其特征在于,所述第1耐压结构部设置于所述控制器件的所述第4面的边缘部。
3.根据权利要求1或2所述的开关装置,其特征在于,所述开关器件具有从施加于所述导电体的过电压中保护所述第2面侧的电路的第2耐压结构部。
4.根据权利要求1~3中任意一项所述的开关装置,其特征在于,所述控制器件与所述开关器件相比,两面之间的耐压高。
5.一种开关装置,其特征在于,具备:
导电体;
开关器件,其在第1面与所述导电体接触,并将所述第1面侧的第1端子与第2面侧的第2端子之间进行开关,所述第2面侧为所述第1面的相反侧;以及
控制器件,其在第3面与所述导电体接触,且具有设置于第4面侧的所述开关器件的控制电路,所述第4面侧为所述第3面的相反侧,
其中,所述控制器件与所述开关器件相比,两面之间的耐压高。
6.根据权利要求1~5中任意一项所述的开关装置,其特征在于,所述控制器件以及所述开关器件自所述导电体侧起具有第1导电型集电极层、第2导电型缓冲层、第2导电型漂移层以及与发射极端子对应设置的第1导电型阱,所述发射极端子位于与所述导电体相反的面侧。
7.根据权利要求6所述的开关装置,其特征在于,所述控制器件与所述开关器件相比,第1导电型阱和第2导电型缓冲层之间的第2导电型漂移层更厚。
8.根据权利要求6或7所述的开关装置,其特征在于,所述控制器件与所述开关器件相比,第2导电型缓冲层的杂质浓度低。
9.根据权利要求1~8中任意一项所述的开关装置,其特征在于,
所述控制电路输入指示是否导通所述开关器件的控制信号,并将所述控制信号用作电源,根据所述控制信号控制所述开关器件内的开关元件的栅极电压。
10.根据权利要求1~9中任意一项所述的开关装置,其特征在于,所述开关器件包括作为开关元件的绝缘栅双极型晶体管。
11.根据权利要求1~10中任意一项所述的开关装置,其特征在于,
所述开关装置作为点火器发挥功能,
所述开关器件切换是否使电流在点火线圈的初级线圈中流通。
12.一种点火装置,其特征在于,具备:
权利要求1~11中任意一项所述的开关装置;
控制装置,其控制所述开关装置;以及
点火线圈,其具有与所述开关装置的所述开关器件连接的初级线圈以及连接于内燃机的火花塞的次级线圈。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1107999A (zh) * 1993-11-26 1995-09-06 富士电机株式会社 使用单触发点火脉冲的混合开关
JP2005322884A (ja) * 2004-04-09 2005-11-17 Denso Corp パワー半導体スイッチング素子及びそれを用いた半導体パワーモジュール
JP2012243930A (ja) * 2011-05-19 2012-12-10 Renesas Electronics Corp 半導体装置、半導体パッケージ、および半導体装置の製造方法
CN105121838A (zh) * 2013-04-11 2015-12-02 株式会社电装 点火装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6221267A (ja) 1985-07-19 1987-01-29 Sanyo Electric Co Ltd 集積回路
JP3182848B2 (ja) * 1992-03-24 2001-07-03 富士電機株式会社 半導体装置
KR100468809B1 (ko) * 2000-05-26 2005-01-29 가부시키 가이샤 히다치 카 엔지니어링 내연기관용 점화장치
JP3740008B2 (ja) * 2000-10-11 2006-01-25 株式会社日立製作所 車載イグナイタ、絶縁ゲート半導体装置及びエンジンシステム
JP5609087B2 (ja) 2009-12-04 2014-10-22 富士電機株式会社 内燃機関点火装置用半導体装置
JP5716749B2 (ja) * 2010-09-17 2015-05-13 富士電機株式会社 半導体装置
JP6098041B2 (ja) * 2012-04-02 2017-03-22 富士電機株式会社 半導体装置
JP6065536B2 (ja) 2012-11-15 2017-01-25 サンケン電気株式会社 半導体装置
US9920736B2 (en) * 2015-02-03 2018-03-20 Fairchild Semiconductor Corporation Ignition control circuit with current slope detection

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1107999A (zh) * 1993-11-26 1995-09-06 富士电机株式会社 使用单触发点火脉冲的混合开关
JP2005322884A (ja) * 2004-04-09 2005-11-17 Denso Corp パワー半導体スイッチング素子及びそれを用いた半導体パワーモジュール
JP2012243930A (ja) * 2011-05-19 2012-12-10 Renesas Electronics Corp 半導体装置、半導体パッケージ、および半導体装置の製造方法
CN105121838A (zh) * 2013-04-11 2015-12-02 株式会社电装 点火装置

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