CN107180786A - 半导体元件结构 - Google Patents
半导体元件结构 Download PDFInfo
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- CN107180786A CN107180786A CN201611108883.3A CN201611108883A CN107180786A CN 107180786 A CN107180786 A CN 107180786A CN 201611108883 A CN201611108883 A CN 201611108883A CN 107180786 A CN107180786 A CN 107180786A
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Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Geometry (AREA)
Abstract
本公开提供了一种半导体元件结构及其形成方法。半导体元件结构包括半导体基底及位于半导体基底上的介电层。介电层具有保护区域及较下部分,较下部分介于保护区域与半导体基底之间。保护区域较介电层的较下部分包含更多的碳。半导体元件结构还包括导电部件。导电部件穿过保护区域,且导电部件的较低部分由介电层的较下部分所围绕。
Description
技术领域
本公开涉及半导体元件结构及其形成方法,且特别涉及半导体元件结构的内连线结构。
背景技术
半导体集成电路(IC)工业已历经快速发展的阶段。集成电路材料及设计在技术上的进步已生产出许多代的集成电路。每一代的集成电路比前代的集成电路具有更小且更复杂的电路。
在集成电路发展的进程中,功能性密度(亦即每一个晶片区域中内连接元件的数目)已经普遍增加,而几何尺寸(亦即工艺中所能创造出最小的元件或线路)则是下降。这种微缩化的过程通常可因增加生产效率及降低相关成本而提供许多利益。
然而,这些进步也增加了集成电路在加工和制造上的复杂度。因为特征尺寸持续缩小,工艺也持续变得更加难以实施。因此,形成具有尺寸越来越小的可靠的半导体元件将是一个挑战。
发明内容
本公开的实施例提供一种半导体元件结构,包括:一半导体基底;一介电层,位于该半导体基底之上,其中该介电层具有一保护区域及一较下部分,该较下部分介于该保护区域与该半导体基底之间,其中该保护区域较该介电层的该较下部分包含更多的碳;以及一导电部件,穿过该保护区域,其中该导电部件的一较低部分由该介电层的该较下部分所围绕。
本公开的实施例提供一种半导体元件结构,包括:一半导体基底;一介电层,位于该半导体基底之上,其中该介电层具有一较下部分及一较上部分,且该较上部分较该较上部分致密;以及一导电部件,位于该介电层之中。
本公开的实施例提供一种半导体元件结构的形成方法,包括:于一半导体基底之上形成一介电层;于该介电层之中形成一导电部件;于该介电层的一较上部分中形成一保护区域;以及于该保护区域及该导电部件之上形成一蚀刻停止层。
附图说明
图1A-图1G显示根据一些实施例的半导体元件结构的数阶段工艺剖面图。
图2显示根据一些实施例的半导体元件结构的剖面图。
图3显示根据一些实施例,于形成半导体元件结构期间形成保护材料层的方法流程图。
附图标记说明:
100~半导体基底;
102~层间介电层;
104A、104B~导电部件;
106~介电层;
106L~较下部分;
106U~较上部分;
108A、108B~开口;
110A、110B~导电部件;
111L~较低部分;
111U~较高部分;
112~保护材料层;
112’~保护层;
114~保护区域(或保护层);
116~表面调整处理;
118~蚀刻停止层;
300~方法;
302、304~步骤。
具体实施方式
以下的公开内容提供许多不同的实施例或范例,以实施本案的不同特征。而本公开以下的公开内容是叙述各个构件及其排列方式的特定范例,以求简化说明。当然,这些特定的范例并非用以限定。例如,若是本公开以下的内容叙述了将一第一特征形成于一第二特征之上或上方,即表示其包含了所形成的上述第一特征与上述第二特征是直接接触的实施例,亦包含了尚可将附加的特征形成于上述第一特征与上述第二特征之间,而使上述第一特征与上述第二特征可能未直接接触的实施例。再者,在以下叙述提及在第二工艺前进行第一工艺,可包括第二工艺于第一工艺之后立刻进行的实施例,且亦可包括附加工艺于第一工艺与第二工艺之间进行的实施例。另外,本公开中不同范例可能使用重复的参考符号及/或标记。这些重复是为了简化与清晰的目的,并非用以限定各个实施例及/或所述外观结构之间的关系。
再者,为了方便描述图式中一元件或特征部件与另一(复数)元件或(复数)特征部件的关系,可使用空间相关用语,例如“在…之下”、“下方”、“较下部”、“上方”、“较上部”及类似的用语等。除了图式所绘示的方位之外,空间相关用语用以涵盖使用或操作中的装置的不同方位。所述装置也可被另外定位(例如,旋转90度或者位于其他方位),并对应地解读所使用的空间相关用语的描述。
本公开的一些实施例叙述如下。可于这些实施例中所述的步骤之前、期间、及/或之后进行其他附加的处理。所叙述的一些步骤可在不同的实施例中被置换或排除。可于半导体元件结构中增加附加的构件。以下所述的一些构件,可于不同的实施例中被置换或排除。虽然,所叙述的一些实施例具有特定的处理顺序,然而这些处理亦可改以其他符合逻辑的顺序进行。
图1A-图1G显示根据一些实施例的半导体元件结构的工艺剖面图。如图1A所示,提供或取得半导体基底100。在一些实施例中,半导体基底100包括半导体晶圆、一部分的半导体晶圆、或半导体晶粒(semiconductor die)。半导体晶圆(例如,硅晶圆)可包含元件构件(device elements),例如是主动元件及/或被动元件。在一些实施例中,半导体基底100包括硅或其他元素半导体材料(elementary semiconductor materials),例如锗(germanium)。在一些其他实施例中,半导体基底100包括化合物半导体(compoundsemiconductor)。化合物半导体可包括碳化硅(silicon carbide)、砷化镓(galliumarsenide)、砷化铟(indium arsenide)、磷化铟(indium phosphide)、其他适合的化合物半导体、或前述的组合。在一些实施例中,半导体基底100包括绝缘层上覆半导体(semiconductor-on-insulator,SOI)基底。SOI基底可借着使用氧注入隔离(implantationof oxygen,SIMOX)工艺、晶圆接合工艺、其他适用的方法、或前述的组合而制作。
在一些实施例中,于半导体基底100之上形成内连线结构(interconnectionstructure)。内连线结构包括层间介电层(interlayer dielectric layer)102及数个导电部件(multiple conductive features),其包括导电部件104A及104B。导电部件104A及104B可包括导电线路(conductive lines)、导电插塞(或通孔导电塞)(conductive vias)、及/或导电接触(conductive contacts)。在一些实施例中,层间介电层102包括数个介电子层(dielectric sub-layers)。数个导电部件(例如导电线路、导电插塞、及导电接触)形成在层间介电层102之中。
之后,于导电部件104A及104B与层间介电层102之上形成一或更多的介电层及导电部件以继续形成内连线结构。在一些实施例中,半导体基底100之中形成有数种元件构件(device elements)。数种元件构例如包括晶体管(例如,金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双载子接面晶体管(bipolar junctiontransistors,BJT)、高压晶体管、高频晶体管、p通道及/或n通道场效应晶体管(PFET/NFET)等)、二极管、或其他适用的元件。可使用数种工艺来形成元件构件,例如包括沉积、蚀刻、注入、微影、热处理、及/或其他适合的工艺。
元件构件通过半导体基底100上的内连线结构彼此相连而形成集成电路元件。例如,其中一导电部件104A及104B可通过一些导电部件而电性连接至形成于半导体基底100中的掺杂区(doped region),导电部件例如包括导电线路、导电插塞、及/或导电接触。集成电路元件包括逻辑元件、存储器元件(例如,静态随机存取存储器,SRAMs)、无线射频元件(RF)、输入/输出(I/O)元件、单晶片系统(system-on-chip,SoC)元件、影像感测元件(imagesensor devices)、其他合适类型的元件、或前述的组合。
如图1A所示,根据一些实施例,于层间介电层102及导电部件104A及104B之上沉积介电层106。在一些实施例中,于介电层106与层间介电层102之间形成蚀刻停止层(未显示)。蚀刻停止层可用以辅助后续于介电层106中形成开口。开口可用来容纳导电插塞及/或导电接触。
在一些实施例中,蚀刻停止层由氮化硅(silicon nitride)、氮氧化硅(siliconoxynitride)、碳化硅(silicon carbide)、氮碳化硅(silicon carbon nitride)、其他适合的材料、或前述的组合所制成。在一些实施例中,蚀刻停止层借着使用化学气相沉积(chemical vapor deposition,CVD)工艺、原子层沉积(atomic layer deposition,ALD)工艺、旋涂(spin-on)工艺、其他适用的工艺、或前述的组合而沉积。可对本公开的实施例作出许多变化及/或调整。在一些其他实施例中,未形成蚀刻停止层。
在一些实施例中,介电层106由低介电常数材料(low-k material)、氧化硅、氮氧化硅、硼硅酸盐玻璃(borosilicate glass,BSG)、磷硅酸盐玻璃(phosphoric silicateglass,PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、氟硅酸盐玻璃(fluorinated silicate glass,FSG)、其他适合的材料、或前述的组合所制成。在一些实施例中,介电层106大抵不包含氮。在一些实施例中,介电层106包括数个子层(sub-layers)。在一些实施例中,介电层106借着使用化学气相沉积工艺、原子层沉积工艺、旋涂工艺、喷涂(spray coating)工艺、其他适用的工艺、或前述的组合而沉积。
低介电常数材料的介电常数可小于二氧化硅的介电常数。例如,低介电常数材料的介电常数介于约1.5至约3.5之间。随着半导体元件密度增加,且电路构件的尺寸变得更小,电阻-电容时间迟滞(RC delay time)更为显著地影响电路效能。因此,使用低介电常数材料来形成介电层106有助于减轻电阻-电容时间迟滞,并增进电路效能。
可使用许多种类的低介电常数材料来形成介电层106。在一些实施例中,介电层106包括多孔介电材料(porous dielectric material)、有机高分子(organic polymer)、有机硅玻璃(organic silica glass)、氟氧化硅系列材料(SiOF series material)、氢硅酸盐(hydrogen silsesquioxane,HSQ)系列材料、甲基硅酸盐(methyl silsesquioxane,MSQ)系列材料、有机多孔系列材料(porous organic series material)、旋涂无机介电材料(spin-on inorganic dielectric)、旋涂有机介电材料(spin-on organicdielectric)、其他适合的材料、或前述的组合。在一些实施例中,介电层106包括硅、氧、及含碳材料(carbon-containing material)。碳元素可化学键结至硅元素或氧元素。
之后,根据一些实施例,如图1B所,于介电层106之中形成数个开口,其包括开口108A及108B。在一些实施例中,开口108A及108B分别露出导电部件104A及104B。在一些实施例中,开口108A及108B为通孔(via holes)、沟槽(trenches)、及/或接触孔(contactholes)。开口108A及108B的形成可涉及一或更多的微影工艺及蚀刻工艺。
如图1C所示,根据一些实施例,于开口108A及108B之中分别形成导电部件110A及110B。导电部件110A及110B可用作导电插塞、导电线路、及/或导电接触。在一些实施例中,导电部件110A及110B包括铜(copper)、铝(aluminum)、钨(tungsten)、钛(titanium)、钴(cobalt)、金(gold)、铂(platinum)、石墨烯(graphene)、碳纳米管(carbon nanotube)、其他适合的材料、或前述的组合。每一导电部件110A及110B可包括多个子层。
在一些实施例中,于介电层106与导电部件110A或110B之间形成阻挡层(barrierlayer)(未显示)。阻挡层可用以避免导电部件的金属离子扩散进入介电层106。在一些实施例中,阻挡层包括数个子层,其包括粘着层(未显示)。粘着层可用以增进阻挡层与后续所形成的材料层之间的粘合。
在一些实施例中,阻挡层由氮化钛(titanium nitride,TiN)、氮化钽(tantalumnitride,TaN)、钽(Ta)、钛(Ti)、钛钨(TiW)、其他适合的材料、或前述的组合所制成。粘着层可由钽、钛、其他适合的材料、或前述的组合所制成。可对本公开的实施例作出许多变化及/或调整。在一些其他实施例中,未形成阻挡层。
在一些实施例中,于介电层106之上沉积阻挡层及一或更多层的导电层以填充开口108A及108B。阻挡层及导电层可借着使用物理气相沉积(physical vapor deposition,PVD)工艺、化学气相沉积工艺、原子层沉积工艺、电化学沉积(electrochemicaldeposition)工艺、无电镀(electroless plating)工艺、旋涂工艺、喷涂工艺、其他适用的工艺、或前述的组合而沉积。
在一些实施例中,使用平坦化工艺来移除阻挡层及导电层的位于开口108A及108B以外的部分。因而,这些材料层所留下的部分形成了导电部件110A及110B,如图1C所示。在一些实施例中,平坦化工艺包括化学机械研磨(chemical mechanical polishing,CMP)工艺、研磨工艺(grinding process)、干式抛光工艺(dry polishing process)、蚀刻工艺、其他适用的工艺、或前述的组合。在一些实施例中,在平坦化工艺之后,介电层106的顶表面与导电部件110A及110B的顶表面大抵共平面。在一些其他实施例中,导电部件110A及110B的顶表面微幅高于介电层106的顶表面。
如图1D所示,根据一些实施例,于介电层106之上形成保护材料层(protectionmaterial layer)112。保护材料层112可用以于介电层106之中(或之上)形成保护区域(protection region)(及/或保护层)以保护介电层106免于在后续工艺期间受到损坏。在一些实施例中,保护材料层112包括数层子层。在一些实施例中,这些子层中的一些具有不同的材料。可将一或更多的材料导入介电层106之中以形成保护区域(及/或保护层)于介电层106之中(或之上)。
前述后续工艺可为涉及等离子体的工艺(plasma-involved process)及/或涉及离子轰击的工艺(process involving ion bombardment)。在一些实施例中,保护材料层112直接用来保护介电层106免于后续工艺期间受到损坏。保护材料层112的厚度可介于约至约之间。
在一些实施例中,保护材料层112为含硅、氧、及碳的材料(silicon,oxygen,andcarbon-containing material)。在一些实施例中,保护材料层112为含硅、氧、碳、及氮的材料(silicon,oxygen,carbon,and nitrogen-containing material)。在一些实施例中,保护材料层112包括高分子材料。在一些其他实施例中,保护材料层112为包含硅、氧、及碳的高分子材料。在一些其他实施例中,保护材料层112为包含硅、氧、碳、及氮的高分子材料。在一些实施例中,保护材料层112选择性形成于介电层106之上。在一些实施例中,保护材料层112大抵不形成于或留在导电部件110A及110B之上。
在一些实施例中,保护材料层112借着使用旋涂工艺、喷涂工艺、选择性化学气相沉积工艺、其他适用的工艺、或前述的组合而选择性形成于介电层106之上。图3显示根据一些实施例的工艺方法流程图,其叙述用以形成保护材料层112的方法300。
请参照图1D及图3,方法300包括步骤302,其中于介电层106与导电部件110A及110B之上涂布保护材料溶液(protection material solution)以于介电层106之上选择性形成保护材料层112。保护材料层112可几乎不形成于导电部件110A及110B之上。或者,保护材料层112可轻易地自导电部件110A及110B之上移除。在一些实施例中,借着使用旋涂工艺、喷涂工艺、其他适用的工艺、或前述的组合而将保护材料溶液涂布在介电层106与导电部件110A及110B之上。
在一些实施例中,保护材料溶液包括一种或更多化合物,其包含带电荷官能团(charged functional groups)。在一些实施例中,保护材料溶液中的一种或更多化合物所包括的带电荷官能团例如为OH-、NH+、P+、其他适合的官能团、或前述的组合。在一些实施例中,保护材料溶液中所使用的溶剂包括水、酒精(alcohol)、丙二醇甲醚醋酸酯(propyleneglycol monomethyl ether acetate)、乙二醇(ethylene glycol)、其他适合的溶剂、或前述的组合。
可将保护材料溶液涂布在介电层106与导电部件110A及110B之上。在一些实施例中,保护材料层112与介电层106之间的粘着力远强于保护材料层112与导电部件110A及110B之间的粘着力。因此,保护材料层112的原本沉积于导电部件110A及110B上的部分可借着使用例如水洗(water rinsing)的方式而轻易地移除。在一些其他情形中,大抵无保护材料层沉积于导电部件110A及110B之上。
在一些实施例中,仔细地调整保护材料溶液的pH值以确保保护材料层112选择性地形成于介电层106之上。在一些实施例中,保护材料溶液的pH值介于约2至约4之间。在一些情形中,若保护材料溶液的pH值大于4或大于5,保护材料层112与导电部件110A及110B之间的粘合力可能会太强。如此,保护材料层112的位于导电部件110A及110B上的部分可能会难以移除。水洗方式可能无法将保护材料层112的位于导电部件110A及110B上的不需要部分移除。在一些其他情形中,若保护材料溶液的pH值小于2,保护材料溶液可能会损坏导电部件110A及110B。
然而,本公开的实施方式不限于以上所述的实施例。在一些其他实施例中,保护材料溶液的pH值具有不同的范围。例如,保护材料溶液的pH值可介于约3至约5之间。
之后,如图1D-图1E所示,根据一些实施例,将一部分或全部的保护材料层112导入介电层106之中以形成保护区域(或保护层)114。在一些实施例中,方法300继续进行至步骤304,其中加热保护材料层112以将一部分或全部的保护材料层112扩散进入介电层106的较上部分(upper portion)106U以形成保护区域(或保护层)114。在一些实施例中,将保护材料层112导入介电层106之中以形成保护区域(或保护层)114,如图1D-图1E所示。在一些实施例中,加热保护材料层112以促使保护材料层112的材料扩散进入介电层106。
在一些实施例中,介电层106为多孔性材料(porous material),且介电层106的较上部分106U包含扩散自原本位于介电层106上的保护材料层112中的材料。来自保护材料层112的材料可部分或完全填充介电层106的较上部分106U中的孔洞。介电层106的较上部分106U及扩散自保护材料层112的材料可共同形成保护区域114(或保护层114)。在一些实施例中,保护区域114(或保护层114)直接接触介电层106的位于保护区域114(或保护层114)下方的较下部分(lower portion)106L。
如前所述,根据一些实施例,保护材料层112包括高分子材料。在一些实施例中,在高于该高分子材料的玻璃转换温度(glass transition temperature,Tg)的温度下加热保护材料层112。可使保护材料层112中的材料在受热后更容易地扩散进入介电层106。在一些实施例中,保护材料层112于温度介于约150度C至约400度C下加热。在一些实施例中,保护材料层112的加热时间介于约1分钟至约15分钟之间。
在一些实施例中,保护区域(或保护层)114的厚度介于约至约 之间。在一些实施例中,保护区域(或保护层)114的顶表面与导电部件110A及110B的顶表面大抵共平面。在这些(或一些)情形下,保护材料层112可完全扩散进入介电层106的较上部分106U而形成保护区域(或保护层)114。
如前所述,根据一些实施例,保护材料层112为含硅、氧、及碳的材料。在一些其他实施例中,保护材料层112为含硅、氧、碳、及氮的材料。在一些实施例中,保护区域(或保护层)114相较于介电层106的位于保护区域(或保护层)114下方的较下部分106L包含更多的碳。在一些实施例中,保护区域(或保护层)114的碳浓度延着自保护区域(或保护层)114的顶部朝向介电层106的较下部分106L的方向逐渐减小。
在一些实施例中,保护区域(或保护层)114相较于介电层106的较下部分106L包含更多的氮。在一些实施例中,保护区域(或保护层)114的氮浓度延着自保护区域(或保护层)114的顶部朝向介电层106的较下部分106L的方向逐渐减小。
在一些实施例中,保护区域(或保护层)114相较于介电层106的较下部分106L更为致密,较下部分106L介于保护区域(或保护层)114与半导体基底100之间。在一些实施例中,介电层106的较下部分106L厚于保护区域(或保护层)114。在一些实施例中,保护区域(或保护层)114的介电常数高于介电层106的较下部分106L的介电常数。可对本公开的实施例作出许多变化及/或调整。在一些其他实施例中,保护区域(或保护层)114的介电常数与介电层106的较下部分106L的介电常数大抵相同。
如图1F所示,根据一些实施例,于保护区域(或保护层)114与导电部件110A及110B之上进行表面调整处理(surface modification treatment)116以清洁导电部件110A及110B的表面。表面调整处理116可用以移除形成在导电部件110A及110B上的氧化物膜或含氧残留物。因此,可相应增进导电部件与后续所形成的导电构件之间的电性连接。
在一些实施例中,表面调整处理116为等离子体处理(plasma treatment)。在一些实施例中,等离子体处理中所使用的反应气体包括氮气、氨气(ammonia)、氢气、其他适合的气体、或前述的组合。在一些实施例中,保护区域(或保护层)114保护介电层106,使其免于在表面调整处理116其间受到损伤。例如,在表面调整处理116前间,可显著地减轻或避免介电层106中发生脱碳现象(carbon depletion)。介电层106的介电常数可维持在相对低的水平,其有助于减轻电阻-电容迟滞现象(RC delay),并增进元件效能。
如图1G所示,根据一些实施例,于保护区域(或保护层)114与导电部件110A及110B之上沉积蚀刻停止层118。在一些实施例中,蚀刻停止层118由氮化硅、氮氧化硅、碳化硅、氮钛化硅、其他适合的材料、或前述的组合所制成。在一些实施例中,蚀刻停止层118包括数个子层。在一些实施例中,蚀刻停止层118借着使用化学气相沉积工艺、原子层沉积工艺、旋涂工艺、其他适用的工艺、或前述的组合而沉积。在一些实施例中,蚀刻停止层118的形成涉及等离子体及/或离子轰击(plasma and/or ion bombardment)。在形成蚀刻停止层118期间,保护区域(或保护层)114保护介电层106免于受损伤。显著地增进介电层106的品质与可靠度。
如图1G所示,根据一些实施例,介电层106的较下部分106L与保护区域(或保护层)114共同形成围绕导电部件110A及110B的介电层106。介电层106的较上部分106U(保护区域(或保护层)114)围绕导电部件110A的较高部分(upper portion)111U,如图1G所示。介电层106的较下部分106L围绕导电部件110A的较低部分(lower portion)111L,如图1G所示。在一些实施例中,每一导电部件110A及110B穿过保护区域(或保护层)114。在一些实施例中,每一导电部件110A及110B穿过保护区域(或保护层)114及介电层106。
如前所述,保护材料层112可完全导入介电层106的较上部分106U而形成保护区域(或保护层)114。或者,保护材料层112可部分导入介电层106而形成保护区域(或保护层)114。在一些实施例中,保护材料层112的余留部分可于表面调整处理116及/或形成蚀刻停止层118期间被移除。在一些其他实施例中,进行其他工艺以移除保护材料层112的余留部分。然而,本公开的实施例不限于此。在一些其他实施例中,留下保护材料层112的余留部分。
图2显示根据一些实施例的半导体元件结构的剖面图。如图2所示,保护材料层112的未被导入介电层106之中的余留部分形成了保护层(protection layer)112’。保护层112’与保护区域(或保护层)114可共同保护介电层106免于在后续工艺前间受到损伤,后续工艺例如是表面调整处理116及/或形成蚀刻停止层118的工艺。例如,在涉及等离子体或离子轰击之后续工艺期间,可显著地减轻或避免脱碳现象发生于介电层106之中。介电层106的介电常数可因而维持在相对低的水平。可减轻电阻-电容迟滞,并增进电路效能。
本公开的实施例将一种或更多种的保护材料导入内连线结构的介电层中以形成保护区域。保护区域用以保护介电层免于在后续工艺期间受到损伤。后续工艺例如是一或更多涉及等离子体及/或离子轰击的工艺。由于受到保护区域的保护,显著地增进内连线结构的品质与可靠度。
根据一些实施例,提供了一种半导体元件结构。半导体元件结构包括半导体基底及位于半导体基底上的介电层。介电层具有保护区域及较下部分,较下部分介于保护区域与半导体基底之间。保护区域较介电层的较下部分包含更多的碳。半导体元件结构还包括导电部件。导电部件穿过保护区域,且导电部件的较低部分由介电层的较下部分所围绕。
在一些实施例中,还包括一蚀刻停止层,位于该保护区域及该导电部件之上。
在一些实施例中,其中该保护区域的顶表面与该导电部件的顶表面大抵共平面。
在一些实施例中,其中该保护区域较该介电层的该较下部分包含更多的氮。
在一些实施例中,其中该保护区域较该介电层的该较下部分更为致密。
在一些实施例中,其中该保护区域较该介电层的该较下部分具有更高的介电常数。
在一些实施例中,其中该保护区域直接接触该介电层的该较下部分。
在一些实施例中,其中该介电层的该较下部分大抵不包含氮。
在一些实施例中,其中该保护区域的一碳浓度,沿着自该保护区域的一顶部朝向该介电层的该较下部分的方向逐渐减小。
在一些实施例中,其中该保护区域的一氮浓度,沿着自该保护区域的一顶部朝向该介电层的该较下部分的方向逐渐减小。
根据一些实施例,提供了一种半导体元件结构。半导体元件结构包括半导体基底及位于半导体基底上的介电层。介电层具有较下部分及较上部分,且较上部分较较上部分致密。半导体元件结构还包括位于介电层中的导电部件。
在一些实施例中,其中该较上部分较该较下部分包含更多的氮。
在一些实施例中,还包括一蚀刻停止层,位于该介电层及该导电部件之上。
在一些实施例中,其中该较上部分的一碳浓度,沿着自该较上部分的一顶部朝向该介电层的该较下部分的方向逐渐减小。
在一些实施例中,其中该较下部分厚于该较上部分。
根据一些实施例,提供了一种半导体元件结构的形成方法。方法包括于一半导体基底之上形成介电层及于介电层之中形成导电部件。方法还包括于介电层的较上部分中形成保护区域。方法还包括于保护区域及导电部件之上形成蚀刻停止层。
在一些实施例中,还包括在形成该蚀刻停止层之前,于该保护区域及该导电部件之上进行一等离子体处理。
在一些实施例中,还包括于该介电层之上形成一保护材料层;以及将该保护材料层的一部分导入该介电层的该较上部分之中以形成该保护区域。
在一些实施例中,还包括于该介电层及该导电部件之上涂布一保护材料溶液以选择性地于该介电层之上形成该保护材料层;以及加热该保护材料层以使该保护材料层的该部分扩散进入该介电层的该较上部分以形成该保护区域。
在一些实施例中,其中该保护材料溶液的pH值介于约2至约4之间。
前述内文概述了许多实施例的特征,以使本领域技术人员可以从各个方面更佳地了解本公开。本领域技术人员应可理解,且可轻易地以本公开为基础来设计或修饰其他工艺及结构,并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本领域技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下,可对本公开进行各种改变、置换或修改。
虽然本公开已以数个较佳实施例公开如上,然其并非用以限定本公开,任何本领域技术人员,在不脱离本公开的精神和范围内,当可作任意的更动与润饰,因此本公开的保护范围当视后附的权利要求所界定者为准。
Claims (1)
1.一种半导体元件结构,包括:
一半导体基底;
一介电层,位于该半导体基底之上,其中该介电层具有一保护区域及一较下部分,该较下部分介于该保护区域与该半导体基底之间,其中该保护区域较该介电层的该较下部分包含更多的碳;以及
一导电部件,穿过该保护区域,其中该导电部件的一较低部分由该介电层的该较下部分所围绕。
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Application publication date: 20170919 |