CN107154427A - A kind of device architecture of reduction GaN device for power switching current collapses - Google Patents

A kind of device architecture of reduction GaN device for power switching current collapses Download PDF

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Publication number
CN107154427A
CN107154427A CN201610117877.8A CN201610117877A CN107154427A CN 107154427 A CN107154427 A CN 107154427A CN 201610117877 A CN201610117877 A CN 201610117877A CN 107154427 A CN107154427 A CN 107154427A
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gan
layer
power switching
switching current
reduction
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CN107154427B (en
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王茂俊
刘少飞
陶明
郝龙
郝一龙
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Peking University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a kind of device architecture of reduction GaN device for power switching current collapses.The structure includes the Mg implanted layers below Si substrates, GaN cushions, GaN channel layers, intrinsic AlGaN layer, mask medium layer, insulation gate dielectric layer, source, leakage, barrier metal layer and source electrode.The structure realizes enhanced GaNMOS in substrate Epitaxial growth AlGaN/GaN heterojunction structures formation two-dimensional electron gas conducting channel by etching away passivation layer and intrinsic AlGaN layer below area of grid.The present invention is by injecting Mg ions, it is connected in the P-type layer of source formation with GaN cushions, the P-type layer can provide a large amount of holes to GaN cushions in a short time, and shortening device is greatly reduced by the recovery time of OFF state to GaN cushions during ON state, thus conducting resistance.The present invention efficiently reduces the current collapse caused by GaN buffering layer defects, improves devices switch speed, significantly the electric property of optimization GaN power devices.

Description

A kind of device architecture of reduction GaN device for power switching current collapses
Technical field
The invention belongs to technical field of semiconductors, it is related to GaN base power electronic device structure and manufacture craft
Background technology
GaN is used as the representative of third generation semiconductor, high saturation drift velocity, high critical breakdown field big with energy gap By force, the advantages of high heat conductance, high concentration can be produced by strong spontaneous polarization effect when particularly GaN heterojunction structures undope Two-dimensional electron gas, superior performance makes it be had a wide range of applications in fields such as power electronics, frequency microwaves.
It is practical most severe that integrity problem using current collapse as representative is that GaN base device for power switching is eventually striking to One of problem.Current collapse causes device dynamic resistance to reduce, and adds the dynamic response time of device for power switching so that device Part reliability is substantially reduced.Surface and barrier layer trap, the GaN cushions of high resistant are considered as producing current collapse phenomenon The GaN cushions of key factor, wherein high resistant under drain terminal stress caused by current collapse be people research emphasis it One.The cushion of Si base GaN device for power switching often mixes C, causes to form pn-junction between raceway groove and cushion, and device is closed When closing, pn-junction exhausts at high drain voltages.After device is opened, because the hole in cushion recovers to need necessarily Time, channel electrons can not be recovered at once, so as to cause the generation of current collapse phenomenon.
Current collapse in GaN power devices greatly reduces the working characteristics of device, in order to solve this problem, is permitted Many research workers are exploring the method for reducing current collapse always, at present, reduce the main method of current collapse and have:1. surface Passivating technique, Si is deposited in device surface3N4Deng passivation layer, reduce influence of the surface defect to channel electrons;2. field plate techniques, Mainly using the field plate designs being connected with grid or source electrode, two electron gases in regulation and control raceway groove, so as to reduce current collapse; 3. energy band engineering, the different material by inserting, change the band structure of hetero-junctions, and then improve channel electrons concentration, reduce Current collapse.
At present, the method for GaN power device current collapses is reduced mainly by weakening surface or barrier layer trap to raceway groove electricity The influence of son realizes, and in widely used GaN power devices, and GaN cushions often adulterate certain density C, Fe The resistance to voltage levels of device are improved Deng element, but this often introduces a considerable amount of defects in GaN cushions, these defects Current collapse can be caused to a certain extent, and the current collapse that GaN cushions are caused does not have good solution.
The content of the invention
The present invention is primarily to preferably solve the problems, such as the current collapse in GaN device for power switching, it is proposed that Yi Zhonggai The device architecture entered, adds highly doped p type island region, and as hole source, it can provide sky for the C GaN cushions adulterated The injection in cave, shortens the time required for cushion returns to poised state after off- state stress disappearance from hole depletion, Jin Erjia The recovery of fast channel electrons, reduces the influence of current collapse.
The present invention technical thought be:A kind of improved device architecture is proposed, in the source of GaN base device for power switching, By injecting the p type island region of Mg ions formation higher-doped, the p type island region is connected with GaN cushions.Device is from closing conducting During, the p type island region can provide enough holes for cushion so that the recovery time in hole shortens in device cushion, The recovery time of corresponding channel electrons also shortens, so as to inhibit the current collapse of device.
According to above-mentioned mentality of designing, a kind of device architecture of reduction GaN device for power switching current collapses includes substrate, GaN cushions, GaN channel layers, intrinsic AlGaN potential barrier, mask medium layer, insulation gate dielectric layer, source, leakage, grid Mg implanted layers below metal level and source electrode;Mg implanted layers connect source electrode and cushion, and source electrode area injects more than Mg Aspect is accumulated so that part AlGaN potential barrier is still connected with source electrode;In substrate Epitaxial growth AlGaN/GaN heterojunction materials, And source electrode and drain electrode are formed on this structure;Defined in wafer surface below Mg injection zones and area of grid, area of grid Mask medium layer and AlGaN layer are etched away.
Described GaN device for power switching is Si bases GaN HEMT, GaN MOSFET or MIS-HEMT.
Each constituent of the structure and material category are as follows:
Described GaN channel layer thickness is between 0 and 20nm.
Described mask medium layer material can be:Si3N4、SiO2、SiON。
The material of described insulation gate dielectric layer is any one in following material:Si3N4、Al2O3、AlN、HfO2、 SiO2、HfTiO、Sc2O3、Ga2O3、MgO、SiNO。
The source electrode and drain electrode are:One in titanium, aluminium, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten etc. Plant or a variety of alloys.
The gate metal is one or more combinations of following conductive material:Platinum, iridium, nickel, gold, molybdenum, palladium, selenium, Beryllium, TiN, polysilicon, ITO.
Described Mg ion implantation concentrations are:1018~1020cm-3
Existing device architecture is different from, the beneficial effects of the invention are as follows:Propose a kind of reduction GaN device for power switching The structure of current collapse, this is a kind of new mentality of designing.In source injection Mg ion formation p type island region, and buffered with GaN Layer is connected so that cushion has enough hole injections during device is from closing to unlatching, shortens the recovery of depletion layer Time, so as to shorten the recovery time of channel current, reduce current collapse.The structure and known reduction current collapse knot Structure process compatible, can be combined with other methods, further weaken the influence of current collapse.
Brief description of the drawings
The structure of device of the present invention and the exemplary embodiment of the present invention can be described more fully hereinafter by referring to accompanying drawing, In accompanying drawing:
Fig. 1 is the overall sectional structure chart of device of the present invention.
Fig. 2~Figure 11 is a kind of diagrammatic cross-section of the embodiment of the present invention after each step manufacturing process, reflects this hair Bright technique manufacturing process.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Description.Described embodiment is only a kind of way of realization in the present invention, i.e. the present invention should not be construed as limited to herein The embodiment of elaboration.Based on the embodiment, those skilled in the art are fully conveyed the scope of the present invention to.
Reference picture 1, the order of the device architecture from bottom to top includes silicon substrate, GaN cushions, GaN raceway groove sheets successively AlGaN potential barrier, Si3N4 mask layers, insulation gate dielectric layer, source, leakage and barrier metal layer are levied, Mg implanted layers are located at source electrode Lower section, is connected with GaN cushions.Its preparation method comprises the following steps:
(1) as shown in Fig. 2 growing one layer of GaN cushion, then regrowth on a si substrate with MOCVD first One layer of intrinsic GaN layer, finally grows 24nm AlGaN.Intrinsic GaN can form two-dimensional electron gas with AlGaN boundaries.
(2) on Fig. 2 architecture basics, mesa-isolated is carried out first, active area is obtained, and then deposits one layer of SiO2, Make Mg ion implanting windows by lithography afterwards, by the use of SiO2 as mask layer, Mg ions are injected by ion implanting, P is formed Type doped region, by controlling ion implanting conditions so that the injection depth of Mg ions reaches the position of GaN cushions, concentration reaches To 1018~1020Cm-3, its profile is as shown in Figure 3 and Figure 4.
(3) on above architecture basics, by being lithographically formed source-drain electrode figure, then electron beam evaporation Ti/Al/Ni/Au Four kinds of metals, the metal electrode in source region and drain region are prepared using stripping technology, and quickly moved back in 900 DEG C of nitrogen atmospheres Fire 30 seconds, forms Ohmic contact, and its profile is as shown in Figure 5.
(4) on the basis of cross-section structure shown in Fig. 5, the blunt of Si3N4 is deposited with PECVD or ICPCVD method Change layer, the section of structure of formation is as shown in Figure 6.
(5) F base gas etching Si3N4 are used, area of grid are obtained, as shown in Figure 7.
(6) enhancement device is realized using the method for oxidation and wet etching in this embodiment.First with will carve The wafer for losing grid region is put into plasma system and aoxidizes 3min, as shown in figure 8, next with the HCl that ratio is 1: 10 Soak for 1min, so as to etch away intrinsic AlGaN potential barrier, form enhancement device as shown in Figure 9.
(7) step in (6) is constantly repeated, until the leakage current for testing out prepared device is zero, at this moment illustrates intrinsic AlGaN layer is etched completely, successfully realizes normally closed enhancement device.
(8) on the basis of (7), in wafer surface growth insulation gate dielectric layer, gate modulation structure, such as Figure 10 are formed It is shown.
(9) make by lithography after source, drain electrode, deposited by electron beam evaporation deposits Ni/Au alloys in recess region, then uses Stripping technology formation grid metal electrode, electrode is T-shaped grid structure, as shown in figure 11.Finally in a nitrogen environment to whole wafer Made annealing treatment, return of goods condition is the 10min that annealed at 400 DEG C.
(10) by above step, that is, obtain reducing the GaN device for power switching structures of current collapse, effectively suppression The current collapse of device is made.

Claims (11)

1. a kind of device architecture of reduction GaN device for power switching current collapses, it is characterised in that:The structure is from bottom to top Including:Si substrates, GaN cushions, GaN channel layers, intrinsic AlGaN layer, mask medium layer, insulation gate dielectric layer, Source, leakage and barrier metal layer, and below source electrode, and the Mg implanted layers being connected with GaN cushions.Wafer surface is defined Grid, source electrode and drain electrode, the AlGaN potential barrier and deposit of the normally closed characteristic (enhanced) of device by etching grid region The gate medium that insulate is obtained, and the Mg ion implanted layers below source electrode can reduce the current collapse of device.
2. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: Backing material is Si.
3. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: The thickness of raceway groove GaN layer is between 0 and 20nm.
4. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: The material of the mask medium layer can be:Si3N4、SiO2、SiON.
5. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: The material of insulation gate dielectric layer therein is any one in following material:Si3N4、Al2O3、AlN、HfO2、SiO2、 HfTiO、Sc2O3、Ga2O3、MgO、SiNO。
6. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: Source electrode therein and drain metal be one kind in titanium, aluminium, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten etc. or A variety of alloys.
7. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: Gate metal therein is one or more combinations of following conductive material:Platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.
8. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: Source region forms the P-type layer of high concentration by Mg ion implantings, and is connected with GaN cushions.
9. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: The Mg ion concentrations of source region injection are 1018~1020cm-3。
10. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: Mask medium layer below area of grid can be realized by ICP or RIE dry etchings.
11. the device architecture of reduction GaN device for power switching current collapses according to claim 1, it is characterised in that: AlGaN layer below area of grid can be rotten by wet etching, electrochemical corrosion, dry etching and dry etching and wet method The method that erosion is combined is realized.
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Cited By (4)

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Publication number Priority date Publication date Assignee Title
CN108493245A (en) * 2018-05-23 2018-09-04 江苏能华微电子科技发展有限公司 A kind of closed type gallium nitride HEMT device
CN110911484A (en) * 2019-11-22 2020-03-24 华南理工大学 Enhanced GaN HEMT device prepared by wet etching assisted doping and preparation method
CN113270478A (en) * 2021-04-23 2021-08-17 北京大学深圳研究生院 Compound semiconductor follow current power transistor
US20220199802A1 (en) * 2020-12-22 2022-06-23 Applied Materials, Inc. Implantation Enabled Precisely Controlled Source And Drain Etch Depth

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108493245A (en) * 2018-05-23 2018-09-04 江苏能华微电子科技发展有限公司 A kind of closed type gallium nitride HEMT device
CN108493245B (en) * 2018-05-23 2024-03-26 江苏能华微电子科技发展有限公司 Normally-off gallium nitride HEMT device
CN110911484A (en) * 2019-11-22 2020-03-24 华南理工大学 Enhanced GaN HEMT device prepared by wet etching assisted doping and preparation method
US20220199802A1 (en) * 2020-12-22 2022-06-23 Applied Materials, Inc. Implantation Enabled Precisely Controlled Source And Drain Etch Depth
US11721743B2 (en) * 2020-12-22 2023-08-08 Applied Materials, Inc. Implantation enabled precisely controlled source and drain etch depth
CN113270478A (en) * 2021-04-23 2021-08-17 北京大学深圳研究生院 Compound semiconductor follow current power transistor
CN113270478B (en) * 2021-04-23 2023-02-17 北京大学深圳研究生院 Compound semiconductor follow current power transistor

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