CN113270478A - Compound semiconductor follow current power transistor - Google Patents
Compound semiconductor follow current power transistor Download PDFInfo
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- CN113270478A CN113270478A CN202110443694.6A CN202110443694A CN113270478A CN 113270478 A CN113270478 A CN 113270478A CN 202110443694 A CN202110443694 A CN 202110443694A CN 113270478 A CN113270478 A CN 113270478A
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 238000010893 electron trap Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- -1 AlGaN/GaN Chemical class 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application discloses a compound semiconductor follow current power transistor. The method comprises the following steps: the electron trap comprises a substrate, a buffer layer and a barrier layer, wherein the buffer layer is arranged on the substrate, the barrier layer is arranged on the buffer layer, a source electrode, a drain electrode and a grid electrode are arranged on the barrier layer, the grid electrode is located between the source electrode and the drain electrode, a trap region used for forming an electron trap is arranged in the barrier layer, the trap region is located between the source electrode and the drain electrode, and the grid electrode is not in contact with the trap region. By arranging the trap region in the barrier layer, when the device works, positive and negative voltages applied to the grid electrode need to extract or inject electrons into the trap region, so that the device is smoothly switched on and off, the risk that the device is broken down or burnt by induced voltage is reduced, and the reliability of the compound semiconductor power transistor in a system is improved.
Description
Technical Field
The application relates to the technical field of transistors, in particular to a compound semiconductor follow current power transistor.
Background
At present, a power electronic converter mainly adopts a silicon-based power device, after development for more than 50 years, from circuit design to wafer manufacturing, various technical indexes are close to theoretical limits, and the requirements on high temperature, high frequency, high efficiency and high power density of a next generation power device are difficult to meet by adjusting or improving a device structure. Compared with a silicon-based power device, a trend of developing the industry has been to adopt a compound semiconductor device (such as gallium nitride) to construct a power electronic switching device, because the compound power device has the characteristics of smaller grid and drain capacitance, no parasitic body diode and the like, the compound power device is more suitable for application in the aspects of high frequency and small power, and meanwhile, due to the low intrinsic carrier concentration of the compound power device with high thermal conductivity and wide forbidden band, the compound semiconductor device can work under high temperature and high power density.
Compared with silicon material power electronic devices, the compound semiconductor power electronic device has higher working frequency, the device faces more severe electromagnetic interference due to high-frequency switching speed, and the device is likely to have non-ideal effects under high-frequency conditions due to parasitic parameters introduced by the device and layout wiring. Particularly, during the high-speed switching process of the device, the phenomenon of overshoot and oscillation of the circuit can be caused by a large current change rate or voltage change rate, and the electronic components are likely to be broken down by an excessively high voltage.
Disclosure of Invention
The present application is directed to solving at least one of the problems in the prior art. Therefore, the compound semiconductor follow current power transistor provided by the application can solve the problem of too fast switching of the device, avoid the situation that the device has a large current conversion rate and a large voltage conversion rate in a power system, and reduce the risk of burning the device.
A compound semiconductor freewheeling power transistor according to an embodiment of the present application includes: the electron trap comprises a substrate, a buffer layer and a barrier layer, wherein the buffer layer is arranged on the substrate, the barrier layer is arranged on the buffer layer, a source electrode, a drain electrode and a grid electrode are arranged on the barrier layer, the grid electrode is positioned between the source electrode and the drain electrode, a trap region used for forming an electron trap is arranged in the barrier layer, the trap region is positioned between the source electrode and the drain electrode, and the grid electrode is not contacted with the trap region.
According to the compound semiconductor freewheeling power transistor of the embodiment of the application, at least the following beneficial effects are achieved: by arranging the trap region in the barrier layer, when the device works, positive and negative voltages applied to the grid electrode need to extract or inject electrons into the trap region, so that the device is smoothly switched on and off, the risk that the device is broken down or burnt by induced voltage is reduced, and the reliability of the compound semiconductor power transistor in a system is improved.
According to some embodiments of the application, further comprising: and the passivation layer is arranged on the surface of the barrier layer.
According to some embodiments of the application, the passivation layer has a thickness of less than 5 μm.
According to some embodiments of the present application, the trap region is proximate to the gate.
According to some embodiments of the present application, the gate ends in a sector shape having a central angle greater than 90 degrees and less than 180 degrees.
According to some embodiments of the present application, a minimum distance of an end of the gate from a boundary of the active region is less than 1 μm.
According to some embodiments of the present application, the gate includes a first gate end and a second gate end, a slot region is formed between the first gate end and the second gate end, and the trap region is located in the slot region.
According to some embodiments of the present application, the first gate end and the second gate end are both fan-shaped, and a central angle of the fan-shaped is greater than 90 degrees and less than 180 degrees.
According to some embodiments of the application, a minimum distance between the first gate end and the second gate end is less than 0.5 μm.
According to some embodiments of the present application, a density of states of the trap region is greater than 0.05 μm-2。
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The present application is further described with reference to the following figures and examples, in which:
fig. 1 is a schematic diagram of a compound semiconductor freewheeling power transistor according to an embodiment of the present application;
FIG. 2 is a top view of a compound semiconductor free-wheeling power transistor of the embodiment of FIG. 1;
fig. 3 is a top view of a compound semiconductor free-wheeling power transistor according to another embodiment of the present application;
fig. 4 is a top view of a compound semiconductor free-wheeling power transistor according to another embodiment of the present application;
FIG. 5 is a circuit diagram of a compound semiconductor freewheeling power transistor according to an embodiment of the present application;
fig. 6 is a test graph of a compound semiconductor freewheeling power transistor according to an embodiment of the present application.
Reference numerals:
a passivation layer 170, a trap region 131, a first gate terminal 161, and a second gate terminal 162.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the positional descriptions, such as the directions of up, down, front, rear, left, right, etc., referred to herein are based on the directions or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific direction, be constructed and operated in a specific direction, and thus, should not be construed as limiting the present application.
In the description of the present application, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and the above, below, exceeding, etc. are understood as excluding the present number, and the above, below, within, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless otherwise expressly limited, terms such as set, mounted, connected and the like should be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the terms in the present application by combining the detailed contents of the technical solutions.
The compound semiconductor freewheeling power Transistor of the present application is a High Electron Mobility Transistor (HEMT), which is a heterojunction field effect Transistor that operates by two-dimensional Electron gas generated by a heterojunction, and commonly used is a heterojunction formed of iii-v group compounds such as AlGaN/GaN, AlGaAs/GaAs, and the like.
Some embodiments, referring to fig. 1 and fig. 2, fig. 1 is a cross-sectional view of the transistor a of fig. 2. The application provides a compound semiconductor follow current power transistor, including: the electron trap comprises a substrate 110, a buffer layer 120 and a barrier layer 130, wherein the buffer layer 120 is arranged on the substrate 110, the barrier layer 130 is arranged on the buffer layer 120, a source 140, a drain 150 and a gate 160 are arranged on the barrier layer 130, the gate 160 is positioned between the source 140 and the drain 150, a trap region 131 for forming an electron trap is arranged in the barrier layer 130, the trap region 131 is positioned between the source 140 and the drain 150, and the gate 160 is not in contact with the trap region 131.
The substrate 110 may be made of at least one of silicon, sapphire, silicon carbide, and aluminum nitride, the buffer layer 120 and the barrier layer 130 are used to form a conductive channel, the source electrode 140, the drain electrode 150, and the gate electrode 160 are deposited on the barrier layer 130 through a deposition process, and the electrode material may be at least one of Ti, Al, Ni, and Au. By an ion implantation process, an element such as Mg or C is implanted into the barrier layer 130, and a trap region 131 is formed in the barrier layer 130, and the trap region 131 is used to form an electron trap. The trap region 131 is located between the source 140 and the drain 150 and is not in metal contact with the gate 160, i.e. the gate 160 does not cover the surface of the trap region 131, so as to achieve a better freewheeling effect. The shape, size, number and density of the trap regions 131 can be selected according to the required threshold voltage, free-wheeling time and other parameters of the transistor, and the electrical parameters of the transistor can be influenced by changing the shape and structure of the gate 160, which is not limited herein.
The transistor is a normally-open structure, and by arranging the trap region 131, when the transistor is required to be turned off, the negative gate voltage enables the gate 160 to charge traps on the surface of the trap region 131, so that the transistor is turned off. When the transistor is to be turned on, the forward gate voltage will extract electrons in the traps in the slot region, and the transistor is turned on, so that the voltage and current conversion rate is reduced to a certain extent, and the risk that the transistor is burnt by the induced voltage in the high-frequency circuit application is reduced.
The threshold voltage of the transistor of the present application has a negative temperature coefficient, and when the operating temperature of the transistor is high, it becomes more difficult for the electron trap to trap electrons, requiring a larger reverse voltage to turn it off. The higher the working temperature is, the lower the threshold voltage of the transistor is, which shows that under the condition of constant gate voltage, the on resistance of the transistor is reduced along with the increase of the temperature, the power consumed on the transistor is also reduced, and the stability of the transistor in a system can be improved.
Some embodiments, further comprising: and a passivation layer 170, wherein the passivation layer 170 is arranged on the surface of the barrier layer 130. The passivation layer 170 may be SiN or the like, and the transistor may be protected by providing the passivation layer 170, and surface defects of the barrier layer 130 may be suppressed to improve reliability of the transistor.
In some embodiments, the thickness of the passivation layer 170 is less than 5 μm. The thickness of the passivation layer 170 is set according to the thickness of the barrier layer 130. For example, when the barrier layer 130 has a thickness of 15 to 20nm, the thickness of the passivation layer 170 needs to be less than 5 μm to ensure proper function of the transistor.
In some embodiments, the trap region 131 is proximate to the gate 160. Referring to fig. 2, the edge of the trap region 131 contacts the edge of the gate 160, and the trap region 131 is disposed at a position closest to the gate 160 to facilitate electron exchange between the gate 160 and the electron trap. In some other embodiments, the trap region 131 may be spaced apart from the gate 160.
In some embodiments, the end of the gate 160 is a fan shape, and the central angle of the fan shape is greater than 90 degrees and less than 180 degrees. The end of the gate electrode 160 may be provided in a convex sector shape in fig. 2 or in a concave sector shape in fig. 3, and the central angle of the sector structure is between 90 and 180 degrees. In this embodiment, the gate width at the end of the gate 160 is 1.5 μm, and the radius of the sector is less than 1 μm.
In some embodiments, the minimum distance from the end of the gate 160 to the active region boundary is less than 1 μm. The dashed lines in fig. 2 and 3 are boundaries of an active region, which is a region where a conductive channel is mainly formed between the source electrode 140 and the drain electrode 150.
In some embodiments, referring to fig. 4, the gate 160 includes a first gate end 161 and a second gate end 162, a slot region is formed between the first gate end 161 and the second gate end 162, and the trap region 131 is located in the slot region. The gate electrode 160 is configured to surround the drain electrode 150, so that the gate electrode 160 has two ends, namely a first gate end 161 and a second gate end 162, and a slot region is formed between the two gate ends, and the trap region 131 is formed by ion implantation into the barrier layer 130 through the slot region.
In some embodiments, the first gate end 161 and the second gate end 162 are fan-shaped, and the central angle of the fan-shaped is greater than 90 degrees and less than 180 degrees. The first gate end 161 and the second gate end 162 may be in a shape of a concave or convex sector, and may be arbitrarily arranged according to design requirements. In some other embodiments, the first gate end 161 and the second gate end 162 may have other shapes such as a rectangle.
In some embodiments, the minimum distance between the first gate terminal 161 and the second gate terminal 162 is less than 0.5 μm.
In some embodiments, the state density of the trap region 131 is greater than 0.05 μm-2。
The compound semiconductor freewheel power transistor of the present application is described in detail below, taking one specific embodiment as an example. Referring to FIG. 2, the source 140 and drain 150 metals are shaped in a large mannerThe small part is a square with a side length of 100 μm, the main body part of the gate electrode 160 is also a square with a side length of 100 μm, the gate width of the protruding end part of the gate electrode 160 is 1.5 μm, the end part of the gate electrode 160 is a fan shape protruding outwards, the radius of the fan shape is less than 1 μm, and the minimum distance of the fan shape from the boundary of the active region is less than 1 μm. One side of the trap region 131 is shaped like a sector of a recess complementary to the end of the gate 160, the width of the recess is the same as the gate width of the end of the gate 160, and the state density of the electron traps doped in the trap region 131 is greater than 0.05 μm-2。
Referring to fig. 5, in order to test the performance parameters of the transistor of the present application, the drain 150 of the transistor is connected to a dc voltage source through a resistor, the source 140 of the transistor is grounded, and the transistor is alternately operated in the on and off states by applying a driving signal to the gate 160. Referring to fig. 6, a waveform diagram of a driving voltage signal and an output voltage signal when a transistor is tested, when the driving voltage is higher or lower than a threshold voltage, the transistors are turned on or off after a certain time delay, so that the conversion rate of voltage and current is reduced, and the risk of burning of the transistors by induced voltage in high-frequency circuit application is reduced.
In the description of the present application, reference to the description of the terms "some embodiments," "examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the present application have been described in detail with reference to the drawings, but the present application is not limited to the embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present application. Furthermore, the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
Claims (10)
1. A compound semiconductor freewheeling power transistor characterized by comprising:
a substrate;
a buffer layer disposed on the substrate;
the barrier layer is arranged on the buffer layer, a source electrode, a drain electrode and a grid electrode are arranged on the barrier layer, the grid electrode is located between the source electrode and the drain electrode, a trap region used for forming an electron trap is arranged in the barrier layer, the trap region is located between the source electrode and the drain electrode, and the grid electrode is not in contact with the trap region.
2. A compound semiconductor freewheel power transistor according to claim 1 characterized in that it also includes: and the passivation layer is arranged on the surface of the barrier layer.
3. A compound semiconductor freewheel power transistor according to claim 2 characterized in that the thickness of the passivation layer is less than 5 μ ι η.
4. A compound semiconductor freewheel power transistor according to claim 1 characterized in that, the trap region is close to the gate.
5. A compound semiconductor free-wheeling power transistor according to claim 4 wherein the gate terminates in a sector having a central angle greater than 90 degrees and less than 180 degrees.
6. A compound semiconductor free-wheeling power transistor according to claim 5 wherein the minimum distance from the end of the gate to the active region boundary is less than 1 μm.
7. A compound semiconductor freewheeling power transistor according to claim 4, characterized in that the gate comprises a first gate end and a second gate end, a slot region being formed between the first gate end and the second gate end, the trap region being located in the slot region.
8. A compound semiconductor freewheel power transistor according to claim 7 characterized in that, the first gate terminal and the second gate terminal are both sector-shaped, the central angle of which is larger than 90 degrees and smaller than 180 degrees.
9. A compound semiconductor freewheel power transistor according to claim 8 characterized in that the minimum distance between the first gate terminal and the second gate terminal is smaller than 0.5 μ ι η.
10. A compound semiconductor free-wheeling power transistor according to claim 1 wherein the trap region has a density of states greater than 0.05 μm-2。
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| CN113270478B (en) | 2023-02-17 |
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