CN107154413A - 具有受光元件的半导体装置 - Google Patents

具有受光元件的半导体装置 Download PDF

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CN107154413A
CN107154413A CN201710119570.6A CN201710119570A CN107154413A CN 107154413 A CN107154413 A CN 107154413A CN 201710119570 A CN201710119570 A CN 201710119570A CN 107154413 A CN107154413 A CN 107154413A
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photo detector
semiconductor device
soi layer
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小山威
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Ablic Inc
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Abstract

具有受光元件的半导体装置,遮挡了不需要的光。在P型半导体衬底(11)的上表面形成多个光电二极管(51),在光电二极管(51)的表面隔着埋入氧化膜(12)设置绝缘氧化膜(31),在光电二极管与相邻的光电二极管之间隔着埋入氧化膜(12)设置SOI层(13),从而对倾斜入射等的不需要的光进行遮光。

Description

具有受光元件的半导体装置
技术领域
本发明涉及具有受光元件的半导体装置。
背景技术
作为半导体装置之一的CMOS图像传感器通常在受光部具有作为受光元件的、一维或二维地配置的像素阵列。受光部的像素阵列的像素利用由具有PN结的光电二极管形成的光检测器来构成。在各像素中,入射光若在半导体衬底内部被吸收则生成载流子,所生成的载流子在该光电二极管的耗尽层部重新复合,产生作为输出的电压或电流。此时,入射光在PN结的上层膜处产生反射、干涉,因而,产生与上层膜的膜厚偏差对应的输出的偏差,成为实用上的问题。而且存在由于光的倾斜入射所致的串扰的问题。另外,在期望的PN结以外的场所产生的载流子可能会成为暗电流的产生源。
作为改善这些问题的对策,提出了如下方法:利用金属布线层将除了受光元件区域以外的其他区域遮光,从而抑制光干涉和暗电流的产生。(例如,参照专利文献1)
专利文献1:日本特开2010-45280号公报
发明内容
但是,在引出用于进行内部电路与传感器部的电连接的布线的部分,无法完全遮光。此外,若遮光金属宽度大,则由于上层膜的应力迁移而产生空隙;若金属布线间隔窄,则由于小凸起而发生短路。因此,本发明的课题在于提供一种具有受光元件的半导体装置,其能够在不依赖于金属布线的情况下对不需要的光进行遮光。
为了解决上述课题,本发明如下构成光检测半导体装置的受光部分。
一种具有受光元件的半导体装置,受光元件由基于PN结的光电二极管构成,该PN结由第1导电型半导体衬底和形成于所述第1导电型半导体衬底的上表面的第2导电型层区域形成,该具有受光元件的半导体装置的特征在于,在所述光电二极管上设置氧化膜,在所述光电二极管与相邻的光电二极管之间,为了进行遮光,隔着埋入氧化膜设置由单晶硅形成的SOI层。
通过使用上述手段,利用SOI层对除受光元件区域以外的其他区域进行遮光,能够抑制光的反射、干涉、倾斜入射和抑制暗电流的产生。另外,由于不使用遮光用布线,因而能够确保布线布局的自由度。
附图说明
图1是本发明的具有受光元件的半导体装置的俯视图。
图2是本发明第1实施例中的具有受光元件的半导体装置沿着图1的A-A线的剖视图。
图3是表示相对于各波长的Si的光吸收的图。
图4是本发明第2实施例中的具有受光元件的半导体装置在与沿着图1的A-A线的截面相对应的位置上的剖视图。
图5是本发明第3实施例中的具有受光元件的半导体装置在与沿着图1的A-A线的截面相对应的位置上的剖视图。
图6是本发明第4实施例中的具有受光元件的半导体装置在与沿着图1的A-A线的截面相对应的位置上的剖视图。
图7是本发明第5实施例中的具有受光元件的半导体装置在与沿着图1的A-A线的截面相对应的位置上的剖视图。
标号说明
1:具有受光元件的半导体装置;10:SOI衬底;11:P型半导体衬底;12:埋入氧化膜;13:SOI层;21:N型层区域;22:高浓度N型半导体区域;23:高浓度P型半导体区域;31:绝缘氧化膜;41:阴电极;42:阳电极;51:光电二极管;L1:入射光。
具体实施方式
下面使用附图对具体实施方式进行说明。
【实施例1】
图1是本发明第1实施例中的具有受光元件的半导体装置的俯视图。在N型层区域21的周围形成由P型半导体衬底11构成的P型层区域,在P型层区域的周围形成P型杂质浓度高的高浓度P型半导体区域23,在其部分区域设置阳电极42。在N型层区域21中形成N型杂质浓度高的高浓度N型半导体区域22,在其部分区域设置阴电极41。
并且,如下文所述,在相邻的N型层区域21之间的区域,在由P型半导体衬底11形成的P型层区域和P型杂质浓度高的高浓度P型半导体区域23的表面,按照至少覆盖它们的方式,隔着氧化膜设置用于进行遮光的SOI层13。
图2是本发明第1实施例中的具有受光元件的半导体装置的剖视图,其是沿着图1的A-A的剖视图。从半导体衬底11的表面直到规定的深度间隔开地形成多个N型层区域21。在N型层区域21的上表面形成N型杂质浓度高的高浓度N型半导体区域22,经由该N型半导体区域22连接阴电极41。在N型层区域21与相邻的N型层区域21之间配置由P型半导体衬底11构成的P型层区域,在其上表面形成P型杂质浓度高的高浓度P型半导体区域23,尽管在本剖视图中未示出,但经由该P型半导体区域23连接阳电极42。
通过N型层区域21与半导体衬底11的PN结,形成光电二极管51。通过按照阴电极41的电位高于阳电极42的电位的方式施加偏压,耗尽层在半导体衬底11扩展,光电二极管51作为用于取入光生成的电荷的光感测区域发挥功能。
在半导体衬底11、N型层区域21、高浓度N型半导体区域22和高浓度P型半导体区域23上形成埋入氧化膜12。并且,在间隔开的多个N型层区域21之间,隔着由二氧化硅形成的埋入氧化膜12设置由单晶硅形成的SOI层13。在SOI层13和被开口而露出的埋入氧化膜12上形成绝缘氧化膜31,上述的阴电极41和阳电极42被设于在绝缘氧化膜31中开孔的接触孔内。
SOI层13可以是将半导体衬底11作为支承衬底、利用埋入氧化膜12而从半导体衬底11分离出的单晶硅层,或者也可以是利用埋入氧化膜12而与半导体衬底11粘在一起的单晶硅层。
另外,在图2中省略了上层的布线等,由于不需要为了遮光用途而使用布线,因而布线布局的自由度高。
对于SOI层13的厚度没有特别限制,但是,若相对于SOI层13的开口宽度不具有一定程度的SOI层13的厚度(=高度),则无法有效地吸收倾斜入射的光,串扰的抑制不充分。在截至目前的测量结果中,优选SOI层厚度>SOI层开口宽度*1.73。该厚度是SOI层13能够吸收仰角小于60度的倾斜入射光的厚度。另外,也需要同时考虑后述的SOI层13的厚度与所吸收的光的波段之间的关系。在SOI层13的厚度大于例如1μm的情况下,从应力的方面考虑,不优选利用多晶硅膜来替换SOI层13。这是由于,多晶硅膜通常由CVD形成,膜厚越厚,所形成的膜的应力越大。
在光L1入射到本结构的具有受光元件的半导体装置1中时,光L1透过绝缘氧化膜31以及埋入氧化膜12,照射光L1的各波长成分按照光能量到达半导体衬底11,产生载流子。若载流子扩散至到达PN结的耗尽层区域,则得到电压或电流形式的输出。
照射光L1在Si(硅)中的光吸收遵循下述朗伯定律。
Log10(J1/J0)=-αL
J0:入射到介质之前的光的强度
J1:在介质中移动时的光的强度
L:光的到达深度
α:吸收系数
图3是表示相对于各波长的Si(硅)的光吸收的图。纵轴表示到达光相对于入射光的强度比,横轴表示光的到达深度,光的波长越短,在硅中越会被吸收而容易衰减。入射光L1在配置有SOI层13的区域被SOI层13吸收,不会到达半导体衬底11。即,具有一定厚度的SOI层13发挥遮光的作用,这种情况下,不必考虑上层膜的反射,不会引起暗电流源载流子的产生。
SOI层13的厚度能够根据期望的波长的光进行调整。例如,在仅遮挡紫外光的情况下设SOI层13的厚度为0.05μm至1μm,在遮挡波长比可见光短的光的情况下设SOI层13的厚度为10μm~100μm,在遮挡红外光的情况下设SOI层13的厚度为100μm~1000μm。
另外,在本发明的具有受光元件的半导体装置的制造中,准备在P型半导体衬底11上隔着埋入氧化膜12形成了SOI层13的SOI衬底,在蚀刻除去了SOI层13的开口部形成光电二极管51。在蚀刻除去SOI层13时,埋入氧化膜12发挥蚀刻阻挡层的作用,能够容易地进行终点检测。
【实施例2】
图4是本发明第2实施例中的具有受光元件的半导体装置的截面,其是与沿着图1的A-A线的截面对应的剖视图。对于与图2相对应的部分附以相同编号。其与图2所示的第1实施例的不同点在于,为了排除光的倾斜入射的影响,SOI层13的开口区域比光电二极管51的区域狭窄。即为下述结构:N型层区域21的端部被SOI层13覆盖,这两者有重叠。
【实施例3】
图5是本发明第3实施例中的具有受光元件的半导体装置的截面,其是与沿着图1的A-A线的截面对应的剖视图。对于与图2相对应的部分附以相同编号。其与图2所示的第1实施例的不同点在于,在与SOI层13相同的开口区域对埋入氧化膜12进行了蚀刻。从而,在N型层区域21上直接形成绝缘氧化膜31。本结构在用于排除埋入氧化膜12与绝缘氧化膜31的界面处的光反射对于输出所带来的影响方面是有效的。
对于SOI层13的厚度没有特别限制,但是,若相对于SOI层13的开口宽度不具有一定程度的高度,则倾斜入射的光的吸收比例不足,串扰的抑制不充分。在截至目前的测量结果中,优选(SOI层厚度+埋入氧化膜厚度)>SOI层开口宽度*1.73。此处,SOI层13的开口宽度在结构上等于埋入氧化膜的开口宽度。
【实施例4】
图6是本发明第4实施例中的具有受光元件的半导体装置的截面,其是与沿着图1的A-A线的截面对应的剖视图。对于与图2相对应的部分附以相同编号。其与图2所示的第1实施例的不同点在于,在与SOI层13相同的开口区域对埋入氧化膜12进行了蚀刻,且SOI层13的开口区域比光电二极管51的区域狭窄。这是为了排除光的倾斜入射的影响、以及埋入氧化膜12与绝缘氧化膜31的界面处的光反射对于输出所带来的影响。
【实施例5】
图7是本发明第5实施例中的具有受光元件的半导体装置的截面,其是与沿着图1的A-A线的截面对应的剖视图。对于与图2相对应的部分附以相同编号。其与图2所示的第1实施例的不同点在于,为了排除光的倾斜入射的影响,使SOI层13的截面形成为梯形。该结构能够通过在进行SOI层13的蚀刻时的条件设定下减弱各向异性强度的程度来达成。该结构可通过与各向异性蚀刻组合、或者仅使用各向异性蚀刻来达成。
对于SOI层13的厚度没有特别限制,但是,若相对于SOI层13的开口宽度不具有一定程度的厚度(=高度),则倾斜入射的光的吸收比例不足,串扰的抑制不充分。在截至目前的测量结果中,优选SOI层厚度>SOI层开口宽度*1.73。

Claims (5)

1.一种具有受光元件的半导体装置,其具备多个基于PN结的光电二极管,该PN结由形成于第1导电型半导体衬底的上表面的第2导电型层区域和所述第1导电型半导体衬底形成,该具有受光元件的半导体装置的特征在于,具有:
由单晶硅构成的SOI层,其在所述光电二极管与相邻的光电二极管之间隔着埋入氧化膜而设置在所述第1导电型半导体衬底上;以及
氧化膜,其设置在所述光电二极管和所述SOI层上。
2.根据权利要求1所述的具有受光元件的半导体装置,其特征在于,
所述SOI层的厚度比遮挡的光的到达深度厚。
3.根据权利要求1所述的具有受光元件的半导体装置,其特征在于,
所述SOI层在俯视时与所述光电二极管重叠。
4.根据权利要求1~3中的任意一项所述的具有受光元件的半导体装置,其特征在于,
所述氧化膜由所述埋入氧化膜和形成在所述埋入氧化膜上的绝缘氧化膜构成。
5.根据权利要求1~3中的任意一项所述的具有受光元件的半导体装置,其特征在于,
所述氧化膜由绝缘氧化膜构成。
CN201710119570.6A 2016-03-03 2017-03-02 具有受光元件的半导体装置 Pending CN107154413A (zh)

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