CN107112308B - The manufacturing method of lead frame, semiconductor device, the manufacturing method of lead frame and semiconductor device - Google Patents
The manufacturing method of lead frame, semiconductor device, the manufacturing method of lead frame and semiconductor device Download PDFInfo
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- CN107112308B CN107112308B CN201580005842.9A CN201580005842A CN107112308B CN 107112308 B CN107112308 B CN 107112308B CN 201580005842 A CN201580005842 A CN 201580005842A CN 107112308 B CN107112308 B CN 107112308B
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- terminal
- lead
- scolding tin
- wall thickness
- wiring substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention provides a kind of lead frame, even if the moulding resin small using linear expansion coefficient, also can inhibit to crack in scolding tin of the portion of terminal of lead in conjunction with wiring substrate in temperature change.Lead frame 1 involved in present embodiment characterized by comprising leading part 2, with inner lead 3 and the outside lead 4 being connected with inner lead 3；And frame section 5, supporting wire portion 2, wherein, inner lead 3 is equipped with portion of terminal 3a, and portion of terminal 3a has the opposite face 3b opposite with the conductive pattern of wiring substrate, and the back side 3c with opposite face 3b opposite side, the peripheral part of portion of terminal 3a, which is equipped with scolding tin wall thickness, ensures portion 6, scolding tin wall thickness ensures that portion 6 is formed, and opposite face 3b is recessed towards the back side side 3c, and thinner than the middle section of opposite face 3b, the middle section of back side 3c does not form recess portion, is flat.
Description
Technical field
The present invention relates to the manufactures of a kind of lead frame, semiconductor device, the manufacturing method of lead frame and semiconductor device
Method.
Background technique
In the past, after being engaged metal lead with the conductive pattern of wiring substrate by scolding tin, then pass through mould
Resin is moulded to the mounting surface of lead (inner lead (Inner-lead)), wiring substrate and the electronics being assemblied on wiring substrate
The semiconductor device that component is packaged is by common cognition.Such semiconductor device can not have to improve heat dissipation performance
Have and be molded resin covering, the mounting surface of wiring substrate and the exposed face of opposite side are equipped with radiator (Heatsink)
But above-mentioned semiconductor device is since package dimension (Package size) is than switch (Switch) element etc.
Discrete (Discrete) product is big, so warpage of packaging assembly once occurs in temperature change, wiring substrate and radiator are connect
Contacting surface product will be reduced so as to cause heat dissipation performance decline.Warpage of packaging assembly can be swollen according to the line between moulding resin and wiring substrate
Swollen coefficient difference and occur.It is currently by using line to reduce warpage of packaging assembly degree when temperature change for this point
The small moulding resin of the coefficient of expansion is poor to reduce linear expansion coefficient.
Further more, in patent document 1, record is to process to be formed on lead with pin protrusion to have at the top of flat circular
(Top) protrusion, so that the scolding tin improved between lead and the lead (inner lead) inside semiconductor device engages reliably
Property.
Advanced technical literature
Patent document
1 special open 2011-249395 bulletin of patent document
Summary of the invention
As above, in order to reduce warpage of packaging assembly degree when temperature change, mould usually small using linear expansion coefficient
Mould resin.However, at that rate, the linear expansion coefficient difference between moulding resin and lead can become larger, and temperature change causes to draw again
When line is expanded/shunk, and the variation of lead can be limited because of moulding resin.Therefore, lead and wiring substrate will be connect
The scolding tin of conjunction applies very big stress.In particular, stress is easy to concentrate on the peripheral part of the front end of lead.As a result, for example
Under the environment violent for vehicle-mounted equal temperature change, has scolding tin and the resistance value increasing that cracking causes solder engagement portion to be divided occurs
Big possibility.
In patent document 1, due in order to carry out pin protrusion processing, it is necessary to which by the portion of terminal of lead front end, (scolding tin is attached
Face) area compare and become much larger in the past, therefore the problem of have the small-sized high density for interfering semiconductor device again.
As other means, for example, it is contemplated that be by advance wiring substrate mounting surface formed groove, then
Ensure that the depth of scolding tin wall thickness and groove is identical for scolding tin engagement is carried out after lead and groove contraposition, so that scolding tin be inhibited to open
It splits.But accurately lead and groove must carry after aligning in the case of this.Therefore, the contraposition warp of lead frame
Latitude and harsh will be become to the condition of each component (lead frame etc.) tolerance, as a result, producing leads to semiconductor device
The problem of increased costs.
The present invention is in view of problem above point, it is therefore an objective to even if providing a kind of moulding resin small using linear expansion coefficient,
Can be in temperature change, inhibition is led by the lead frame that scolding tin of the portion of terminal of lead in conjunction with wiring substrate cracks, partly
The manufacturing method of body device, the manufacturing method of lead frame and semiconductor device.
Lead frame involved in a kind of form of the invention characterized by comprising
Leading part, with inner lead and the outside lead being connected with the inner lead；And
Frame section supports the leading part,
Wherein, the inner lead is equipped with portion of terminal, and the portion of terminal has opposite with the conductive pattern of wiring substrate
Opposite face, and the back side with the opposite face opposite side,
The peripheral part of the portion of terminal, which is equipped with scolding tin wall thickness, ensures portion, and the scolding tin wall thickness portion of ensuring is formed, described
Opposite face is recessed towards the back side, and thinner than the middle section of the opposite face, and the back side does not form recess portion,
It is flat.
In addition, in the lead frame,
The scolding tin wall thickness ensures that the front end of the portion of terminal can also be at least arranged in portion.
In addition, in the lead frame,
The scolding tin wall thickness ensures that portion can also be configured to "U" word shape along the periphery of the portion of terminal.
In addition, in the lead frame,
The inner lead has the wire connections for being electrically connected the portion of terminal with the outside lead, the scolding tin
Wall thickness ensures that portion can also extend in the way of the wire connections from the portion of terminal towards the outside lead.
In addition, in the lead frame,
The scolding tin wall thickness portion of ensuring, which can also be, becomes wall thickness by the peripheral part progress die-casting process to the portion of terminal
It is formed after thin.
The manufacturing method of semiconductor device involved in a kind of form of the invention characterized by comprising
Prepare the process of wiring substrate, the wiring substrate has insulating substrate and is arranged on the insulating substrate
Conductive pattern；
Prepare the process of the lead frame；
In the process of the mounting surface installation electronic component of the wiring substrate；
The portion of terminal scolding tin of the lead frame is bonded on the process on the conductive pattern of the wiring substrate；
The mounting surface and the inner lead to the electronic component, the wiring substrate utilize potting resin
The process being packaged；And
The process that the frame of the lead frame is cut off.
Semiconductor device involved in a kind of form of the invention characterized by comprising
Wiring substrate, with insulating substrate and the conductive pattern being arranged on the insulating substrate, and in mounting surface
On electronic component is installed；
Leading part, with inner lead and the outside lead being connected with the inner lead；And
Potting resin portion, the mounting surface and the inner lead to the electronic component, the wiring substrate into
Row encapsulation,
Wherein, the inner lead is equipped with portion of terminal, and the portion of terminal has opposite with the conductive pattern of wiring substrate
Opposite face, and the back side with the opposite face opposite side, and be bonded on the conductive pattern by scolding tin,
The peripheral part of the portion of terminal, which is equipped with scolding tin wall thickness, ensures portion, and the scolding tin wall thickness portion of ensuring is formed, described
Opposite face is recessed towards the back side, and thinner than the middle section of the opposite face, and the middle section at the back side does not have
Recess portion is formed, is flat.
The manufacturing method of lead frame involved in a kind of form of the invention, for manufacturing the lead for having leading part
Frame, the outside lead that the leading part has inner lead and is connected with the inner lead, the inner lead are equipped with
Portion of terminal, the portion of terminal have the opposite face opposite with the conductive pattern of wiring substrate characterized by comprising
Die-casting process process, the die-casting process that metal sheet is compressed by the mold using upper and lower a pair,
In the interarea of one side of the metal sheet as the opposite face, the portion of terminal as the inner lead
On the part of peripheral part, formed thinner wall section, the thinner wall section be formed the opposite face be recessed towards the back side and
The shaped shape thinner than the middle section of the opposite face；And
The formation process of inner lead, the bottom for making cutting line B pass through the thinner wall section by pressing to wear the metal sheet
Face, to form the inner lead for ensuring portion equipped with scolding tin wall thickness in the peripheral part of the portion of terminal.
In addition, in the manufacturing method of the lead frame,
Before carrying out the die-casting process process, it can also further comprise: the metal sheet being carried out to press to wear processing,
Process is pressed to wear to form the preparation of the temporary interna lead of shape bigger than the inner lead.
In addition, in the manufacturing method of the lead frame,
In the die-casting process process, the thinner wall section of "U" word shape can also be formed along the periphery of the portion of terminal.
Invention effect
According to the present invention, the peripheral part of the portion of terminal of lead, which is equipped with scolding tin wall thickness, ensures portion, and the scolding tin wall thickness ensures portion
It is formed, the back side of the opposite face opposite with the conductive pattern of wiring substrate towards portion of terminal is recessed, and compares portion of terminal
Opposite face middle section it is thinner, the middle section at the back side does not form recess portion, is flat.In this way, it will be able to
In the periphery for the portion of terminal that stress is easy to concentrate, it is ensured that the wall thickness for the scolding tin for engaging the portion of terminal of lead with wiring substrate,
, also can be in the case where even if the moulding resin for using linear expansion coefficient small is as the potting resin of semiconductor device
When temperature change, inhibit the generation of scolding tin cracking.
Detailed description of the invention
Fig. 1 is the plan view of lead frame 1 involved in embodiments of the present invention.
(a) is the plan view of the front end portion of inner lead 3 in Fig. 2, is (b) side of the front end portion of inner lead 3
Figure, (C) is the cross-section diagram along I-I line of (a).
Fig. 3 A is the illustrated planar figure of the manufacturing method of lead frame 1 involved in embodiment.
Fig. 3 B is the illustrated planar figure of the manufacturing method of lead frame 1 involved in embodiment after Fig. 3 A.
(a) is the cross-section diagram along I-I line of Fig. 3 B (4) in Fig. 4, is (b) cross-section diagram along II-II line of Fig. 3 B (4).
Fig. 5 is the oblique view of semiconductor device 30 involved in embodiments of the present invention.
Fig. 6 is the cross-section diagram of the amplified semiconductor device 30 centered on the front end portion of inner lead 3.
Specific embodiment
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.In addition, with the structure of same function in each figure
It is noted as same symbol at element, the constituent element of same symbol is not repeated to be described in detail.
(lead frame)
Firstly, will be with regard to lead frame 1 involved in embodiments of the present invention, referring to Fig.1 and Fig. 2 is illustrated.
Lead frame 1 is as shown in Figure 1, have a plurality of leads portion 2, and support the frame section 5 in these a plurality of leads portions 2.Respectively
Leading part 2 has inner lead 3, and the outside lead 4 being connected with inner lead 3.In addition, as shown in Figure 1, lead frame 1
It is also equipped with a plurality of leads portion 13 towards leading part 2.For example, drawing when lead frame 1 is suitable for the semiconductor device of Switching Power Supply
Line portion 2 receives switch member as control terminal as power supply terminal, ground terminal and current output terminal etc., leading part 13
The control signal of part.
Inner lead 3 is in leading part 2, eventually by the part of (aftermentioned) encapsulation in resin-encapsulated portion 25.Inner lead 3 is such as
Shown in Fig. 2 (a) and Fig. 2 (b), there is portion of terminal 3a and wire connections 3d.Wire connections 3d and 4 phase of outside lead
Even, and it is electrically connected portion of terminal 3a with outside lead 4.
Portion of terminal 3a is as shown in Figure 1 and Figure 2, and the front end portion of inner lead 3 is arranged in.The inner lead 3 such as Fig. 2
(b) shown in, there is the opposite face 3b and back side 3c with opposite face 3b opposite side.Opposite face 3b is the conduction with wiring substrate
The opposite face of figure (conductive pattern 22 of aftermentioned wiring substrate 20), referred to as scolding tin attachment surface.Portion of terminal 3a such as Fig. 2 (b)
It is shown, 3 bending of inner lead is formed as to the front end portion of inner lead 3 by bending part 3e.
As shown in Fig. 2 (a)~(c), the peripheral part of portion of terminal 3a is equipped with for ensuring that the scolding tin wall thickness of scolding tin wall thickness ensures
Portion 6.The scolding tin wall thickness ensures that portion 6 is formed, and opposite face 3b is recessed towards the back side side 3c, and the central area than opposite face 3b
Domain is thinner.In addition, the middle section of the back side 3c of portion of terminal 3a does not form recess portion, is as shown in Fig. 2 (b) and Fig. 2 (c)
Flat.
More specifically, scolding tin wall thickness ensures that such as Fig. 2 (a) of portion 6 is shown, and the periphery along portion of terminal 3a is configured to "U"
Word shape.In this way, it will be able to ensure scolding tin wall thickness in the periphery overall region of portion of terminal 3a.As a result, no matter matching
Line substrate whichaway (for example, long direction or short direction) warpage, since scolding tin wall thickness is ensured that, so can press down
The generation of scolding tin cracking processed.
Scolding tin wall thickness ensures that portion 6 is to pass through as be described hereinafter about as the detailed description in the explanation of the manufacturing method of lead frame 1
The die-casting process of the peripheral part of portion of terminal 3a (coining processing (Coining process)) is made to be formed after wall thickness thinning.
Further more, scolding tin wall thickness ensures that portion 6 is not limited to "U" word shape, as long as the end that the stress that scolding tin is arranged in most is concentrated
It can on the front end (the region C1 in Fig. 2 (a)) of sub-portion 3a.
In addition, scolding tin wall thickness ensures that portion 6 can also be from portion of terminal 3a towards outside lead as shown in Fig. 2 (a) and Fig. 2 (b)
4 extend in the way of wire connections 3d.In this way, it will be able to further improve between portion of terminal 3a and wiring substrate
The reliability of scolding tin engagement.
As above, in the lead frame 1 involved in embodiment, the peripheral part of the portion of terminal 3a of inner lead 3 is equipped with
Scolding tin wall thickness ensures portion 6.In this way, when portion of terminal 3a being engaged with the conductive pattern of wiring substrate using scolding tin, it will be able to
In the periphery for the portion of terminal 3a that stress is easy to concentrate, ensure to be equivalent to scolding tin wall thickness ensures the scolding tin wall thickness of depth in portion 6 more.By
It can play the role of padded coaming when stress occurs in scolding tin, therefore ensure that portion 6 will mitigate end by the way that scolding tin wall thickness is arranged
The stress of sub-portion 3a periphery.So according to the present embodiment, even if using linear expansion coefficient small moulding resin the case where
Under, it can also inhibit in temperature change by the portion of terminal 3a of leading part 2 and wiring substrate (such as aftermentioned wiring substrate 20)
The scolding tin of engagement cracks.
Further, when by the installation of lead frame 1 to wiring substrate, since to ensure that portion 6 can be absorbed extra for scolding tin wall thickness
Scolding tin, therefore the solder bridge being able to suppress between adjacent conductive pattern.
In addition, in the present embodiment, it, can since scolding tin wall thickness ensures that portion 6 is formed by die-casting process
In the case where not expanding the area of portion of terminal, setting scolding tin wall thickness ensures portion 6.So the semiconductor of lead frame 1 has been used to fill
Enlargement will not be incurred by setting (for example, aftermentioned semiconductor device 30), and it is possible to realize the miniaturization of semiconductor device height
It is densification.
In addition, the explanation in the manufacturing method of semiconductor device as be described hereinafter, due to installing by lead frame 1 to wiring substrate
When necessary aligning accuracy with do not changed in the past, therefore the rising of semiconductor device cost can be prevented.
(manufacturing method of lead frame)
Next, the manufacture of just above-mentioned lead frame 1 is illustrated referring to Fig. 3 A and Fig. 3 B.
Firstly, preparing the laminal metal sheet 10 being made of copper alloy.Then, as shown in Figure 3A, to the metal
Processing is formed in light sheet 10, to form the temporary interna lead 11 (preform process) than the bigger shape of inner lead 3.
In addition, also there is the case where without this preform process.
Next, being the week using mold (not shown) a pair of up and down to temporary interna lead 11 as shown in Fig. 3 A (2)
The die-casting process (die-casting process process) that edge (metal sheet 10) is compressed.In Fig. 3 A (2), die-casting process region A
Indicate the range of progress die-casting process.Make the peripheral part of temporary interna lead 11 only as shown in Fig. 3 B (3) by die-casting process
The part for being equivalent to compressed volume size expands outward, forms thinner wall section 12.
For in further detail, by die-casting process, in the peripheral part (metal sheet 10) of temporary interna lead 11
In the interarea (face as opposite face 3b) of one side, on the part of the peripheral part of the portion of terminal 3a as inner lead 3, formed
The thinner wall section 12 of shaped shape.The thinner wall section 12 is formed opposite face 3b and is recessed towards the back side side 3c, and than opposite face 3b
Middle section it is thinner.Further more, the periphery along portion of terminal 3a can also be formed and be in the thinner wall section 12 of "U" word shape.But,
The shape of thinner wall section 12 is that corresponding scolding tin wall thickness ensures the shape in portion 6 to determine, is not limited to "U" font.
Next, being pressed to wear to metal sheet 10 and (press to wear process again) is that cutting line B is passed through as shown in Fig. 3 B (3)
Thinner wall section 12.In this way, as shown in Fig. 3 B (4), Fig. 4 (a) and Fig. 4 (b), the peripheral part for being formed in portion of terminal 3a is equipped with weldering
Tin wall thickness ensures the inner lead 3 in portion 6.Scolding tin wall thickness ensures to be formed opposite shown in portion 6 such as Fig. 3 B (4) and Fig. 4 (b)
Face 3b is recessed towards the back side side 3c, and the middle section C2 than opposite face 3b is thinner.
As above, according to the present embodiment, by die-casting process, portion of terminal 3a lesser to area also can be easily
It is processed.By like this to inner lead 3 carry out die-casting process can while avoiding the enlargement of portion of terminal 3a,
Forming scolding tin wall thickness in the peripheral part of portion of terminal 3a ensures portion 6.
(semiconductor device)
Next, putting up with the semiconductor device 30 using above-mentioned lead frame 1, it is illustrated referring to Fig. 5 and Fig. 6.?
In Fig. 5, in order to show the internal structure of semiconductor device 30, it is assumed that potting resin portion 25 is transparent and illustrates.In addition, Fig. 6
Although the cross-section diagram of the amplified semiconductor device 30 centered on the front end portion of inner lead 3, not shown to have envelope
Fill resin portion 25.
Semiconductor device 30 is as shown in figure 5, have: wiring substrate 20；Scolding tin is bonded on the leading part on wiring substrate 20
2,13；Potting resin 25；Switch element 24, the thermistor (Thermistor) 28, Yi Jifen being mounted on wiring substrate 20
Leakage resistance (Shunt resistor) 29；And connecting line (Wire) 27.
Wiring substrate 20 is as shown in fig. 6, with insulating substrate 21 and the conductive pattern being arranged on insulating substrate 21
22,23.Insulating substrate 21 is for example made of ceramics, but not limited to this.In addition, conductive pattern 22,23 is for example made of copper, but not
It is limited to this.Further more, conductive pattern 23 for example in order to improve thermal diffusivity, is connected with radiator (not shown).
On the mounting surface (face for being formed with conductive pattern 22) of wiring substrate 20, various electronic components are installed.For example, peace
The switch element 24, thermistor 28 and shunt resistance 29 of power MOSFET etc. are installed on dress face.These electronic components with
It is electrically connected between conductive pattern 22 and by connecting line 27 between resistance component.In this way, such as switch electricity is just constituted
Source circuit.
Potting resin portion 25 is made of the resin after hardening, and will: the mounting surface of wiring substrate 20 shown in fig. 5, peace
Electronic component, connecting line 27 and inner lead 3 on wiring substrate 20 are packaged.
In semiconductor device 30, as shown in fig. 6, the opposite face 3b of the portion of terminal 3a of inner lead 3 and wiring substrate 20
Conductive pattern 22 it is opposite, and engaged by scolding tin 26 with conductive pattern 22.
Ensure portion 6 since the peripheral part of portion of terminal 3a is equipped with scolding tin wall thickness, the scolding tin at the peripheral part of portion of terminal 3a
26 wall ratio middle section is thick to be equivalent to the thickness that scolding tin wall thickness ensures the depth in portion 6.Since scolding tin 26 occurs in stress
When can play the role of padded coaming, therefore ensure that portion 6 will mitigate the stress of portion of terminal 3a periphery by the way that scolding tin wall thickness is arranged.
So according to the present embodiment, even if the material in the moulding resin for using linear expansion coefficient small as potting resin portion 25
In the case of, also the scolding tin 26 for engaging leading part 2 (portion of terminal 3a) with wiring substrate 20 can be inhibited to occur in temperature change
Cracking.
Further, ensure portion 6 due to that scolding tin wall thickness can be arranged in the case where not expanding the area of portion of terminal 3a, because
This can prevent the enlargement of semiconductor device 30.In addition, due to necessary when by the installation of lead frame 1 to wiring substrate 20
Aligning accuracy with do not changed in the past, therefore the rising of 30 cost of semiconductor device can be prevented.
(manufacturing method of semiconductor device)
It is illustrated next, putting up with using the manufacturing method of above-mentioned semiconductor device 30.
Firstly, preparing wiring substrate 20 and lead frame 1.Then, the various electronics of installation are installed in wiring substrate 20
Component (switch element 24 etc.).
Next, after the position between wiring substrate 20 and lead frame 1 is aligned, by the portion of terminal 3a of lead frame 1
Scolding tin is bonded on the conductive pattern 22 of wiring substrate 20.At this point, since scolding tin wall thickness ensures that extra weldering can be absorbed in portion 6
Tin, therefore the solder bridge being able to suppress between adjacent conductive pattern 22.
Next, 27 electricity of connecting line will be passed through between various electronic components and conductive pattern 22 and between electronic component
Connection.
Next, the mounting surface of wiring substrate 20 and inner lead 3 are packaged to be formed using potting resin
Potting resin portion 25.Finally, the frame section 5 of excision lead frame 1, to complete the production of semiconductor device 30.
According to the manufacturing method of above-mentioned semiconductor device 30, when by the installation of lead frame 1 to wiring substrate 20, wiring base
Aligning accuracy between plate 20 and lead frame 1 with do not changed in the past.Therefore, according to this or mode, lead frame 1 will be avoided
Aligning accuracy, lead frame 1 and wiring substrate 20 etc. harsh is become for the condition of each component tolerance, to can prevent
The only rising of 30 cost of semiconductor device.
Based on above-mentioned record, those skilled in the art may will recognize that addition effect of the invention and various deformations,
But form of the invention is not limited to above-mentioned each embodiment.It is also possible to want the composition in different embodiments
Element is suitably combined.It is not departing from and is being guided out in content specified in range from Patent request and its equipollent
In the range of idea of the invention thought and purport, it is able to carry out various additions, change and part and deletes.
Symbol description
1 lead frame
2,13 leading part
3 inner leads
3a portion of terminal
3b opposite face
The back side 3c
3d wire connections
3e bending part
4 outside leads
5 frame sections
6 scolding tin wall thickness ensure portion
10 metal sheets
11 temporary interna leads
12 thinner wall sections
20 wiring substrates
21 insulating substrates
22,23 conductive pattern
24 switch elements
25 resin-encapsulated portions
26 scolding tin
27 connecting lines
28 thermistors
29 shunt resistances
30 semiconductor devices
A die-casting process region
B cutting line
The region C1
C2 middle section
Claims (9)
1. a kind of lead frame characterized by comprising
Leading part, with inner lead and the outside lead being connected with the inner lead；And
Frame section supports the leading part,
Wherein, the inner lead is equipped with portion of terminal, and the portion of terminal has opposite with the conductive pattern of wiring substrate opposite
Face, and the back side with the opposite face opposite side,
The peripheral part of the portion of terminal, which is equipped with scolding tin wall thickness, ensures that portion, the scolding tin wall thickness portion of ensuring are formed, described opposite
The back side recess is faced toward, and thinner than the middle section of the opposite face, it is flat that the back side, which does not form recess portion,
Smooth,
The scolding tin wall thickness ensures that portion is configured to "U" word shape along the periphery of the portion of terminal.
2. lead frame according to claim 1, it is characterised in that:
Wherein, the scolding tin wall thickness portion of ensuring is arranged at the front end of the portion of terminal.
3. lead frame as claimed in any of claims 1 to 2, it is characterised in that:
Wherein, the inner lead has the wire connections for being electrically connected the portion of terminal with the outside lead, the weldering
Tin wall thickness ensures that portion is extended to from the portion of terminal towards the outside lead in the way of the wire connections.
4. lead frame as claimed in any of claims 1 to 2, it is characterised in that:
Wherein, the scolding tin wall thickness portion of ensuring is after keeping wall thickness thinning by the peripheral part progress die-casting process to the portion of terminal
It is formed.
5. a kind of manufacturing method of semiconductor device characterized by comprising
Prepare the process of wiring substrate, the conduction that the wiring substrate has insulating substrate and is arranged on the insulating substrate
Figure；
Prepare the process of lead frame described in any one of claim 1 to 2；
In the process of the mounting surface installation electronic component of the wiring substrate；
The portion of terminal scolding tin of the lead frame is bonded on the process on the conductive pattern of the wiring substrate；
The mounting surface and the inner lead to the electronic component, the wiring substrate are carried out using potting resin
The process of encapsulation；And
The process that the frame of the lead frame is cut off.
6. a kind of semiconductor device characterized by comprising
Wiring substrate with insulating substrate and the conductive pattern being arranged on the insulating substrate, and is pacified on mounting surface
Equipped with electronic component；
Leading part, with inner lead and the outside lead being connected with the inner lead；And
Potting resin portion seals the mounting surface and the inner lead of the electronic component, the wiring substrate
Dress,
Wherein, the inner lead is equipped with portion of terminal, and the portion of terminal has opposite with the conductive pattern of wiring substrate opposite
Face, and the back side with the opposite face opposite side, and be bonded on the conductive pattern by scolding tin,
The peripheral part of the portion of terminal, which is equipped with scolding tin wall thickness, ensures that portion, the scolding tin wall thickness portion of ensuring are formed, described opposite
The back side recess is faced toward, and thinner than the middle section of the opposite face, the middle section at the back side does not have shape
At recess portion, it is flat,
The scolding tin wall thickness ensures that portion is configured to "U" word shape along the periphery of the portion of terminal.
7. a kind of manufacturing method of lead frame, for manufacturing the lead frame for having leading part, the leading part has inside
Lead and the outside lead being connected with the inner lead, the inner lead are equipped with portion of terminal, and the portion of terminal has
The opposite face opposite with the conductive pattern of wiring substrate, characterized by comprising:
Die-casting process process, by the die-casting process compressed using upper and lower a pair of mold to metal sheet, in conduct
In the interarea of one side of the metal sheet of the opposite face, the periphery of the portion of terminal as the inner lead
On the part in portion, thinner wall section is formed, the thinner wall section is formed the opposite face and is recessed towards back side and than the phase
Thinner the shaped shape of the middle section on opposite；And
The formation process of inner lead, the bottom surface for making cutting line B pass through the thinner wall section by pressing to wear the metal sheet, from
And the inner lead for ensuring portion equipped with scolding tin wall thickness is formed in the peripheral part of the portion of terminal.
8. the manufacturing method of lead frame according to claim 7, it is characterised in that:
Wherein, before carrying out the die-casting process process, further comprise the metal sheet is carried out to press to wear processing, thus
The preparation for forming the temporary interna lead of shape bigger than the inner lead presses to wear process.
9. the manufacturing method of lead frame according to claim 7 or 8, it is characterised in that:
Wherein, in the die-casting process process, the thinner wall section of "U" word shape is formed along the periphery of the portion of terminal.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014240477 | 2014-11-27 | ||
| JP2014-240477 | 2014-11-27 | ||
| PCT/JP2015/078363 WO2016084483A1 (en) | 2014-11-27 | 2015-10-06 | Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107112308A CN107112308A (en) | 2017-08-29 |
| CN107112308B true CN107112308B (en) | 2019-06-14 |
Family
ID=56074061
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580005842.9A Active CN107112308B (en) | 2014-11-27 | 2015-10-06 | The manufacturing method of lead frame, semiconductor device, the manufacturing method of lead frame and semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9966327B2 (en) |
| EP (1) | EP3226292B1 (en) |
| JP (1) | JP6193510B2 (en) |
| CN (1) | CN107112308B (en) |
| WO (1) | WO2016084483A1 (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101821588B1 (en) * | 2016-04-22 | 2018-01-25 | 주식회사 코아비스 | Fuel pump module and method for improving radiant heat |
| DE102016112289B4 (en) * | 2016-07-05 | 2020-07-30 | Danfoss Silicon Power Gmbh | Lead frame and method of making the same |
| JP2018041956A (en) * | 2016-09-06 | 2018-03-15 | エイブリック株式会社 | Semiconductor device manufacturing method |
| WO2018150558A1 (en) * | 2017-02-20 | 2018-08-23 | 新電元工業株式会社 | Electronic device, connector, and method for producing electronic device |
| WO2018150556A1 (en) * | 2017-02-20 | 2018-08-23 | 新電元工業株式会社 | Electronic device, and connector |
| US10910292B2 (en) | 2017-02-20 | 2021-02-02 | Shindengen Electric Manufacturing Co., Ltd. | Electronic device and connection body |
| WO2019082343A1 (en) * | 2017-10-26 | 2019-05-02 | 新電元工業株式会社 | Semiconductor device |
| CN110892527B (en) * | 2017-10-26 | 2023-10-27 | 新电元工业株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN111316428B (en) * | 2017-10-26 | 2023-10-20 | 新电元工业株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP6752981B2 (en) * | 2017-10-26 | 2020-09-09 | 新電元工業株式会社 | Manufacturing method of semiconductor devices |
| JP6780635B2 (en) | 2017-12-22 | 2020-11-04 | 三菱電機株式会社 | Semiconductor module |
| JP7238277B2 (en) | 2018-06-14 | 2023-03-14 | 富士電機株式会社 | Semiconductor device, lead frame and method for manufacturing semiconductor device |
| CN111587486B (en) * | 2018-12-19 | 2023-06-16 | 新电元工业株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP7244630B2 (en) * | 2019-04-25 | 2023-03-22 | 京セラ株式会社 | Wiring substrates, packages for electronic components, and electronic devices |
| US11349021B2 (en) * | 2020-03-24 | 2022-05-31 | Littelfuse, Inc. | Thyristor assembly |
| JP7422646B2 (en) | 2020-11-27 | 2024-01-26 | 三菱電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
| US20220310409A1 (en) * | 2021-03-24 | 2022-09-29 | Littelfuse, Inc. | Method to connect power terminal to substrate within semiconductor package |
| JP2022181817A (en) * | 2021-05-27 | 2022-12-08 | 株式会社デンソー | Semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4846700A (en) * | 1987-04-06 | 1989-07-11 | Dennis Richard K | Lead frame for semi-conductor device |
| JPH029158A (en) * | 1988-06-27 | 1990-01-12 | T & K Internatl Kenkyusho:Kk | Resin sealing molding of semiconductor element and semiconductor lead frame therefor |
| JPH0311607A (en) * | 1989-06-08 | 1991-01-18 | Shinko Electric Ind Co Ltd | Fitting structure of lead of electronic device |
| CN101563777A (en) * | 2006-12-18 | 2009-10-21 | 矽马电子股份有限公司 | Lead frame, method for manufacturing the lead frame, and semiconductor device having the lead frame mounted thereon |
| JP2011249395A (en) * | 2010-05-24 | 2011-12-08 | Mitsubishi Electric Corp | Semiconductor device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5512728A (en) * | 1978-07-14 | 1980-01-29 | Hitachi Ltd | Regin sealing type power transistor |
| JPH07111370A (en) * | 1993-10-13 | 1995-04-25 | Fuji Electric Co Ltd | Semiconductor device |
| KR100857161B1 (en) * | 2001-01-31 | 2008-09-05 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and its manufacturing method |
| JP4860939B2 (en) * | 2005-04-08 | 2012-01-25 | ローム株式会社 | Semiconductor device |
| JP2007165714A (en) | 2005-12-15 | 2007-06-28 | Renesas Technology Corp | Semiconductor device |
| JP2012064855A (en) * | 2010-09-17 | 2012-03-29 | Toshiba Corp | Semiconductor device |
| JP5696780B2 (en) * | 2011-04-01 | 2015-04-08 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2013123016A (en) | 2011-12-12 | 2013-06-20 | Denso Corp | Semiconductor device |
-
2015
- 2015-10-06 WO PCT/JP2015/078363 patent/WO2016084483A1/en active Application Filing
- 2015-10-06 US US15/124,472 patent/US9966327B2/en active Active
- 2015-10-06 CN CN201580005842.9A patent/CN107112308B/en active Active
- 2015-10-06 EP EP15863679.5A patent/EP3226292B1/en active Active
- 2015-10-06 JP JP2016561442A patent/JP6193510B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4846700A (en) * | 1987-04-06 | 1989-07-11 | Dennis Richard K | Lead frame for semi-conductor device |
| JPH029158A (en) * | 1988-06-27 | 1990-01-12 | T & K Internatl Kenkyusho:Kk | Resin sealing molding of semiconductor element and semiconductor lead frame therefor |
| JPH0311607A (en) * | 1989-06-08 | 1991-01-18 | Shinko Electric Ind Co Ltd | Fitting structure of lead of electronic device |
| CN101563777A (en) * | 2006-12-18 | 2009-10-21 | 矽马电子股份有限公司 | Lead frame, method for manufacturing the lead frame, and semiconductor device having the lead frame mounted thereon |
| JP2011249395A (en) * | 2010-05-24 | 2011-12-08 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2016084483A1 (en) | 2017-04-27 |
| CN107112308A (en) | 2017-08-29 |
| US9966327B2 (en) | 2018-05-08 |
| EP3226292B1 (en) | 2019-05-29 |
| WO2016084483A1 (en) | 2016-06-02 |
| EP3226292A4 (en) | 2018-08-01 |
| JP6193510B2 (en) | 2017-09-06 |
| EP3226292A1 (en) | 2017-10-04 |
| US20170025331A1 (en) | 2017-01-26 |
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