CN107068741A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN107068741A
CN107068741A CN201710064351.2A CN201710064351A CN107068741A CN 107068741 A CN107068741 A CN 107068741A CN 201710064351 A CN201710064351 A CN 201710064351A CN 107068741 A CN107068741 A CN 107068741A
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electrode
source electrode
source
semiconductor device
grid
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CN107068741B (zh
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藤田光
藤田光一
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

得到一种能够防止高频电力增益的下降、能够小型化的半导体装置及其制造方法。源极电极(12)具有：第1源极电极(12a)；第2源极电极(12b)，其是第2阶层或者更高阶层的电极，形成于第1源极电极(12a)之上；以及第3源极电极(12c)，其是第3阶层或者更高阶层的电极，形成于第2源极电极(12b)之上，且形成于栅极引出电极(15)的上方。栅极引出电极(15)是第2阶层或者更高阶层的电极，形成于第1源极电极(12a)之上，栅极引出电极(15)的周围被第1、第2及第3源极电极(12a、12b、12c)包围。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法。
背景技术
为了提高在频率为3MHz至3GHz的高频带且以输出为几W至几百W的高输出进行动作的半导体装置、特别是横型场效应晶体管的特性，需要降低栅极电阻、栅极电容、源极电阻等的寄生成分。对此，提出了栅极引出电极及源极沟槽。另外，为了确保高散热性，迄今为止是将由高价的金属和陶瓷构成的中空封装用于横型场效应晶体管。并且，为了实现产品的小型化、低成本化而推进廉价的塑料模塑封装、倒装芯片封装的应用，但存在栅极电极或者漏极电极的寄生电容增大、高频特性下降这一问题。
作为降低栅极电极的寄生电容的方法，提出有下述方法，即，由与源极接地的屏蔽电极对栅极引出电极进行屏蔽，降低漏极电极和栅极电极的电容(例如参照专利文献1)。
为了降低应用模塑封装时的寄生电容，提出有下述方法，即，通过将接地的屏蔽金属与栅极电极、漏极电极及源极电极之间的空间设为中空，从而降低各电极间的电容(例如参照专利文献2)。作为降低源极电阻的方法，还提出有下述构造，即，将源极区域的高电阻的硅外延层设为源极沟槽，将源极电极直接与低电阻亚(sub)层电连接(例如参照专利文献3)。
专利文献1：日本特表2005－519474号公报
专利文献2：日本特开2004－6816号公报
专利文献3：美国专利第7420247号说明书
对于现有的半导体装置来说，在进一步推进小型化的情况下，栅极电极、漏极电极及源极电极的间隔变近，从而电极间的寄生电容增大，高增益化变得困难。因此，需要进一步降低电极间的寄生电容。另外，散热性由于小型化而下降，因此存在需要提高散热性等问题。
在专利文献1中，通过在第1阶层将栅极引出电极设置于源极电极间，从而使栅极电阻下降而改善高频动作。并且，通过在第2阶层利用与源极接地的屏蔽电极而相对于漏极电极进行屏蔽，从而降低栅极电极的电容，防止在应用塑料模塑封装时电容增大。但是，由于在第1阶层形成源极电极和栅极引出配线，因此半导体装置的源极区域面积增大，从而难以小型化。另外，由于在栅极电极和源极屏蔽电极之间存在作为电介体的氧化硅膜(SiO2)等，因此存在源极－栅极间的电容增大而使得高频动作变得困难等问题。
在专利文献2中，由于在栅极电极和漏极电极之间存在由电介体膜构成的玻璃涂膜，因此产生栅极－漏极间的寄生电容。因此，存在进一步的高频动作变得困难等问题。在专利文献3中，存在高台阶的源极沟槽开口部的填埋和源极区域的面积增大等问题。
发明内容
本发明就是为了解决上述课题而提出的，其目的在于得到一种能够防止高频电力增益的下降、能够小型化的半导体装置及其制造方法。
本发明所涉及的半导体装置具有大于或等于3个阶层的电极，该半导体装置的特征在于，具有：半导体衬底；外延层，其形成于所述半导体衬底之上；晶体管，其形成于所述外延层；源极电极，其形成于所述外延层之上，与所述晶体管的源极电连接；以及栅极引出电极，其形成于所述外延层之上，与所述晶体管的栅极电连接，所述源极电极具有：第1源极电极；第2源极电极，其是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上；以及第3源极电极，其是第3阶层或者更高阶层的电极，形成于所述第2源极电极之上，且形成于所述栅极引出电极的上方，所述栅极引出电极是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上，所述栅极引出电极的周围被所述第1、第2及第3源极电极包围。
发明的效果
在本发明中，由于栅极引出电极的周围被接地的第1、第2及第3源极电极包围，因此流过第1、第2及第3漏极电极的输出电力不会反馈至栅极引出电极，能够防止高频电力增益的下降。另外，由于利用第2阶层或者更高阶层的第2源极电极和第3阶层或者更高阶层的第3阶层的第3源极电极将第2阶层或者更高阶层的栅极引出电极的周围包围，因此能够缩小水平方向的尺寸而将装置小型化。并且，通过使用本发明，即使在应用了廉价的塑料模塑封装的情况下、使用了芯片尺寸封装的情况下，也能够防止高频电力增益的下降。
附图说明
图1是表示本发明的实施方式1所涉及的半导体装置的剖面图。
图2是表示对比例1所涉及的半导体装置的剖面图。
图3是表示对比例2所涉及的半导体装置的剖面图。
图4是表示本发明的实施方式2所涉及的半导体装置的剖面图。
图5是表示本发明的实施方式3所涉及的半导体装置的剖面图。
图6是表示对比例3所涉及的半导体装置的剖面图。
图7是表示本发明的实施方式4所涉及的半导体装置的剖面图。
图8是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的俯视图。
图9是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的剖面图。
图10是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的剖面图。
图11是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的剖面图。
图12是用于对本发明的实施方式5所涉及的半导体装置的制造方法进行说明的剖面图。
图13是用于对本发明的实施方式5所涉及的半导体装置的制造方法进行说明的剖面图。
图14是表示本发明的实施方式6所涉及的半导体装置的俯视图。
图15是表示本发明的实施方式6所涉及的半导体装置的俯视图。
图16是用于对本发明的实施方式6所涉及的半导体装置的制造方法进行说明的剖面图。
图17是用于对本发明的实施方式6所涉及的半导体装置的制造方法进行说明的剖面图。
标号的说明
1半导体衬底，2外延层，12源极电极，12a第1源极电极，12b第2源极电极，12c第3源极电极，13a第1漏极电极，13b第2漏极电极，13c第3漏极电极，14第2层间膜(绝缘膜、第1牺牲层)，15栅极引出电极，16第3层间膜(绝缘膜、第1牺牲层)，17表面保护膜，18、29中空构造，19源极沟槽，20狭缝孔，26阻挡层，27氧化硅膜(第2牺牲层)，28源极焊盘，29源极接触孔，30栅极焊盘，32漏极焊盘，33源极凸块电极，34栅极凸块电极，35漏极凸块电极。
具体实施方式
参照附图，对本发明的实施方式所涉及的半导体装置及其制造方法进行说明。对相同或者相对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1
图1是表示本发明的实施方式1所涉及的半导体装置的剖面图。该半导体装置是具有大于或等于3个阶层的电极的高频高输出用横型场效应晶体管(LDMOSFET)。
在P++型半导体衬底1之上形成有P－型外延层2。在P－型外延层2形成有P型沟道层3、N型漏极层4、N－型漏极层5、N+型漏极层6、N+型源极层7以及P++型源极沉降层8。这些扩散层是通过P型或者N型的离子注入和热扩散而形成的。
在P型沟道层3之上隔着栅极氧化膜9形成有栅极电极10。栅极电极10由多晶硅和金属硅化物(WSi、CoSi、NiSi等)构成。作为氧化硅膜的第1层间膜11是在栅极电极10之上通过CVD法等而形成的。以上述方式在外延层2形成有晶体管。
作为第1阶层的电极，由铝或者其化合物构成的第1源极电极12a及第1漏极电极13a形成于P－型外延层2之上。第1源极电极12a与N+型源极层7及P++型源极沉降层8电连接。P++型源极沉降层8将第1源极电极12a与P++型半导体衬底1电连接。P++型半导体衬底1接地，被作为源极电极使用。第1漏极电极13a与N+型漏极层6电连接。作为氧化硅膜的第2层间膜14是在第1源极电极12a及第1漏极电极13a之上通过CVD法等而形成的。
作为第2阶层的电极，形成有由铝或者其化合物构成的栅极引出电极15、第2源极电极12b及第2漏极电极13b。栅极引出电极15与栅极电极10电连接。第2源极电极12b形成于第1源极电极12a之上。第2漏极电极13b形成于第1漏极电极13a之上。作为氧化硅膜的第3层间膜16是在栅极引出电极15、第2源极电极12b及第2漏极电极13b之上通过CVD法等而形成的。
作为第3阶层的电极，形成有由铝或者其化合物构成的第3源极电极12c及第3漏极电极13c。第3源极电极12c形成于第2源极电极12b之上，且形成于栅极引出电极15的上方。第1、第2及第3源极电极12a、12b、12c是与晶体管的源极电连接的源极电极12。栅极引出电极15形成于第1源极电极12a之上，栅极引出电极15的周围被第1、第2及第3源极电极12a、12b、12c包围。在栅极引出电极15和源极电极12之间形成有第2及第3层间膜14、16。氮化硅膜等表面保护膜17通过CVD法等形成于包含源极电极12之上在内的装置整体。
下面，与对比例进行比较而对本实施方式的效果进行说明。图2是表示对比例1所涉及的半导体装置的剖面图。第1源极电极12a将栅极电极10及N－型漏极层5的上方覆盖。图3是表示对比例2所涉及的半导体装置的剖面图。与栅极电极10电连接的栅极引出电极15被作为第2阶层的电极而形成于第1源极电极12a之上。
在对比例2中，通过使用由与栅极电极10相比电阻率较小的材料构成、且截面积大的栅极引出电极15，从而栅极电阻下降，因此与对比例1相比高频特性提高。但是，由于栅极引出电极15与第1及第2漏极电极13a、13b之间未进行电磁屏蔽，因此漏极－栅极间的寄生电容增加。由于漏极－栅极间的寄生电容导致流过第1及第2漏极电极13a、13b的输出电力反馈至栅极引出电极15，因此高频电力增益下降。另外，在将作为电介体的塑料模塑材料用作封装的情况下，由于栅极引出电极15和第1及第2漏极电极13a、13b的上部由塑料模塑材料覆盖，因此漏极－栅极间的寄生电容进一步增加，高频电力增益进一步下降。
在本实施方式中，由于栅极引出电极15的周围被接地的第1、第2及第3源极电极12a、12b、12c包围，因此即使在应用了塑料模塑封装的情况下，流过第1、第2及第3漏极电极13a、13b、13c的输出电力也不会反馈至栅极引出电极15，能够防止高频电力增益的下降。
另外，在专利文献1中，在第1阶层形成源极电极和栅极引出电极，利用第2阶层的电极将栅极引出电极的周围包围而相对于漏极电极进行屏蔽，但由于源极区域的面积扩大，装置的小型化是困难的。与此相对，在本实施方式中，由于利用第2及第3阶层的第2及第3源极电极12b、12c将第2阶层的栅极引出电极15的周围包围，因此能够缩小水平方向的尺寸而将装置小型化。
实施方式2
图4是表示本发明的实施方式2所涉及的半导体装置的剖面图。栅极引出电极15和源极电极12之间是去除第2及第3层间膜14、16而得到了空间的中空构造18。其他结构与实施方式1相同。
在实施方式1中，由于在栅极引出电极15和源极电极12之间存在第2及第3层间膜14、16，因此有时栅极－源极间的寄生电容增加而引起高频特性的下降。本实施方式通过将栅极引出电极15和源极电极12之间设为中空构造18，从而栅极－源极间的寄生电容下降。因此，与实施方式1相比，能够将装置小型化，即使在应用了塑料模塑封装的情况下，也能够防止高频电力增益的下降。
实施方式3
图5是表示本发明的实施方式3所涉及的半导体装置的剖面图。源极沟槽19是在从P－型外延层2起至P++型半导体衬底1的中途为止通过干式蚀刻法等而形成的。P++型源极层20是在源极沟槽19的侧壁及底面通过硼等P型杂质注入而形成的。第1源极电极12a形成于源极沟槽19内，在源极沟槽19内与P++型半导体衬底1、N+型源极层7及P++型源极层20电连接。作为氧化硅膜的第2层间膜14是在第1源极电极12a及第1漏极电极13a之上通过CVD法等而形成的。栅极引出电极15是在形成第2层间膜14后通过CVD法或者溅射法等利用金属材料(W、Al等)对源极沟槽19进行填埋、然后通过照相制版和蚀刻工序而形成的。作为氧化硅膜的第3层间膜16是在形成栅极引出电极15后通过CVD法等而形成的。
作为第2阶层的电极的第2源极电极12b形成于第1源极电极12a之上，且形成于栅极引出电极15的上方。栅极引出电极15形成于第1源极电极12a之上，栅极引出电极15的周围被第1及第2源极电极12a、12b包围。
下面，与对比例3进行比较而对本实施方式的效果进行说明。图6是表示对比例3所涉及的半导体装置的剖面图。在对比例3中，在源极区域的P－型外延层2形成源极沟槽19，将第1源极电极12a与P++型半导体衬底1直接连接。由此，能够降低源极接地电阻及源极电感而高输出化。但是，由于在源极沟槽19产生高台阶，因而需要使用CVD膜等进行填埋。
在本实施方式中，通过源极沟槽19的应用，能够降低源极接地电阻及源极电感而高输出化。并且，由于通过使用栅极引出电极15，从而栅极电阻下降，因此高频特性提高。另外，由于栅极引出电极15的周围被接地的第1及第2源极电极12a、12b包围，因此即使在应用了塑料模塑封装的情况下，流过第1、第2及第3漏极电极13a、13b、13c的输出电力也不会反馈至栅极引出电极15，能够防止高频电力增益的下降。
实施方式4
图7是表示本发明的实施方式4所涉及的半导体装置的剖面图。栅极引出电极15和源极电极12之间是去除第2及第3层间膜14、16而得到了空间的中空构造18。其他结构与实施方式3相同。本实施方式与实施方式3相比能够将装置小型化，即使在应用了塑料模塑封装的情况下，也能够防止高频电力增益的下降。
下面，对本实施方式所涉及的半导体装置的制造方法进行说明。图8是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的俯视图。图9～11是用于对本发明的实施方式4所涉及的半导体装置的制造方法进行说明的剖面图。图9～11与沿图8的I－II的剖面相对应。
首先，在P++型半导体衬底1之上形成P－型外延层2。在P－型外延层2形成具有P型沟道层3等的晶体管。在外延层2之上形成与晶体管的栅极电连接的栅极引出电极15。形成将栅极引出电极15的周围覆盖的第1牺牲膜、即第2及第3层间膜14、16。以覆盖其周围的方式形成与晶体管的源极电连接的第1及第2源极电极12a、12b。
然后，如图8及图9所示，在源极沟槽19的上方，在源极电极的最上层的第2源极电极12b形成狭缝孔(slit hole)20。另外，栅极引出电极15通过栅极配线21、22而与两侧的栅极电极10电连接。在图8中以虚线示出晶体管的有源区域23。如图9所示，在晶体管的非有源区域形成有场(field)氧化膜24。
然后，如图10所示，形成仅狭缝孔20的周边开设了开口的光致抗蚀剂25。使用氢氟酸或者含有氢氟酸的混合酸经由狭缝孔20相对于栅极引出电极15及源极电极12而选择性地对第2及第3层间膜14、16进行蚀刻，在栅极引出电极15和源极电极12之间形成中空构造18。
然后，如图11所示，去除光致抗蚀剂25，在源极电极12之上形成玻璃涂膜等表面保护膜17。在这里，如果将狭缝孔20的短边的尺寸设定为小于或等于表面保护膜17的厚度的2倍，则能够利用表面保护膜17将狭缝孔20堵塞。但是，也可以形成将短边的尺寸设定为小于或等于表面保护膜17的厚度的2倍的第1狭缝孔、和将短边的尺寸设定为大于表面保护膜17的厚度的2倍的第2狭缝孔，利用表面保护膜17将第1狭缝孔堵塞，而不堵塞第2狭缝孔。如上所述，通过不将中空构造18完全堵塞，从而能够防止中空构造18由于中空构造18内的空气的热膨胀而破裂。
通过以上工序，制造出具有中空构造18的、本实施方式所涉及的半导体装置。此外，实施方式2的栅极引出电极15和源极电极12之间的中空构造18也是通过相同的方法而形成的。
在实施方式3中，由于在栅极引出电极15和源极电极12之间存在第2及第3层间膜14、16，因此有时栅极－源极间的寄生电容增加而引起高频特性的下降。本实施方式通过将栅极引出电极15和源极电极12之间设为中空构造18，从而栅极－源极间的寄生电容下降。因此，与实施方式3相比，能够将装置小型化，即使在应用了塑料模塑封装的情况下，也能够防止高频电力增益的下降。
实施方式5
图12及图13是用于对本发明的实施方式5所涉及的半导体装置的制造方法进行说明的剖面图。首先，进行与实施方式4相同的制造工序。
然后，如图12所示，在作为氧化硅膜的第3层间膜16之上通过CVD法等而形成阻挡层26。阻挡层26是氮化硅膜、或者不会被氢氟酸或者含有氢氟酸的混合酸蚀刻掉的其他绝缘膜。在阻挡层26之上通过CVD法等而形成将第2漏极电极13b的周围覆盖的氧化硅膜27。在氧化硅膜27之上形成源极焊盘28。源极焊盘28经由源极接触孔29与源极电极12电连接。源极焊盘28以将包含第2漏极电极13b在内的晶体管的有源部的上方覆盖的方式形成。在源极焊盘28之上形成表面保护膜17。
然后，如图13所示，相对于阻挡层26及第2漏极电极13b而选择性地对氧化硅膜27进行蚀刻，在第2漏极电极13b和源极焊盘28之间，形成与栅极引出电极15的周围的中空构造18进行了电磁屏蔽的单独的中空构造29。在源极焊盘28，在第2漏极电极13b的上方形成有未图示的狭缝孔。使用该狭缝孔，与实施方式4的中空构造18同样地形成本实施方式的中空构造29。
在本实施方式中，在实施方式4的结构及效果的基础上，通过使用源极焊盘28，从而能够在装置上表面获得晶体管的接地。另外，在晶体管动作过程中产生的热容易从装置上表面进行散热。因此，能够实现装置的小型化，由于接地电感降低而能够进一步高频化。另外，还能够在装置上表面形成源极、栅极、漏极端子，能够应用倒装芯片安装、芯片尺寸封装(CSP)。另外，通过在第2漏极电极13b和源极焊盘28之间形成中空构造29，从而漏极－源极间的寄生电容下降。因此，与实施方式4相比，能够将装置小型化，即使在应用了塑料模塑封装的情况下，也能够防止高频电力增益的下降。
实施方式6
图14及图15是表示本发明的实施方式6所涉及的半导体装置的俯视图。本实施方式是将实施方式5应用于能够进行倒装芯片安装的产品后的结构。
图14示出形成凸块电极之前的状态。栅极焊盘30通过栅极配线31而与栅极引出电极15电连接。漏极焊盘32与第2漏极电极13b电连接。
图15示出形成凸块电极之后的状态。源极凸块电极33、栅极凸块电极34及漏极凸块电极35分别形成于源极焊盘28、栅极焊盘30及漏极焊盘32之上。源极凸块电极33、栅极凸块电极34及漏极凸块电极35由铜、金、焊料等金属材料构成，是通过镀敷法等而形成的。
下面，对本实施方式所涉及的半导体装置的制造方法进行说明。图16及图17是用于对本发明的实施方式6所涉及的半导体装置的制造方法进行说明的剖面图。图16及图17与沿图15的I－II的剖面相对应。
首先，实施与实施方式5相同的制造工序。然后，如图16所示，在源极焊盘28及表面保护膜17之上的芯片整体通过涂敷法等而形成聚酰亚胺、塑料等树脂膜36。
然后，如图17所示，通过干式蚀刻法等对表面保护膜17及树脂膜36进行开口，形成接触孔37。通过镀敷法或者CVD法等，将铜、钨等金属材料填埋于接触孔37，形成插塞配线38。通过铜、金、焊料等，将源极凸块电极33形成于插塞配线38之上。源极凸块电极33形成于源极接触孔29的正上方。此外，虽未图示，但在同一工序中，将栅极凸块电极34及漏极凸块电极35分别形成于栅极焊盘30及漏极焊盘32之上。
在本实施方式中，在装置上表面，将源极凸块电极33、栅极凸块电极34及漏极凸块电极35分别形成于源极焊盘28、栅极焊盘30及漏极焊盘32之上。由此，栅极、源极、漏极的各电感成分减少，实现高频增益的增大。另外，晶体管芯片的外周线39的大小的芯片尺寸封装(CSP)产品的形态成为可能，与以往相比能够大幅度地实现产品的小型化。
如果在装置上表面形成作为电介体的树脂膜36，则由于栅极电极、漏极电极、源极电极间的寄生电容的增大，因而高频特性下降。因此，在专利文献2中提出有下述方案，即，通过对栅极电极、漏极电极、源极电极进行电磁屏蔽，将屏蔽金属和各电极之间的空间设为中空，从而降低各电极间的电容。在实施方式5、6中，在第2漏极电极13b和源极焊盘28之间形成与栅极引出电极15的周围的中空构造18进行了电磁屏蔽的单独的中空构造29。因此，与专利文献2相比，栅极－漏极间的寄生电容下降。因此，即使在晶体管上部形成作为电介体的树脂膜36，也能够降低栅极－漏极间、栅极－源极间、漏极－源极间的寄生电容，所以能够防止高频特性的下降。
由于源极凸块电极33形成于源极接触孔29的正上方，因此能够对在晶体管的有源区域产生的热进行释放，因而具有防止半导体装置的破坏、高寿命化的效果。此外，在本实施方式中使用了实施方式5的构造，但即使在实施方式2的构造的上表面形成凸块电极，也能够实现相同的效果。
此外，在实施方式1、2、5、6中对3个阶层的电极构造进行了说明，但也可以存在更多阶层。即，第2源极电极12b及栅极引出电极15不限于第2阶层的电极，也可以是更高阶层的电极，第3源极电极12c不限于第3阶层的电极，也可以是更高阶层的电极。另外，在实施方式3、4中对2个阶层的电极构造进行了说明，但也可以存在更多阶层。即，第2源极电极12b不限于第2阶层的电极，也可以是更高阶层的电极。无论在何种情况下，只要栅极引出电极15形成于最上层和最下层的电极间即可。
另外，在实施方式1～6中，对使用了硅衬底的N沟道型的高频高输出用横型场效应晶体管进行了说明，但还能够将本发明应用于P沟道型的高频高输出用横型场效应晶体管，实现等同的效果。另外，还能够将本发明应用于作为半导体衬底及外延层的半导体材料而使用了SiC、GaN、GaAs及其他化合物的横型场效应晶体管，实现等同的效果。

Claims (13)

1.一种半导体装置，其具有大于或等于3个阶层的电极，
该半导体装置的特征在于，具有：
半导体衬底；
外延层，其形成于所述半导体衬底之上；
晶体管，其形成于所述外延层；
源极电极，其形成于所述外延层之上，与所述晶体管的源极电连接；以及
栅极引出电极，其形成于所述外延层之上，与所述晶体管的栅极电连接，
所述源极电极具有：
第1源极电极；
第2源极电极，其是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上；以及
第3源极电极，其是第3阶层或者更高阶层的电极，形成于所述第2源极电极之上，且形成于所述栅极引出电极的上方，
所述栅极引出电极是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上，所述栅极引出电极的周围被所述第1、第2及第3源极电极包围。
2.一种半导体装置，其具有大于或等于2个阶层的电极，
该半导体装置的特征在于，具有：
半导体衬底；
外延层，其形成于所述半导体衬底之上，形成有源极沟槽；
晶体管，其形成于所述外延层；
源极电极，其形成于所述外延层之上，与所述晶体管的源极电连接；以及
栅极引出电极，其形成于所述外延层之上，与所述晶体管的栅极电连接，
所述源极电极具有：
第1源极电极，其形成于所述源极沟槽内；以及
第2源极电极，其是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上，且形成于所述栅极引出电极的上方，
所述栅极引出电极形成于所述第1源极电极之上，所述栅极引出电极的周围被所述第1及第2源极电极包围。
3.根据权利要求1或2所述的半导体装置，其特征在于，
还具有在所述栅极引出电极和所述源极电极之间形成的绝缘膜。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述栅极引出电极和所述源极电极之间是中空构造。
5.根据权利要求4所述的半导体装置，其特征在于，具有：
漏极电极，其形成于所述外延层之上，与所述晶体管的漏极电连接；以及
源极焊盘，其形成于所述漏极电极的上方，与所述源极电极电连接，
所述漏极电极和所述源极焊盘之间是与所述栅极引出电极的周围的中空构造进行了电磁屏蔽的单独的中空构造。
6.根据权利要求5所述的半导体装置，其特征在于，
所述源极焊盘形成为将所述晶体管的有源部的上方覆盖。
7.根据权利要求5或6所述的半导体装置，其特征在于，具有：
源极接触孔，其将所述源极电极和所述源极焊盘电连接；
栅极焊盘，其与所述栅极引出电极电连接；
漏极焊盘，其与所述漏极电极电连接；以及
在所述源极焊盘、所述栅极焊盘以及所述漏极焊盘之上分别形成的源极凸块电极、栅极凸块电极以及漏极凸块电极，
所述源极凸块电极形成于所述源极接触孔的正上方。
8.一种半导体装置的制造方法，其特征在于，具有下述工序，即：
在半导体衬底之上形成外延层；
在所述外延层形成晶体管；
在所述外延层之上形成与所述晶体管的栅极电连接的栅极引出电极；
形成将所述栅极引出电极的周围覆盖的第1牺牲层；
以将所述第1牺牲层的周围覆盖的方式，形成与所述晶体管的源极电连接的源极电极；
在所述源极电极的最上层形成狭缝孔；以及
经由所述狭缝孔，相对于所述栅极引出电极及所述源极电极而选择性地对所述第1牺牲层进行蚀刻，在所述栅极引出电极和所述源极电极之间形成中空构造。
9.根据权利要求8所述的半导体装置的制造方法，其特征在于，
形成所述源极电极的工序具有下述工序，即；
形成第1源极电极；
将第2源极电极形成于所述第1源极电极之上，该第2源极电极是第2阶层或者更高阶层的电极；以及
将第3源极电极形成于所述第2源极电极之上，且形成于所述栅极引出电极的上方，该第3源极电极是第3阶层或者更高阶层的电极，
所述栅极引出电极是第2阶层或者更高阶层的电极，形成于所述第1源极电极之上，所述栅极引出电极的周围被所述第1、第2及第3源极电极包围。
10.根据权利要求8所述的半导体装置的制造方法，其特征在于，
还具有在所述外延层形成源极沟槽的工序，
形成所述源极电极的工序具有下述工序，即：
在所述源极沟槽内形成第1源极电极；以及
将第2源极电极形成于所述第1源极电极之上，且形成于所述栅极引出电极的上方，该第2源极电极是第2阶层或者更高阶层的电极，
所述栅极引出电极形成于所述第1源极电极之上，所述栅极引出电极的周围被所述第1及第2源极电极包围。
11.根据权利要求8至10中任一项所述的半导体装置的制造方法，其特征在于，
还具有以将所述狭缝孔堵塞的方式在所述源极电极之上形成表面保护膜的工序，
将所述狭缝孔的短边的尺寸设定为小于或等于所述表面保护膜的厚度的2倍。
12.根据权利要求8至10中任一项所述的半导体装置的制造方法，其特征在于，还具有下述工序，即：
作为所述狭缝孔而形成第1及第2狭缝孔；以及
以堵塞所述第1狭缝孔、不堵塞所述第2狭缝孔的方式形成表面保护膜，
将所述第1狭缝孔的短边的尺寸设定为小于或等于所述表面保护膜的厚度的2倍，
将所述第2狭缝孔的短边的尺寸设定为大于所述表面保护膜的厚度的2倍。
13.根据权利要求8至12中任一项所述的半导体装置的制造方法，其特征在于，具有下述工序，即：
在所述外延层之上形成绝缘膜；
在所述绝缘膜之上形成阻挡层；
在所述外延层之上形成与所述晶体管的漏极电连接的漏极电极；
在所述阻挡层之上形成将所述漏极电极的周围覆盖的第2牺牲层；
在所述第2牺牲层之上形成与所述源极电极电连接的源极焊盘；以及
相对于所述阻挡层及所述漏极电极而选择性地对所述第2牺牲层进行蚀刻，在所述漏极电极和所述源极焊盘之间形成与所述栅极引出电极的周围的中空构造进行了电磁屏蔽的单独的中空构造。
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