CN107068570A - 一种薄膜晶体管、显示基板、显示装置及制作方法 - Google Patents

一种薄膜晶体管、显示基板、显示装置及制作方法 Download PDF

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CN107068570A
CN107068570A CN201710276986.9A CN201710276986A CN107068570A CN 107068570 A CN107068570 A CN 107068570A CN 201710276986 A CN201710276986 A CN 201710276986A CN 107068570 A CN107068570 A CN 107068570A
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groove structure
tft
film transistor
thin film
photoresist
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李贺飞
段献学
王铖铖
刘天真
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US15/820,732 priority patent/US20180308931A1/en
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Abstract

本发明提供一种薄膜晶体管、显示基板、显示装置及制作方法。薄膜晶体管的制作方法包括：形成具有第一凹槽结构和第二凹槽结构的有源层，第一凹槽结构和第二凹槽结构相互独立；在所第一凹槽结构和第二凹槽结构内分别沉积导电材料，以形成薄膜晶体管的源电极和漏电极。本发明的方案在有源层上形成第一凹槽结构和第二凹槽结构，之后将导电材料沉积在第一凹槽结构和第二凹槽结构内以直接形成源/漏电极。在沉积过程中，第一凹槽结构和第二凹槽结构可看成是容器，避免导电材料蔓延到有源层其他区域上，可防止导电材料的离子影响有源层的导电性能，使得薄膜晶体管在制作完成后具有较低的关态电流，从而能够更为稳定地驱动显示画面。

Description

一种薄膜晶体管、显示基板、显示装置及制作方法
技术领域
本发明涉及显示产品的制作领域，特别是指一种薄膜晶体管、显示基板、显示装置及制作方法。
背景技术
随着TFT-LCD(薄膜晶体管液晶显示器)的迅速发展，用户对器件的显示质量提出了更高的要求。其中显示画面均匀、高解析度、无窜扰等是高品质TFT-LCD的关键要求，TFT的关态电流(Ioff，也称漏电流)大小是影响上述品质的重要参数之一。关态电流偏高会影响薄膜晶体管的开关特性，从而导致TFT-LCD出现显示不均、发白、窜扰等显示类缺陷。
针对于传统的背沟道刻蚀型结构的TFT而言，在制造过程中，是先形成有源层硅岛结构，而后制作源漏电极，由于背沟道刻蚀型TFT在沟道刻蚀中会受到源漏电极金属离子的污染，会导致有源层的导电性质受到影响，最终导致关态电流偏高，影响TFT特性。
发明内容
本发明的目的是降低薄膜晶体管的关态电流，可以较大幅度的提高TFT-LCD的显示品质，提高产品的竞争力。
为实现上述目的，本发明的实施例提供一种薄膜晶体管的制作方法，包括：
形成具有第一凹槽结构以及第二凹槽结构的有源层，所述第一凹槽结构和所述第二凹槽结构相互独立；
在所述第一凹槽结构和所述第二凹槽结构内分别沉积导电材料，形成所述薄膜晶体管的源电极和漏电极。
其中，形成具有第一凹槽结构以及第二凹槽结构的有源层的步骤，包括：
沉积一层半导体材料层；
在所述半导体材料层上涂覆光刻胶；
通过掩膜板对所述光刻胶进行曝光，显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶未保留区域，所述光刻胶部分保留区对应所述第一凹槽结构和第二凹槽结构，所述光刻胶完全保留区域对应所述有源层的除所述第一凹槽结构和第二凹槽结构之外的区域，所述光刻胶未保留区域对应有源层的图形之外的区域；
对光刻胶未保留区域的半导体材料层进行刻蚀；
对光刻胶部分保留区域的光刻胶进行灰化，并对光刻胶部分保留区域的半导体材料层进行刻蚀，形成所述第一凹槽结构和所述第二凹槽结构；
对光刻胶完全保留区域的光刻胶进行灰化。
其中，所述光刻胶部分保留区还对应有第三凹槽结构；
形成具有第一凹槽结构以及第二凹槽结构的同时，还包括：
在所述第一凹槽结构和所述第二凹槽结构之间形成第三凹槽结构，所述第三凹槽结构与所述第一凹槽结构和所述第二凹槽结构相互独立。
其中，所述制作方法还包括：
在所述第一凹槽结构和所述第二凹槽结构内分别沉积导电材料包括：
采用喷墨打印技术在所述第一凹槽结构和所述第二凹槽结构内喷涂金属纳米溶液，从而形成至少部分位于所述第一凹槽结构内的源电极和至少部分位于所述第二凹槽结构内的漏电极。
其中，所述金属纳米溶液为Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W中的一者或几者的组合的金属纳米溶液。
另一方面，本发明还提供一种薄膜晶体管，该薄膜晶体管采用了上述制作方法制作得到，包括：
具有第一凹槽结构以及第二凹槽结构的有源层，所述第一凹槽结构和所述第二凹槽结构相互独立；
至少部分位于所述第一凹槽结构内的所述薄膜晶体管的源电极和至少部分位于所述第二凹槽结构内的所述薄膜晶体管的漏电极。
其中，所述有源层还包括：
位于所述第一凹槽结构和所述第二凹槽结构之间的第三凹槽结构；
所述第三凹槽结构与所述第一凹槽结构和所述第二凹槽结构相互独立。
此外，本发明的实施例还提供一种显示基板的制作方法，包括采用上述薄膜晶体管的制作方法以制作显示基板的薄膜晶体管。
此外，本发明的实施例还提供一种显示基板，包括上述薄膜晶体管。
此外，本发明的实施例还提供一种显示装置，包括上述显示基板。
本发明的上述方案具有如下有益效果：
本发明的方案在有源层上形成相隔的第一凹槽结构和第二凹槽结构，之后将导电材料沉积在第一凹槽结构和第二凹槽结构内，可直接形成源电极和漏电极。在沉积过程中，第一凹槽结构和第二凹槽结构可以看成是一个容器，可避免导电材料蔓延到有源层其他区域上，可防止导电材料的离子影响有源层其他区域的导电性能，使得薄膜晶体管在制作完成后具有较低的关态电流，从而在应用到显示产品上时，能够更为稳定地驱动显示画面，为用户带来了更高品质的画面体验效果。
附图说明
图1A-图1H为本发明的薄膜晶体管的示意图；
图2为本发明的显示基板的结构示意图。
附图标记：
1-衬底基板；2-栅电极；3-栅绝缘层；4-半导体材料层；4*-有缘层；5-光刻胶；61-源电极；62-漏电极；7-钝化层；8-像素电极；A-光刻胶全保留区域；B-光刻胶部分保留区域。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
针对现有薄膜晶体管制作方法会影响有源层导电性的问题，本发明提供一种解决方案。
一方面，本发明的实施例提供一种薄膜晶体管的制作方法，包括：
步骤一，形成具有第一凹槽结构以及第二凹槽结构的有源层，第一凹槽结构和第二凹槽结构相互独立；
步骤二，在第一凹槽结构和第二凹槽结构内分别沉积导电材料，形成薄膜晶体管的源电极和漏电极。
在本实施例的制作方法中，先形成具有第一凹槽结构和第二凹槽结构的有源层，其中第一凹槽结构对应源电极的设置位置，第二凹槽结构对应漏电极的设置位置，之后将导电材料沉积在第一凹槽结构和第二凹槽结构内，可直接形成源电极和漏电极，在沉积过程中，第一凹槽结构和第二凹槽结构可以有效阻止导电材料蔓延到有源层的其他区域上，从而避免了导电材料的离子影响有源层其他位置上的导电性能，进而有效降低了薄膜晶体管的关态电流。
此外，本实施例的制作方法不需要使用刻蚀工艺将导电材料层刻蚀出源电极和漏电极，因此相比于传统的制作工艺，提高了制作效率并降低了制作成本，这对于制造商来讲，具有很高的实用价值。
下面结合实现方式，对本实施例的薄膜晶体管的制作方法进行详细介绍，本实施例中的薄膜晶体管可以为底栅型，也可以为顶栅型，以及对应的可以实现本方案的其他类型。
示例性地，假设本实施例的薄膜晶体管为底栅型，则详细的制作方法包括如下步骤：
步骤11，参考图1A，在衬底基板1上依次形成栅电极2、栅绝缘层3和半导体材料层4；
步骤12，参考图1B，在半导体材料层4上涂覆光刻胶5(本文以正性光刻胶为例，需要说明的是负性光刻胶也同样适用，本文不再进行举例赘述)；
步骤13，参考图1C，通过掩膜板对光刻胶5进行曝光，显影后形成光刻胶完全保留区域A、光刻胶部分保留区域B和光刻胶未保留区域C(图1中未覆盖光刻胶的区域)；
其中，光刻胶部分保留区52对应第一凹槽结构、第二凹槽结构，光刻胶完全保留区域对应有源层的除第一凹槽结构和第二凹槽结构之外的区域，光刻胶未保留区域对应有源层的图形之外的区域；
步骤14，参考图1D，对光刻胶未保留区域的半导体材料层4进行刻蚀；
步骤15，参考图1E，对光刻胶部分保留区域B的光刻胶5进行灰化；
步骤16，参考图1F，并对光刻胶部分保留区域B的半导体材料层4进行刻蚀，形成第一凹槽结构41和第二凹槽结构42；
步骤17，参考图1G，对光刻胶完全保留区域的光刻胶进行灰化，以去除剩余光刻胶5；
步骤18，参考图1H，采用喷墨打印技术在第一凹槽结构41和第二凹槽结构42内喷涂金属纳米溶液，以形成源电极61和漏电极62。
由于目前尚未有采用喷墨打印技术制作源电极和漏电极的方案，因此在实际应用中，经过多次实践后发现，采用Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W中的一者或几者的组合的金属纳米溶液最为适合喷墨打印技术。
以上是本实现方式的薄膜晶体管的制作流程，可以看出，本实施例通过喷墨打印技术可以在第一凹槽结构和第二凹槽结构内直接精确沉积出源电极和漏电极，相比于传统工艺，在制作效率以及制作成本上均得到了明显的改善。此外，喷墨打印方式不需要将导电材料完全覆盖有源层，因此可以有效避免导电材料的离子影响有源层的导电性能，使得薄膜晶体管制成后，具有较低的关态电流，能够更稳定地驱动显示画面。
这里需要给予说明的是，上述步骤11至步骤18仅用于示例性介绍本实施例的制作方法的具体实施，在该基础之上，参考图1H，本实施例的制作方法还可以在有源层上形成有位于第一凹槽结构41和第二凹槽结构42之间的第三凹槽结构43，即图1D中，光刻胶部分保留区域B还对应的第三凹槽结构43，从而在步骤25中能够将半导体材料层4刻蚀出该第三凹槽结构43。
具体地，上述第三凹槽结构43是现有的非必要结构，在一些常规的制作工艺中，还需要在半导体材料层4沉积欧姆接触层，以让源电极61和漏电极62通过欧姆接触层与半导体材料层4接触，若设置欧姆接触层，则需要采用刻蚀工艺刻蚀掉源电极61和漏电极62之间的欧姆接触层的部分，从而在刻蚀完成后以形成第三凹槽结构43，该第三凹槽结构43位置所对应的有源层的导电性对薄膜晶体管的关态电流Ioff有着重要的影响，本实现方式可避免将导电材料沉积在第三凹槽结构43的设置区上。
此外，本实施例的制作方法同样适用于制作顶栅的薄膜晶体管，由于原理相同，本文不再进行举例赘述。
另一方面，本发明的另一实施例还提供一种薄膜晶体管，如图1H所示，包括：具有第一凹槽结构41以及第二凹槽结构42的有源层4*，第一凹槽结构41和第二凹槽结构42相互独立；
至少部分位于第一凹槽结构41内的薄膜晶体管的源电极61和至少部分位于第二凹槽结构42内的薄膜晶体管的漏电极62。
进一步地，本实施例的薄膜晶体管还包括位于第一凹槽结构41和第二凹槽结构42之间的第三凹槽结构43，该第三凹槽结构43与第一凹槽结构41和第二凹槽结构42相互独立。
通过上文描述可以知道，第三凹槽结构43的设置能够有效降低薄膜晶体管的关态电流，以达到更加稳定的画面驱动效果。
显然，本实施例的薄膜晶体管可以由本发明的薄膜晶体管的制作方法所制作出，因此该薄膜晶体管也能够实现该制作方法所能实现的技术效果。
同理，本发明的另一实施例还提供一种显示基板的制作方法，采用了本发明提供的薄膜晶体管的制作方法以制作显示基板的薄膜晶体管。
可以看出的是，基于本发明提供的薄膜晶体管的制作方法，本发明的显示基板简化了制作工艺并降低了制作成本，对于大批量的生产场景下，具有十分重要的改进意义。
此外，本发明的另一实施例还提供一种包括本发明提供的薄膜晶体管的显示基板，以及包括有该显示基板的显示装置。
显然，本实施例的显示基板以及显示装置基于本发明提供的薄膜晶体管，能够驱动出更高品质且更为稳定的显示画面，为用户提带来了更好的画面体验效果。
具体地，如图2所示，在实际应用中，本实施例的显示基板还包括覆盖薄膜晶体管的钝化层7和像素电极8。其中像素电极8通过贯穿钝化层7的过孔与薄膜晶体管的漏电极62连接，从而加载薄膜晶体管上的驱动信号。
此外，本实施例的显示装置可以泛指一切包括有该显示基板的产品，可以是显示面板，也可以是手机、PAD、电视、车载屏幕等。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种薄膜晶体管的制作方法，其特征在于，包括：
形成具有第一凹槽结构以及第二凹槽结构的有源层，所述第一凹槽结构和所述第二凹槽结构相互独立；
在所述第一凹槽结构和所述第二凹槽结构内分别沉积导电材料，形成所述薄膜晶体管的源电极和漏电极。
2.根据权利要求1所述的制作方法，其特征在于，
形成具有第一凹槽结构以及第二凹槽结构的有源层的步骤，包括：
沉积一层半导体材料层；
在所述半导体材料层上涂覆光刻胶；
通过掩膜板对所述光刻胶进行曝光，显影后形成光刻胶完全保留区域、光刻胶部分保留区域和光刻胶未保留区域，所述光刻胶部分保留区对应所述第一凹槽结构和第二凹槽结构的区域，所述光刻胶完全保留区域对应所述有源层的除所述第一凹槽结构和第二凹槽结构之外的区域，所述光刻胶未保留区域对应有源层的图形之外的区域；
对光刻胶未保留区域的半导体材料层进行刻蚀；
对光刻胶部分保留区域的光刻胶进行灰化，并对光刻胶部分保留区域的半导体材料层进行刻蚀，形成所述第一凹槽结构和所述第二凹槽结构；
对光刻胶完全保留区域的光刻胶进行灰化。
3.根据权利要求2所述的制作方法，其特征在于，
所述光刻胶部分保留区还对应有第三凹槽结构；
形成具有第一凹槽结构以及第二凹槽结构的同时，还包括：
在所述第一凹槽结构和所述第二凹槽结构之间形成第三凹槽结构，所述第三凹槽结构与所述第一凹槽结构和所述第二凹槽结构相互独立。
4.根据权利要求1所述的制作方法，其特征在于，还包括：
在所述第一凹槽结构和所述第二凹槽结构内分别沉积导电材料包括：
采用喷墨打印技术在所述第一凹槽结构和所述第二凹槽结构内喷涂金属纳米溶液，从而形成至少部分位于所述第一凹槽结构内的源电极和至少部分位于所述第二凹槽结构内的漏电极。
5.根据权利要求4所述的制作方法，其特征在于，
所述金属纳米溶液为Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W中的一者或几者的组合的金属纳米溶液。
6.一种薄膜晶体管，其特征在于，采用如权利要求1-5中任一项所述的制作方法制作得到，所述薄膜晶体管包括：
具有第一凹槽结构以及第二凹槽结构的有源层，所述第一凹槽结构和所述第二凹槽结构相互独立；
至少部分位于所述第一凹槽结构内的所述薄膜晶体管的源电极和至少部分位于所述第二凹槽结构内的所述薄膜晶体管的漏电极。
7.根据权利要求6所述的薄膜晶体管，其特征在于，所述有源层还包括：
位于所述第一凹槽结构和所述第二凹槽结构之间的第三凹槽结构；
所述第三凹槽结构与所述第一凹槽结构和所述第二凹槽结构相互独立。
8.一种显示基板的制作方法，其特征在于，采用如权利要求1-5中任一项所述的制作方法制作显示基板的薄膜晶体管。
9.一种显示基板，其特征在于，包括如权利要求6或7所述的薄膜晶体管。
10.一种显示装置，其特征在于，包括如权利要求9所述的显示基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107611025A (zh) * 2017-08-30 2018-01-19 华南理工大学 一种堆栈式薄膜晶体管电极的喷墨打印制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075658A (zh) * 2006-05-16 2007-11-21 三星电子株式会社 电极的形成方法和有机薄膜晶体管及显示装置
US20080296567A1 (en) * 2007-06-04 2008-12-04 Irving Lyn M Method of making thin film transistors comprising zinc-oxide-based semiconductor materials
CN104347726A (zh) * 2013-07-29 2015-02-11 三星显示有限公司 薄膜晶体管衬底及其制造方法以及显示装置
CN104779171A (zh) * 2015-05-05 2015-07-15 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
CN104979380A (zh) * 2015-05-26 2015-10-14 合肥鑫晟光电科技有限公司 一种薄膜晶体管及其制造方法
US20160049479A1 (en) * 2014-08-15 2016-02-18 Innolux Corporation Array substrate structure and contact structure
CN105428243A (zh) * 2016-01-11 2016-03-23 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、阵列基板和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101075658A (zh) * 2006-05-16 2007-11-21 三星电子株式会社 电极的形成方法和有机薄膜晶体管及显示装置
US20080296567A1 (en) * 2007-06-04 2008-12-04 Irving Lyn M Method of making thin film transistors comprising zinc-oxide-based semiconductor materials
CN104347726A (zh) * 2013-07-29 2015-02-11 三星显示有限公司 薄膜晶体管衬底及其制造方法以及显示装置
US20160049479A1 (en) * 2014-08-15 2016-02-18 Innolux Corporation Array substrate structure and contact structure
CN104779171A (zh) * 2015-05-05 2015-07-15 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
CN104979380A (zh) * 2015-05-26 2015-10-14 合肥鑫晟光电科技有限公司 一种薄膜晶体管及其制造方法
CN105428243A (zh) * 2016-01-11 2016-03-23 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、阵列基板和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107611025A (zh) * 2017-08-30 2018-01-19 华南理工大学 一种堆栈式薄膜晶体管电极的喷墨打印制备方法

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Application publication date: 20170818