CN1070515A - △-掺杂量子阱场效应晶体管的制作方法 - Google Patents

△-掺杂量子阱场效应晶体管的制作方法 Download PDF

Info

Publication number
CN1070515A
CN1070515A CN92105604A CN92105604A CN1070515A CN 1070515 A CN1070515 A CN 1070515A CN 92105604 A CN92105604 A CN 92105604A CN 92105604 A CN92105604 A CN 92105604A CN 1070515 A CN1070515 A CN 1070515A
Authority
CN
China
Prior art keywords
quantum well
effect transistor
layer
making
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN92105604A
Other languages
English (en)
Other versions
CN1025091C (zh
Inventor
丁润夏
郑东皓
张景植
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY
Pohang Comprehensive Iron And Steel Co Ltd
Posco Co Ltd
Original Assignee
INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY
Pohang Comprehensive Iron And Steel Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY, Pohang Comprehensive Iron And Steel Co Ltd filed Critical INSTITUTE OF INDUSTRIAL SCIENCE AND TECHNOLOGY
Publication of CN1070515A publication Critical patent/CN1070515A/zh
Application granted granted Critical
Publication of CN1025091C publication Critical patent/CN1025091C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365Planar doping, e.g. atomic-plane doping, delta-doping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/925Fluid growth doping control, e.g. delta doping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种制作△-掺杂量子阱场效应晶体管的工艺 方法,该晶体管包括:一基片、超晶格、缓冲层、量子 阱、覆盖层以及欧姆接触层。在欧姆层上形成漏极、 源极和栅极。各量子阱均按下述方式形成:用有机金 属化学汽相淀积工艺在低反层压力下形成第一 GaAs层;然后将Si杂质,如SiH4或Si2H6呈△-掺 杂掺入层内,再用相同的淀积工艺,在同样条件下形 成第二CaAs层,从而形成本发明的 GaAs/AlGaAs△-掺杂量子阱场效应晶体管。

Description

本发明涉及一种可广泛用于高速集成电路及高频电路的△-掺杂量子阱场效应晶体管的制作工艺方法,特别涉及一种采用有机金属化学汽相淀积工艺(MOCVD)制作的△-掺杂量子阱场效应晶体管的制作方法,从而可得到一种经济实用的GaAs/AlGaAs△-掺杂量子阱场效应晶体管。
通常,高速GaAs/AlGaAs△-掺杂量子阱场效应晶体管是采用分子束外延工艺(MBE)制作的。日本特许出愿号昭61-276269公开了一种此类GaAs/AlGaAs△-掺杂量子阱场效应晶体管,它是采用分子束外延工艺形成的。按该现有技术,△-掺杂量子阱是形成在非沟道区上的,而掺杂的GaAs是用在栅极上的。在场效应晶体管中采用这种结构,不仅降低了其击穿电压,而且也不可能得到其它的优良特性。
另一现有技术的实例是A.Ishibashi等人的GaAs场效应晶体管,公开在Electronics    Letters上,Vol.24,No.16,PP1034,Au-gust    1988。该GaAs场效应晶体管设置了一长度为0.15μm的栅,得到最大本征跨导为400ms/mm,其水平相对较高。
另外一个现有技术的实例是E.F.Schubert等人提出的场效应晶体管,公开在IEEE上,Vol.33,No5,PP625,May1986。根据他们的方案,分子束外延工艺是这样进行的,让GaAs的掺杂得以形成一种符合Dirac    δ函数的电子浓度分布,由此形成一种场效层晶体管。在此情况下,可以得到一种高二维电子层(2    DEG),高击穿电压和高非本征跨导,因而能获得一种高性能的器件。
再一个现有技术的实例是W.P.Hong等人的场效应晶体管,公开在IEEE上,Vol.37,No.8,PP1924-1926,August 1990分子束外延工艺被用来形成此种晶体管,当覆盖层为300
Figure 921056044_IMG3
,栅长为1.3μm时,可获得最大跨导为160ms/mm、栅电压摆幅为2.1V、最大漏极电流为420mA/mm。
然而,按上述常规技术,GaAs/AlGaAs量子阱场效应晶体管大多数是采用分子束外延工艺形成的,但是若要实施分子束外延工艺,则必须提供低于10-11乇的超高真空。结果就会使得制作工艺的生产率和经济实效下降。
本发明旨在克服常规技术中的上述不足之处。
所以,本发明的目的在于提供一种用于高速和高频电路的GaAs/AlGaAs△-掺杂量子阱场效应晶体管的制作工艺方法,按此法,采用一种可易于推广实际应用的有机金属化学汽相淀积工艺,由此,得到比常规GaAs/AlGaAs量子阱场效应晶体管性能更好的特性。
根据本发明,GaAs/AlGaAs晶体的生长是在650-750℃温度范围内进行的,所以△-掺杂分布不会变宽,而形成高质量晶体。
若结晶温度低于650℃,则不能制成高质量晶体;但若超过750℃,则掺杂分布将变宽,那就不适宜用于电子器件。
同时,量子阱的厚度最好处于100-200
Figure 921056044_IMG4
的范围内。若量子阱的厚度薄于100A,则会恶化对载流子的约束,而若厚于200
Figure 921056044_IMG5
,其量子效应就会被减弱。
AlGaAs覆盖层的厚度应为100-500
Figure 921056044_IMG6
,在此情况下,△-掺杂分布的弥散可被减至最小,从而获得最大的跨导。若覆盖层的厚度薄于100
Figure 921056044_IMG7
,会出现遂道效应,器件的特性将被劣化。同时,若厚于500
Figure 921056044_IMG8
,虽然栅与沟道间的距离可通过开槽工艺加以调整,却使源-漏电阻增大,且使掺杂分布变宽,因而降低了器件的特性。
在△-掺杂期间,用N型杂质,如SiH4或SiH6使GaAs层内硅的掺杂范围做成2-7×1012/cm3。在Si掺杂期间,掺杂剂电子浓度是靠控制SiH4或Si2H6的掺杂时间来调整的,而且,其界面应是突变的,其厚度必须是可调整的。
上述的本发明的目的及其它的优点,将通过参考附图,对本发明的优选实施例的详细描述而变得更加明显。
图1是表示依照本发明的场效应晶体管的垂直剖视图。
图2是表示依照本发明的场效应晶体管与漏-源电压的关系特性曲线图。
图3是表示依照本发明的场效应晶体管非本征跨导及漏极电流测量值与栅电压的关系曲线图。
图4是表示依照本发明制作有肖特基(Schottky)二极管的电压一电流特性曲线图。
图5是表明依照本发明的场效应晶体管量子阱的△-掺要分布图。
图6是表明依照本发明的场效应晶体管电流及功率增益与频率的关系图。
图1是依照本发明的用有机金属化学汽相淀积工艺制成的GaAs/Al0.3Ga0.7As△-掺杂量子阱场效应晶体管的垂直剖面图,其中将一个△-掺杂引入为使电子通过而设置的GaAs层中。
通过GaAs基片1浸入超声波浴中,依提到的次序用三氯乙烯、丙酮和甲醇各浸渍5分钟,即把它浸入上述三种化学物质中,各浸渍5分钟,清洗GaAs基片1以便去掉有机外来材料。然后将基片1放入由硫酸、过氧化氢和去离子水按4∶1∶1配比组成的溶液中浸渍30秒进行腐蚀。用于该工艺的设备是有机金属化学汽相淀积装置,流量速率保持在6标准升/秒(SLM),同时,在反应腔内的压力维持在76乇。
在基片1上形成一超晶格层(S/L)2,将该超晶格层2放入一反应腔,向反应腔内引入三甲基镓(TMG)和三甲基铝(TM )。流量分别为5.8sccm和4.8sccm;并向反应腔内,引入0.3SLM砷化三氢气(AsH3)。因而在此条件下生成层2,使得50
Figure 921056044_IMG10
的GaAs超晶格和50
Figure 921056044_IMG11
的Al0.3Ga0.7As超晶格通过20个循环来形成。在此工艺过程中,GaAs的生长速率是5
Figure 921056044_IMG12
/sec,而AlGaAs的生长速率是6.4
Figure 921056044_IMG13
/sec。
在超晶格层2上形成一层不掺杂AlGaAs缓冲层3,为形成该缓冲层3,使用的三甲基镓和三甲基铝的流量分别为5.8sccm和2.5sccm。在层3的形成过程中,AlGaAs的生长速率是5.3
Figure 921056044_IMG14
/sec,而该工艺过程持续31分钟,使AlGaAs层生长10000
Figure 921056044_IMG15
在该缓冲层3上形成第一GaAs量子阱4,该量子阱4经15秒的形成工艺过程,采用的三甲基镓的流量为5.8sccm,因而使其生长到75
Figure 921056044_IMG16
。然后,锁住三甲基镓的气门,代之以打开SiH4或Si2H6的气门,由此完成一次n型杂质引入第一GaAs量子阱4的△-掺杂。在实行该工艺过程之前和之后,分别进行排气15秒和7秒。
采用有机金属化学汽相淀积工艺进行在第一量子阱4内的Si△-掺杂,然后在与第一量子阱4相同的生长条件下,生长第二量子阱5。
在第二量子阱5上,用分别为5.8sccm和2.5scm的三甲基镓和三甲基铝生长56秒,形成AlGaAs覆盖层6。该层的生长速率与缓冲层3的生长速率相同,因而,所形成的覆盖层6的厚度为300
Figure 921056044_IMG17
。此后,为了增强欧姆接触,在覆盖层6上形成一层厚度为20
Figure 921056044_IMG18
的GaAs欧姆层7。在此形成工艺过程中,使用的三甲基镓的流量为5.8sccm,生长时间为4秒。
同时,在上述工艺过程中,将三甲基铝保持在20℃的恒温器中,而三甲基镓保持在-10℃的恒温器内,再用氢把胂稀释到10%,也用氢把甲硅烷稀释到100ppm,此时的生长温度为700-750℃。特别是,当反应层温度上升和下降时,若反应温度超过400℃,要让200sccm的AsH3流经样品1,以便防止样品1表面的分解。
下面表1表明了各种气体的流量,生长时间和生长温度。
Figure 921056044_IMG19
现在将介绍场效应晶体管的制作工艺过程。
器件的隔离是通过台面腐蚀及形成一层低杂质浓度的不掺杂的层实现的,台面腐蚀工艺则用UV接触对准器完成的,以便形成器件图形,并用硫酸、过氧化氢和去离子水(以1∶1∶25的配比混合)的混合溶液腐蚀12秒钟,大约腐蚀掉700
Figure 921056044_IMG20
,来实现腐蚀。
此后,源-漏的形成工艺过程是这样进行的:首先去掉光致抗蚀剂,然后用光掩模形成源-漏图形,再用热分解工艺依次淀积金属AuGe(1200
Figure 921056044_IMG21
),Ni(350
Figure 921056044_IMG22
)和Au(1500
Figure 921056044_IMG23
)。然后用剥离工艺,去掉所要求部位上的金属,再在430℃的温度下进行30秒钟热处理。
随后,再用一个栅极光掩膜和接触对准器进行栅形成工艺,形成μm的栅图形。而后通过将其浸入硫酸、过氧化氢和去离子水的溶液(以3∶1∶50的配比混合)中,形成栅凹槽。然后,用去离子水进行清洗,再用氮进行干燥。
然后,把所得部件浸入氢氧化铵和去离子水(混合比1∶15)溶液浸渍,再用氮干燥。随后放入金属化设备中,以便进行淀积厚度为0.3μm的Au。然后进行剥离工艺,从而完成本发明的最终的△-掺杂GaAs/Al0.3Ga0.7As量子阱场效应晶体管的形成。
按上述方式制得的场效应晶体管的电流对漏-源电压的特性曲线示于图2,其漏极电流和跨导对栅压的特性曲线示于图3。
由图可见,当场效应晶体管的栅长为2μm时,其跨导为190mS/mm,栅压的变化范围是2.5V,而漏电流的线性度是非常令人满意的,特别是,最大漏极电流为425mA/mm,与常规的GaAs场效应晶体管相比,改善了数十倍。
图4用图解表示依照本发明的具有GaAs/Al0.3Ga0.7As△-掺杂量子阱的肖特基(Schottky)二极管电压-电流特性曲线。
图5用图解来表示对本发明的△-掺杂GaAs/Al0.3Ga0.7As量子阱结构所测得的△-掺杂分布的电容-电压特性曲线图。在此,在Si△-掺杂层的最大值一半处的总宽度很窄,为43
Figure 921056044_IMG24
图6用图解表示依照本发明的2μm×10μm△-掺杂GaAs/Al0.3Ga0.7As量子阱场效应晶体管的电流增益及功率增益对频率的关系曲线。
根据如上所述的本发明,在低压反应腔内,用有机金属化学汽相淀积工艺,可以形成一种高速高性能的△-掺杂GaAs/AlGaAs量子阱场效应晶体管。所以,本发明的场效应晶体管与常规的只能在超高真空下制造的△-掺杂量子阱场效应晶体管相比,具有经济上的及其它优良特性的优点。所以,若将本发明的晶体管用于超大型计算机上,可以制成超高速大容量数据处理设备。

Claims (7)

1、一种制作△-掺杂量子阱场效应晶体管的工艺方法,包括:依次形成基片、超晶格、缓冲层、量子阱、覆盖层以及欧姆层等各工艺步骤,以及在所述覆盖屋上和在所述欧姆层上,用金属化和剥离,工艺形成源极、漏极以及栅极等各工艺步骤,
所说的量子阱的形成步骤进一步包括:
将三甲基镓和胂引入一反层腔内的步骤;
通过使用有机化学汽相淀积工艺形成一个第一GaAs理量子阱的步骤;
将Si杂质掺入所述第一量子阱的步骤;以及
将三甲基镓和胂引入所说的反应腔内,在与形成所述第一量子阱时相同的条件下,形成一个第二量子阱的步骤。
2、如权利要求1所请求保护制作△-掺杂量子阱场效应晶体管的工艺方法,其中所述有机金属化学汽相淀积工艺是在650-750℃温度范围内进行的。
3、一种如权利要求1所请求保护的制作△-掺杂量子阱场效应晶体管的工艺方法,其中所述第一和第二量子阱的组合厚度在100-200
Figure 921056044_IMG2
范围内。
4、一种如权利要求1所请求保护的制作△-掺杂量子阱场效应晶体管的工艺方法,其中向所述第一和第二量子阱做Si△-掺杂的杂质是SiH4
5、一种如权利要求1所请求保护的制作△-掺杂量子阱场效应晶体管的工艺方法,其中向所述第一和第二量子阱做Si△-掺杂的杂质是Si2H6
6、一种如权利要求1所请求保护的制作△-掺杂量子阱场效应晶体管的工艺方法,其中△-掺杂范围是2-5×1012/cm2
7、一种如权利要求1所请求保护的制作△-掺杂量子阱场效应晶体管的工艺方法,其中在实现△-掺杂之前和之后,都在76乇压力下,分别进行15秒和7秒的排气。
CN92105604A 1991-09-12 1992-07-11 Δ-掺杂量子阱场效应晶体管的制作方法 Expired - Fee Related CN1025091C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR15938/91 1991-09-12
KR1019910015938A KR940006711B1 (ko) 1991-09-12 1991-09-12 델타도핑 양자 우물전계 효과 트랜지스터의 제조방법

Publications (2)

Publication Number Publication Date
CN1070515A true CN1070515A (zh) 1993-03-31
CN1025091C CN1025091C (zh) 1994-06-15

Family

ID=19319879

Family Applications (1)

Application Number Title Priority Date Filing Date
CN92105604A Expired - Fee Related CN1025091C (zh) 1991-09-12 1992-07-11 Δ-掺杂量子阱场效应晶体管的制作方法

Country Status (5)

Country Link
US (1) US5284782A (zh)
EP (1) EP0531621A3 (zh)
JP (1) JPH0794758A (zh)
KR (1) KR940006711B1 (zh)
CN (1) CN1025091C (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1742343B (zh) * 2003-01-29 2011-10-19 波尔伊克两合公司 有机存储单元及其驱动电路
CN102308388A (zh) * 2009-03-16 2012-01-04 英特尔公司 用于改善量子阱器件中的并行传导的设备和方法

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610085A (en) * 1993-11-29 1997-03-11 Texas Instruments Incorporated Method of making a vertical FET using epitaxial overgrowth
KR0144821B1 (ko) * 1994-05-16 1998-07-01 양승택 저전원전압으로 작동가능한 갈륨비소 반도체 전력소자의 제조 방법
CN1254026C (zh) * 2000-11-21 2006-04-26 松下电器产业株式会社 通信系统用仪器
US7112830B2 (en) * 2002-11-25 2006-09-26 Apa Enterprises, Inc. Super lattice modification of overlying transistor
JP4601263B2 (ja) * 2003-04-25 2010-12-22 三菱電機株式会社 電界効果トランジスタ
JP4469139B2 (ja) * 2003-04-28 2010-05-26 シャープ株式会社 化合物半導体fet
US7601980B2 (en) * 2006-12-29 2009-10-13 Intel Corporation Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures
CN101997029B (zh) * 2009-08-26 2012-07-25 中国科学院半导体研究所 高迁移率量子点场效应晶体管及其制作方法
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728322A (en) * 1980-07-28 1982-02-16 Fujitsu Ltd Formation of semiconductor single crystal layer
JPS58219731A (ja) * 1982-06-15 1983-12-21 Toshiba Corp 化合物半導体の気相成長方法
JPS6187318A (ja) * 1984-10-05 1986-05-02 Toshiba Corp ガリウム・アルミニウム・砒素層へのド−ピング方法
US4882609A (en) * 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
JPS61174775A (ja) * 1985-01-30 1986-08-06 Fujitsu Ltd 半導体装置
JPS61276269A (ja) * 1985-05-30 1986-12-06 Fujitsu Ltd ヘテロ接合型電界効果トランジスタ
JPS6242569A (ja) * 1985-08-20 1987-02-24 Fujitsu Ltd 電界効果型トランジスタ
JPS62136882A (ja) * 1985-12-11 1987-06-19 Fujitsu Ltd 高速電界効果半導体装置
FR2610150B1 (fr) * 1987-01-23 1989-05-12 Trailigaz Dispositif d'alimentation electrique pour un ozoneur
JPH01171279A (ja) * 1987-12-25 1989-07-06 Mitsubishi Monsanto Chem Co 半導体装置
US5041393A (en) * 1988-12-28 1991-08-20 At&T Bell Laboratories Fabrication of GaAs integrated circuits
US4994408A (en) * 1989-02-06 1991-02-19 Motorola Inc. Epitaxial film growth using low pressure MOCVD
JPH02230746A (ja) * 1989-03-03 1990-09-13 Hitachi Ltd 半導体装置
US5021360A (en) * 1989-09-25 1991-06-04 Gte Laboratories Incorporated Method of farbicating highly lattice mismatched quantum well structures
JPH03288448A (ja) * 1990-04-05 1991-12-18 Nec Corp 電界効果トランジスタ
JPH04112548A (ja) * 1990-08-31 1992-04-14 Sanyo Electric Co Ltd 速度変調トランジスタ
JP2919581B2 (ja) * 1990-08-31 1999-07-12 三洋電機株式会社 速度変調トランジスタ

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1742343B (zh) * 2003-01-29 2011-10-19 波尔伊克两合公司 有机存储单元及其驱动电路
CN102308388A (zh) * 2009-03-16 2012-01-04 英特尔公司 用于改善量子阱器件中的并行传导的设备和方法
US8525151B2 (en) 2009-03-16 2013-09-03 Intel Corporation Apparatus and methods for improving parallel conduction in a quantum well device
US9048266B2 (en) 2009-03-16 2015-06-02 Intel Corporation Apparatus and methods for improving parallel conduction in a quantum well device

Also Published As

Publication number Publication date
EP0531621A2 (en) 1993-03-17
JPH0794758A (ja) 1995-04-07
KR930006983A (ko) 1993-04-22
US5284782A (en) 1994-02-08
EP0531621A3 (en) 1995-08-30
KR940006711B1 (ko) 1994-07-25
CN1025091C (zh) 1994-06-15

Similar Documents

Publication Publication Date Title
CN1025091C (zh) Δ-掺杂量子阱场效应晶体管的制作方法
Pande et al. Channel mobility enhancement in InP metal‐insulator‐semiconductor field‐effect transistors
US20030235934A1 (en) Layers of group III-nitride semiconductor made by processes with multi-step epitaxial growths
CN109786510B (zh) 一种四元探测器的制备方法以及由此得到的铟镓砷铋四元探测器
CA1244560A (en) Method of annealing a compound semiconductor substrate
Jeong et al. Sulfide treated GaAs MISFET's with gate insulator of photo-CVD grown P/sub 3/N/sub 5/film
Kapila et al. Passivation of GaAs surfaces and AlGaAs/GaAs heterojunction bipolar transistors using sulfide solutions and SiN x overlayer
CA1201365A (en) Method of growing oxide layer on indium gallium arsenide
US20170365672A1 (en) Composite gate dielectric layer applied to group iii-v substrate and method for manufacturing the same
CN102544103B (zh) 一种InP反型n沟道场效应管及其制备方法
US11626483B2 (en) Low-leakage regrown GaN p-n junctions for GaN power devices
Jeong et al. DC and AC characteristics of AL/sub 0.25/Ga/sub 0.75/As/GaAs quantum-well delta-doped channel FET grown by LP-MOCVD
WO2022031937A1 (en) ENHANCEMENT-MODE GaN HFET
Jeong et al. Effects of sulfide passivation on the performance of gaas misfets with photo-cvd grown p3n5 gate insulators
Breitschädel et al. Minimization of leakage current of recessed gate AlGaN/GaN HEMTs by optimizing the dry-etching process
Kim et al. Pd/Ge/Ti/Au ohmic contact to AlGaAs/InGaAs pseudomorphic high electron mobility transistor with an undoped cap layer
Salimian et al. Equal rate and anisotropic reactive ion etching of GaAs/AlGaAs heterostructures in SiCl4 plasma
Imai et al. Application of reactive‐ion‐beam etching to recessed‐gate GaAs metal–semiconductor field‐effect transistors
Dobkin et al. Monolayer surface doping of GaAs from a plated zinc source
CN1140930C (zh) AIxGa1-xN/GaN异质结的铁电体/半导体存贮器的制法
JP3089732B2 (ja) 化合物半導体のエピタキシャル成長方法
CN113540208B (zh) 基于原位生长MIS结构的垂直GaN肖特基二极管及其制备方法
JP2780501B2 (ja) 絶縁膜付き半導体ウェハ及びその製造方法
CN117423740A (zh) 一种基于导电型SiC衬底的GaN垂直器件及其生长方法
Jordan et al. The growth, characterization and electronic device applications of GaAs/Si

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C15 Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993)
OR01 Other related matters
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee