CN107026132A - 多输出封装件结构、天线系统及半导体封装方法 - Google Patents

多输出封装件结构、天线系统及半导体封装方法 Download PDF

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Publication number
CN107026132A
CN107026132A CN201611202573.8A CN201611202573A CN107026132A CN 107026132 A CN107026132 A CN 107026132A CN 201611202573 A CN201611202573 A CN 201611202573A CN 107026132 A CN107026132 A CN 107026132A
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China
Prior art keywords
antenna
tube core
spiral winding
rdl
auxiliary body
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CN201611202573.8A
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Inventor
陈韦廷
汤子君
曾明鸿
林胤藏
陈颉彦
王垂堂
郭鸿毅
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107026132A publication Critical patent/CN107026132A/zh
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Abstract

本发明的实施例公开了一种多输出封装件结构。多输出封装件结构包括天线主体；再分布层(RDL)；以及RDL中的天线辅助体。还公开了一种天线系统。天线系统包括：天线主体，布置为提供第一共振；以及天线辅助体，布置为通过寄生耦合至天线主体提供第二共振。还公开了一种相关联的半导体封装方法。

Description

多输出封装件结构、天线系统及半导体封装方法
技术领域
本发明的实施例涉及半导体领域，更具体地涉及多输出封装件结构、天线系统及半导体封装方法。
背景技术
能够在一个以上频带中操作的移动电话的天线的设计(例如，双模式)受到市场要求持续减小电话的整个尺寸的约束。用于具有极轻重量的智能电话的天线将需要尤其地紧凑，同时仍然能够提供令人满意的性能。
发明内容
本发明的实施例提供了一种多输出封装件结构，包括：天线主体；再分布层(RDL)；以及天线辅助体，在所述再分布层中。
本发明的实施例还提供了一种天线系统，包括：天线主体，布置为提供第一共振；以及天线辅助体，布置为通过寄生耦合至所述天线主体提供第二共振。
本发明的实施例还提供了一种半导体封装方法，包括：提供载体；在所述载体上附着天线主体以提供第一共振；在所述载体上设置天线辅助体，以通过寄生耦合至所述天线主体提供第二共振；其中，所述第一共振不同于所述第二共振。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1至图7是根据本发明的一些示例性实施例的示出包括多模式天线的多输出结构的制造中的中间阶段的示意图和截面图；
图8是根据本发明的第二实施例的示出多模式天线系统的顶视图；
图9A是根据本发明的第三实施例的示出多模式天线系统的顶视图；
图9B是沿图9A的线9-9截取的截面图；
图10A是根据本发明的第四实施例的示出多模式天线系统的顶视图；
图10B是沿图10A的线10-10截取的截面图；
图11A是根据本发明的第五实施例的示出多模式天线系统的顶视图；以及
图11B是沿图11A的线11-11截取的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
尽管提出本发明宽泛范围的数值范围和参数设定是近似值，在特定实例中的数值设定被尽可能精确地报告。然而，任何数值固有地包含某些必然误差，该误差由各自的测试测量结果中发现的标准偏差产生。同样，正如此处使用的术语“约”一般指在给定值或范围的10％、5％、1％或0.5％内。或者，术语“约”意思是在本领域普通的技术人员可以考虑到的可接受的平均标准误差内。除了在操作/工作实例中，或者除非明确指出，否则应该理解，通过术语“大约”修改所有示例中的所有的数值范围、数量、值和百分比(诸如用于本文所公开的材料的数量、持续时间、温度、操作条件、比率大小等)。因此，除非有相反规定，本发明和所附权利要求所记载的数值参数设定是可以根据要求改变的近似值。至少，每个数值参数应该至少被解释为根据被报告的有效数字的数目，并应用普通的四舍五入技术。此处范围可以表示为从一个端点到另一个端点或在两个端点之间。此处公开的所有范围包括端点，除非另有说明。
公开了能够在一个以上的频带中操作的多模式天线。在一个示例性实施例中，多模式天线嵌入在具有包括的至少一个天线主体的多输出封装件结构中且还提供了其形成方法。示出了形成多输出封装件的中间阶段。讨论实施例的变化。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图7是根据本发明的一些示例性实施例的示出包括多模式天线的多输出结构的制造中的中间阶段的示意图。图1是示出了载体20和载体20上的粘合层22的截面图。载体20可为玻璃载体、陶瓷载体等。粘合层22可以是由诸如粘合膜的粘合剂形成的。
图2A是示出了载体20上方的螺旋线圈23的放置的三维立体图。螺旋线圈23是用作天线主体的具有4匝的16mm平坦的螺旋线圈电感器且从顶视图角度看时具有多边形的基本轮廓。在该实施例中，从顶视图角度，螺旋线圈23描绘了16mm*16mm的尺寸的四边形。在一些实施例中，从顶视图角度，螺旋线圈23可以布置为四方形、正多边形、圆形或椭圆形。在一些实施例中，螺旋线圈23可具有圆角。如图2A所示，螺旋线圈23具有多边形、圆形或椭圆形的横截面，且横截面具有高度H和宽度W。在该实施例中，高度H约为150um。在一些实施例中，高度H可在约100um至约200um的范围内。请注意，这不旨在使本发明限制于此处所示的几何实例。螺旋线圈23包括线圈最外匝处的第一端23a和线圈最内匝处的第二端23b。
螺旋线圈23是可在别处制造的组件且随后被放置在载体20上。在一些实施例中，螺旋线圈23可以是由铜(Cu)组成的且通过诸如低成本穿孔、湿蚀刻或激光切割的操作制造。与通过在图案化的衬底上的电镀方法制备的现有的螺旋线圈相比，由所述操作制作的螺旋线圈23具有增加的厚度(即，H)且因此具有更大的深宽比(即，H和W的比率，又称高宽比)。在固定的宽度下，更大的深度为螺旋线圈23提供更大的截面面积，因此减少电阻值。在一些实施例中，深宽比可以超过2。在一些实施例中，深宽比可以超过2.5。图2B是示出了沿图2A的线2-2截取的载体20上方的螺旋线圈23的放置的截面图。
在一些实施例中，可以利用拾取放置机器以将平坦的螺旋线圈23逐一地安装至晶圆上。拾取放置机器可以包括其上具有多个孔的真空喷嘴以提供真空吸力，从而当将平坦的螺旋线圈23从托盘移动至晶圆上的具体位置时牢固地固定平坦的螺旋线圈23。在一些其它实施例中，与前述的拾取放置机器相反，可以利用振动部件对准装置以将平坦的螺旋线圈23的组一次性地安装至晶圆上。振动部件对准装置可以包括由振动发生器固定支撑的线圈对准托板，其中，该线圈对准托板具有用于在振动发生器的振动期间平坦的螺旋线圈23的组的对准的多个凹槽。然后，晶圆被翻转且附接至线圈对准托板，从而使得平坦的螺旋线圈23的组通过按压和加热操作从托板转移至晶圆。
图3A是示出了载体20上方的管芯24和25的放置的三维立体图。管芯24和管芯25放置在载体20上方的螺旋线圈23的旁边。在一些实施例中，管芯24和管芯25附接至粘合至载体20的粘合层22。管芯24可以是包括其中的逻辑晶体管的逻辑器件且和天线主体协同工作。例如，管芯24是包括充电相关功能的集成电路(IC)，并且管芯25是蓝牙IC。在一些实施例中，诸如电阻器、电容器和电感器的集成无源器件(IPD)还可包括在管芯24和25中。在一些实施例中，从顶视图角度，螺旋线圈23描绘了16mm*16mm的尺寸的四边形，并且从顶视图角度，管芯24和25中的每个都包括3mm*3mm的尺寸。
形成电连接件26和27以分别地作为管芯24和25的顶部，并且电连接件26和27电耦合至管芯24和25中的器件。在一些实施例中，电连接件26和27包括可以在器件管芯24和25放置在载体20上方之前预形成的金属支柱(诸如铜支柱)。金属支柱26和27可以不具有焊料且可以包括垂直的侧壁。在一些实施例中，介电层形成在管芯24和管芯25的顶面处，金属支柱26和27在介电层中至少具有下部或全部。介电层的顶面还可以与金属支柱26和27的顶端基本上齐平。介电层可以由聚酰亚胺、聚苯并恶唑(PBO)、氧化物层、氮化物层或它们的多层组成。当不形成介电层时，金属支柱26和27从管芯24和25的顶面之上突出。在该实施例中，在图3A和随后附图中不描述介电层。
管芯24和25附接至附着于载体20的粘合层22。控制管芯24、25的厚度和金属支柱26和27的高度，从而使得管芯24和25的金属支柱26和27的顶端与螺旋线圈23的高度H基本上齐平。此外，由于管芯24、25和螺旋线圈23放置在粘合层22上，所以管芯24、25和螺旋线圈23的背面彼此齐平。
图3B示出了图3A的结构的顶视图。在一些实施例中，管芯24、25和螺旋线圈23的放置在晶圆级处，并且因此，在载体20上方放置有多个管芯24、25和螺旋线圈23。图3B示出了载体20具有圆形顶视图形状。在可选实施例中，载体20还可以具有矩形顶视图形状，且管芯24和25可以布局为阵列。在图3B中，环绕每组管芯24、25和螺旋线圈23的矩形(未标记)限定在随后操作中形成的对应的封装件的边界。
参考图4，在管芯24、25和螺旋线圈23上分配且模制模制材料40。管芯24、25和螺旋线圈23的相对位移可参考之前讨论的图3A。模制材料40填充管芯24、25和螺旋线圈23之间的间隙，并且可以与粘合层22接触。此外，如果在管芯24和25的顶面上不形成介电层，那么模制材料40可以填充在金属支柱26和27之间的间隙内。在一些实施例中，模制材料40由聚合物组成。例如，模制材料40可包括模塑料、模制底部填充物、环氧树脂、或树脂。模制材料40的顶面高于金属支柱26、27和螺旋线圈23的顶端。模制材料40的底面与管芯24、25和螺旋线圈23的背面基本上齐平。在被分配之后，固化模制材料40。
接下来，实施可以是研磨操作或化学机械抛光(CMP)操作的平坦化操作以减薄模制材料40。可以完成平坦化操作直到暴露金属支柱26、27和螺旋线圈23的顶端。图5中示出了生成的结构。金属支柱26、27的顶端和螺旋线圈23的顶端的相对位移可参考之前讨论的图3A。螺旋线圈23与管芯24和25中的金属支柱26和27的顶端彼此齐平，且与模制材料的顶面40A齐平。在不形成介电层的一些实施例中，模制材料40环绕金属支柱26和27中的每个且与金属支柱26和27中的每个接触。在形成介电层的可选实施例中，金属支柱26和27的顶端彼此齐平且与介电层的表面和模制材料40的顶面40A基本上齐平。
接下来，参考图6A和图6B，图6B是沿图6A的线6-6截取的截面图。在模制材料40上方形成再分布层(RDL)45。RDL 45包括介电层44以及位于其中的多个导电图案41a、41b、41c、41d、42a、42b、43a和43，其中，由于实际上切割线仅穿过导电图案41b、42b、和43，所以图6B中仅示出了导电图案41b、42b、和43。可以具有一个、两个、三个或更多的介电层44，每个介电层44都包括在相同平面处多个连接导电图案。导电图案41a、41b、41c、和41d是将上部相邻再分布层中的导电图案42a和42b与螺旋线圈23和管芯24互连的通孔。这样，螺旋线圈23的第一端23a和第二端23b与管芯24连接。L形导电图案43具有约7um的高度且可用作天线辅助体，以及沿着螺旋线圈23的一侧定位，从而使得L形导电图案43的较长段平行于螺旋线圈23的右侧。导电图案43通过通孔43a连接至管芯25。在一些实施例中，导电图案43和螺旋线圈23的线圈最外匝之间的水平距离确定为阻抗匹配和电容耦合设计的结果。从顶视图角度，在螺旋线圈23描绘了16mm*16mm的尺寸且管芯25包括3mm*3mm的尺寸的方案下，水平距离在从约100μm至约150μm的范围内。
底部再分布层和对应的介电层44中的通孔41a、41b、41c、41d和43a具有约4.5um的高度且具有与金属支柱26、27、螺旋线圈23的顶端以及模制材料40的顶面40A接触的底面。在一些实施例中，RDL 45通过形成和图案化介电层44，且在图案化的介电层44中的开口中形成导电图案41a、41b、41c、41d、42a、42b、43a和43来形成。在可选实施例中，RDL45通过沉积金属层，图案化金属层，以及用介电层44填充导电图案41a、41b、41c、41d、42a、42b、43a和43之间的间隙形成。在又一可选的实施例中，RDL 45可以使用镶嵌工艺形成。RDL 45可以由铜、镍、钯、铝、钨等组成。介电层44可以包括诸如可以被图案化而不需使用额外的光刻胶的聚酰亚胺、PBO等的感光材料。介电层44还可以由无机材料或诸如氧化物和/或氮化物的材料形成。
在该实施例中，充电IC 24可配置为检测在相关近场区域内定位的无线充电器且配置为通过近场共振以6.78MHz穿过天线主体23发送无线功率。此外，天线辅助体43通过寄生耦合至天线主体23提供2.45GHz共振。术语寄生耦合是指当元件邻近且当元件通过其它元件分隔开时第一元件和第二元件之间的寄生耦合，其中，能量从第一元件寄生耦合至串联的任何数量的元件且然后寄生耦合至第二元件。以这样的方式，充电IC 24和蓝牙IC 25可以通过共用的天线主体23和天线辅助体43同时操作，并且天线主体23和天线辅助体43的总面积和成本小于专用于充电IC 24和蓝牙IC 25的两个单独的天线。这样，可以减小半导体器件的总面积。
图7示出根据一些示例性实施例的电连接件46的形成。连接件46的形成可以包括将焊球放置在导电图案47的暴露部分上以及回流焊球。在可选的实施例中，连接件46的形成包括实施镀敷操作以在连接图案47的暴露部分上方形成铜或焊料区域。连接件46还可以包括金属支柱或者金属支柱和焊帽，其也可以通过镀敷来形成。载体20与封装件48分离且可以去除粘合层22。包括管芯24、25、螺旋线圈23、模制材料40、上面的RDL 45和连接件46的组合结构称为多输出封装件48。多输出封装件48占据晶圆的包括多个多输出封装件的部分，且沿着多个多输出封装件内的划线管芯锯切晶圆。
上述的示例性实施例提供了一种包括集成在其中的管芯和螺旋线圈的多输出封装件。与通过电镀制备的现有的螺旋线圈相比，本文讨论的集成在多输出封装件中的螺旋线圈拥有更高的深宽比，从而当提供相同的性能时，本发明的螺旋线圈的形状因数更小。此外，与现有的螺旋线圈相比，本发明的螺旋线圈具有高纯度铜和更低的剩余应力。
在一些实施例中，例如，如图8所示，更多的无线通信系统应用可进一步被纳入充电和蓝牙系统中。图8是根据本发明的第二实施例示出的多模式天线系统的顶视图。长期演进(LTE)IC 84和无线保真(WiFi)IC 80进一步并入多输出封装件48中。利用相应的LTE天线辅助体86和相应的WiFi天线辅助体82以寄生耦合至天线主体23。以这样的方式，通过共用天线主体23和三个天线辅助体43、82和86来实现四模式天线系统。与使用四个单独的天线相比，公开的四模式天线系统具有减少的面积、成本和天线之间的干扰。
请注意，在一些实施例中，螺旋线圈23，即天线主体，还可通过RDL中的图案化和沉积操作形成。此外，多模式天线的概念还可应用于不同于晶圆级封装件工艺的场合。例如，本发明的概念可通过铜迹线应用于印刷电路板(PCB)上的天线。在另一实例中，本发明的概念可通过金属线应用于半导体管芯中的天线。在一些实施例中，可以根据各个设计要求改变天线主体的图案。在下面段落中描述一些可选的设计。
图9A是根据本发明的第三实施例的示出多模式天线系统的顶视图。图9A中示出的多模式天线系统是包括用作通过用于LTE相关应用的导电图案93耦合至LTE IC 94的天线主体的单极天线(monopole antenna)90三模式天线系统。如图9A所示，三模式天线系统还包括耦合至用于WiFi相关应用的WiFi IC 92的天线辅助体91，其中，天线辅助体91寄生耦合至天线90的侧部。如图9A所示，另一天线辅助体95耦合至用于相关应用的蓝牙IC 96，其中，天线辅助体95寄生耦合至单极天线90的另一侧。
图9B是沿图9A的线9-9截取的截面图。请注意，为了简洁，图9B仅示出了天线体所在的RDL 99。如可以图9B看见，天线主体90，是由在RDL 99的介电层98中形成的导电图案组成的。在RDL 99的同一介电层98中形成天线辅助体91和95。如上所述，可在RDL 99中通过图案化和沉积操作形成天线主体90以及辅助体91和95。然而，这并不是对本发明的限制。
图10A是根据本发明的第四实施例的示出多模式天线系统的顶视图。图10A中示出的多模式天线系统是包括用作通过用于LTE相关应用的导电图案103耦合至LTE IC 104的天线主体的锯齿形天线100的三模式天线系统。如图10A所示，三模式天线系统还包括耦合至用于WiFi相关应用的WiFi IC 102的天线辅助体101，其中，天线辅助体101寄生耦合至锯齿形天线100的侧部。如图10A所示，另一天线辅助体105耦合至用于相关应用的蓝牙IC106，其中，天线辅助体105寄生耦合至锯齿形天线100的另一侧。
图10B是沿图10A的线10-10截取的截面图。请注意，为了简洁，图10B仅示出了天线体所在的RDL 109。如可从图10B看见，螺旋管形天线100是由RDL 109的介电层107和108中形成的导电线100a和100b组成的，其中，通孔100c也形成在介电层107和108中以使导电线100a和100b互连并且因此形成锯齿形天线100。在RDL 109的介电层108中形成天线辅助体101和105。如上所述，可在RDL 109中通过图案化和沉积操作形成天线主体100和辅助体101和105。然而，这并不是对本发明的限制。
图11A是根据本发明的第五实施例的示出多模式天线系统的顶视图。图11A中示出的多模式天线系统是包括用作通过用于LTE相关应用的导电图案113耦合至LTE IC 114的天线主体的螺旋管形天线110的三模式天线系统。如图11A所示，三模式天线系统还包括耦合至用于WiFi相关应用的WiFi IC 112的天线辅助体111，其中，天线辅助体111寄生耦合至螺旋管形天线110的侧部。如图11A所示，另一天线辅助体115耦合至用于相关应用的蓝牙IC116，其中，天线辅助体115寄生耦合至螺旋管形天线110的内部。
图11B是沿图11A的线11-11截取的截面图。请注意，为了简洁，图11B仅示出了天线体所在的RDL 120。如可从图11B看见，锯齿形天线110是由在RDL 120的介电层117和119中形成的导电线110a和110b组成的。在RDL 120的介电层109中形成天线辅助体111。天线辅助体115形成在RDL 120的介电层108中以穿过锯齿形天线110的中心并且由导电线110a和110b围绕。通孔110c形成在介电层117和118中以互连导电线110a和110b并且因此形成锯齿形天线110。如上所述，可在RDL 120中通过图案化和沉积操作形成天线主体110和辅助体111和115。然而，这并不是对本发明的限制。
公开的多模式天线工艺拥有紧凑和简单的结构且可在具有不同频率的各种应用中实现。与为不同的模式分别使用单独的天线的系统相比，本发明具有减小的面积、成本和天线之间的干扰。此外，通过各个实施例示出的多模式天线很容易被集成在晶圆级封装工艺中。
本发明的一些实施例提供了一种多输出封装件结构，包括天线主体；再分布层(RDL)；以及RDL中的天线辅助体。
在本发明的一些实施例中，天线主体提供处于第一频率的共振。
在本发明的一些实施例中，天线辅助体通过寄生耦合至天线主体提供处于第二频率的共振。
在本发明的一些实施例中，第一频率高于第二频率或低于第二频率。
在本发明的一些实施例中，天线主体位于RDL中。
在本发明的一些实施例中，天线主体位于与RDL相邻的层中，并且层中的间隙由模制材料填充。
在本发明的一些实施例中，天线主体是螺旋线圈。
在本发明的一些实施例中，天线辅助体包括与天线主体的侧部平行的导电线。
在本发明的一些实施例中，还包括连接至RDL的第一管芯，从而使得第一管芯通过RDL连接至天线主体。
在本发明的一些实施例中，第一管芯包括与充电应用相关的功能。
在本发明的一些实施例中，还包括连接至RDL的第二管芯，从而使得第二管芯通过RDL连接至天线辅助体。
在本发明的一些实施例中，第二管芯包括与无线通信系统相关的功能。
本发明的一些实施例提供了一种天线系统，包括：天线主体，布置为提供第一共振；以及天线辅助体，布置为通过寄生耦合至天线主体提供第二共振；其中天线主体的尺寸大于天线辅助体的尺寸。
在本发明的一些实施例中，天线主体是螺旋线圈。
在本发明的一些实施例中，天线主体是单极天线。
在本发明的一些实施例中，天线主体是螺旋管形天线。
在本发明的一些实施例中，天线辅助体至少部分地平行于天线主体。
在本发明的一些实施例中，天线辅助体与天线主体至少部分地重叠。
本发明的一些实施例提供了一种半导体封装方法，包括：提供载体；在载体上附着天线主体以提供第一共振；在载体上方的再分布层(RDL)中设置天线辅助体以通过寄生耦合至天线主体提供第二共振；其中，第一共振不同于第二共振。
在本发明的一些实施例中，该方法还包括：在载体上附着管芯；以及将天线主体通过RDL与管芯连接。
本发明的实施例提供了一种多输出封装件结构，包括：天线主体；再分布层(RDL)；以及天线辅助体，在所述再分布层中。
根据本发明的一个实施例，其中，所述天线主体提供处于第一频率的共振。
根据本发明的一个实施例，其中，所述天线辅助体通过寄生耦合至所述天线主体提供处于第二频率的共振。
根据本发明的一个实施例，其中，所述第一频率高于所述第二频率。
根据本发明的一个实施例，其中，所述天线主体位于所述再分布层中。
根据本发明的一个实施例，其中，所述天线主体位于与所述再分布层相邻的层中，并且所述层中的间隙由模制材料填充。
根据本发明的一个实施例，其中，所述天线主体是螺旋线圈。
根据本发明的一个实施例，其中，所述天线辅助体包括平行于所述天线主体的侧部的导电线。
根据本发明的一个实施例，多输出封装件结构还包括连接至所述再分布层的第一管芯，从而使得所述第一管芯通过所述再分布层连接至所述天线主体。
根据本发明的一个实施例，其中，所述第一管芯包括与充电应用相关的功能。
根据本发明的一个实施例，多输出封装件结构还包括连接至所述再分布层的第二管芯，从而使得所述第二管芯通过所述再分布层连接至所述天线辅助体。
根据本发明的一个实施例，其中，所述第二管芯包括与无线通信系统相关的功能。
本发明的实施例还提供了一种天线系统，包括：天线主体，布置为提供第一共振；以及天线辅助体，布置为通过寄生耦合至所述天线主体提供第二共振；其中，所述天线主体的尺寸大于所述天线辅助体的尺寸。
根据本发明的一个实施例，其中，所述天线主体是螺旋线圈。
根据本发明的一个实施例，其中，所述天线主体是平面回折倒F天线(MIFA)。
根据本发明的一个实施例，其中，所述天线主体是锯齿形天线。
根据本发明的一个实施例，其中，所述天线辅助体至少部分地平行于所述天线主体。
根据本发明的一个实施例，其中，所述天线辅助体与所述天线主体至少部分地重叠。
本发明的实施例还提供了一种半导体封装方法，包括：提供载体；在所述载体上附着天线主体以提供第一共振；在所述载体上方的再分布层(RDL)中设置天线辅助体，以通过寄生耦合至所述天线主体提供第二共振；其中，所述第一共振不同于所述第二共振。
根据本发明的一个实施例，半导体封装方法还包括：在所述载体上附着管芯；以及通过所述再分布层将所述天线主体与所述管芯连接。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的实施例。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (1)

1.一种多输出封装件结构，包括：
天线主体；
再分布层(RDL)；以及
天线辅助体，在所述多输出封装件结构中。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269732B2 (en) * 2016-07-20 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info package with integrated antennas or inductors
US10332841B2 (en) 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN107742778A (zh) * 2017-10-25 2018-02-27 中芯长电半导体（江阴）有限公司 扇出型天线封装结构及其制备方法
USD917434S1 (en) * 2018-04-25 2021-04-27 Dentsply Sirona Inc. Dental tool with transponder
CN111403356B (zh) * 2020-04-02 2024-08-02 杭州晶通科技有限公司 一种模块化天线的扇出型封装结构的制备工艺

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101137797B1 (ko) * 2003-12-15 2012-04-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 집적회로장치의 제조방법, 비접촉형 박막집적회로장치 및 그 제조 방법, 비접촉형 박막 집적회로장치를 가지는 아이디 태그 및 동전
CN1910600B (zh) * 2004-01-23 2011-12-14 株式会社半导体能源研究所 Id标记、id卡和id标签
CN101142715B (zh) * 2005-03-15 2012-08-22 株式会社半导体能源研究所 半导体器件以及具有该半导体器件的电子器件
WO2009142756A2 (en) * 2008-05-22 2009-11-26 California Institute Of Technology On-chip highly-efficient antennas using strong resonant coupling
US8451618B2 (en) * 2010-10-28 2013-05-28 Infineon Technologies Ag Integrated antennas in wafer level package
US9711465B2 (en) * 2012-05-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
US8890319B2 (en) * 2012-09-12 2014-11-18 Infineon Technologies Ag Chip to package interface
US8779564B1 (en) * 2013-03-14 2014-07-15 Intel IP Corporation Semiconductor device with capacitive coupling structure
US9910145B2 (en) * 2013-12-19 2018-03-06 Infineon Technologies Ag Wireless communication system, a radar system and a method for determining a position information of an object
KR102219857B1 (ko) * 2014-03-18 2021-02-24 삼성전자주식회사 전자 장치 및 그 동작 방법

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