US20170018348A1 - Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices - Google Patents
Coupling inductors in an ic device using interconnecting elements with solder caps and resulting devices Download PDFInfo
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- US20170018348A1 US20170018348A1 US14/798,604 US201514798604A US2017018348A1 US 20170018348 A1 US20170018348 A1 US 20170018348A1 US 201514798604 A US201514798604 A US 201514798604A US 2017018348 A1 US2017018348 A1 US 2017018348A1
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 40
- 230000008878 coupling Effects 0.000 title abstract description 4
- 238000010168 coupling process Methods 0.000 title abstract description 4
- 238000005859 coupling reaction Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 44
- 239000002184 metal Substances 0.000 description 38
- 229910052751 metal Inorganic materials 0.000 description 38
- 239000010949 copper Substances 0.000 description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H01F17/00—Fixed inductances of the signal type
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- H01F17/0013—Printed inductances with stacked layers
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- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
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- H01F27/292—Surface mounted devices
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Abstract
Description
- The present disclosure relates generally to designing and fabricating integrated circuit (IC) devices. The present disclosure is particularly applicable to integrating coupled inductors in an IC device.
- Generally, an IC device may include a variety of components such as transistors, capacitors, inductors, voltage regulators, resistors, or the like, which may provide various functionalities in operation of an IC device. With industry demand for more efficient, smaller sized, and multifunctioning IC devices, manufacturing of such devices requires advanced IC design and manufacturing processes. Two coupled inductors have been used for ripple cancelation in integrated voltage regulators (IVRs). With a special timing scheme, the two phases perform complete current ripple cancellation across all duty cycles in the output. Moreover, the ripple current through each inductor is substantially reduced by a factor of (1+k) which decreases the inductor loss and improves the power supply efficiency. This converter topology enables the use of ultra-small inductors (2 nH) in a high efficiency converter and an ultra-small capacitor (2 nF) in an ultra-compact size. Components, such as an inductor without a core, may be challenging to implement in an IC device, wherein a thicker (e.g., 2 μm) metal layer may be required for forming the inductor coil/spiral. Coupled inductors may be implemented in a single metal layer (e.g., side-by-side) or in multiple adjacent (e.g., stacked) metal layers; however, in either case, the implementation would require a layout area in one or more layers, which may already include congested and compacted layouts of other components.
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FIG. 1A schematically illustrates an example of coupled inductors implemented on a same layer in an IC device.Substrate layer 101 includes a coupled inductor coils/spirals coils - Similar issues are associated with another example of coupled inductors as illustrated in
FIG. 1B , whereinductor coils different layers - Therefore, there is a need for a methodology enabling formation of coupled inductors in an IC device with a reduced area without metal and silicon thickness issues and resulting devices.
- An aspect of the present disclosure is a method of using interconnecting elements (e.g., copper pillars) with solder caps on substrates to implement coupled inductors in an IC device.
- Another aspect of the present disclosure is an IC device including interconnecting elements with solder caps on substrates to implement coupled inductors.
- Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
- According to the present disclosure some technical effects may be achieved in part by a method including forming a top inductor structure, in a top inductor area on a lower surface of a top substrate, the top inductor structure having first and second top terminals at its opposite ends; forming a bottom inductor structure, in a bottom inductor area on an upper surface of a bottom substrate, the bottom inductor structure having first and second bottom terminals at its opposite ends; forming top interconnecting elements on the lower surface of the top substrate around the top inductor area; forming bottom interconnecting elements on the upper surface of the bottom substrate around the bottom inductor area; forming solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and connecting the top and bottom interconnecting elements to each other. In some aspects, forming each of the top and bottom inductor structures includes forming a coil of conductive material, the coil having first and second terminals at its opposite ends.
- Another aspect includes forming the top interconnecting elements concurrently with the top inductor structure and the bottom interconnecting elements concurrently with the bottom inductor structure; forming a mask over each of the top and bottom inductor structures; forming the solder bumps; and removing the mask prior to connecting the top and bottom interconnecting elements.
- One aspect includes forming the top interconnecting elements, the bottom interconnecting elements, and solder bumps and forming a mask over the solder bumps prior to forming the top and bottom inductor structures; and removing the mask subsequent to forming the top and bottom inductor structures.
- An additional aspect includes forming a top barrier structure, in the top inductor area at the lower surface, spaced from and surrounding a perimeter of the top inductor structure; forming a bottom barrier structure, in the bottom inductor area at the upper surface, spaced from and surrounding a perimeter of the bottom inductor structure; depositing a layer of non-conductive bonding material, with a same thickness as the solder bumps, on lower and upper surfaces, respectively, of the top and bottom barrier structures; and connecting the top and bottom barrier structures. In one aspect, the top and bottom inductor structures are separated from each other by an air gap.
- In another aspect, the top inductor structures, the top inductor areas, and top barrier structures are substantially a same geometrical shape as and are vertically aligned with the bottom inductor structures, bottom inductor areas, and bottom barrier structures, respectively. Some aspects include injecting an under-fill material around the top and bottom barrier structures subsequent to connecting the top and bottom barrier structures. In one aspect, the top and bottom inductor structures are at a same height as the top and bottom interconnecting elements.
- According to the present disclosure, some technical effects may be achieved in part by a semiconductor device including: a top substrate having a lower surface; a bottom substrate having an upper surface; a top inductor structure, in a top inductor area at the lower surface, the top inductor structure having first and second top terminals at its opposite ends; a bottom inductor structure, in a bottom inductor area at the upper surface, the bottom inductor structure having first and second bottom terminals at its opposite ends; top interconnecting elements on the lower surface surrounding the top inductor area; bottom interconnecting elements on the upper surface surrounding the bottom inductor area; solder bumps on lower and upper surfaces, respectively, of the top and bottom interconnecting elements; and the top and bottom interconnecting elements connected to each other. In some aspects of the semiconductor device, each of the top and bottom inductor structures includes a coil of conductive material, the coil having first and second terminals at its opposite ends.
- In another aspect, the semiconductor device includes a top barrier structure, in the top inductor area at the lower surface, spaced from and surrounding a perimeter of the top inductor structure; a bottom barrier structure, in the bottom inductor area at the upper surface, spaced from and surrounding a perimeter of the bottom inductor structure; a layer of non-conductive bonding material, with a same thickness as the solder bumps, on lower and upper surfaces, respectively, of the top and bottom barrier structures; and the top and bottom barrier structures connected to each other. In an additional aspect of the semiconductor device, the top and bottom inductor structures are separated from each other by an air gap.
- In one aspect of the semiconductor device, the top inductor structures, the top inductor areas, and top barrier structures are substantially a same geometrical shape as and are vertically aligned with the bottom inductor structures, bottom inductor areas, and bottom barrier structures, respectively. In some aspects, the semiconductor device includes an under-fill material around the top and bottom barrier structures. In another aspect, the top and bottom inductor structures are at a same height as the top and bottom interconnecting elements.
- Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
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FIGS. 1A and 1B schematically illustrate examples of coupled inductors implemented in an IC device; -
FIGS. 2A through 2H schematically illustrate use of interconnecting elements with solder caps on substrates to implement coupled inductors in an IC device, in accordance with an exemplary embodiment; -
FIGS. 3A through 3H illustrate a process flow for creating interconnecting elements with solder caps as well as an inductor structure on a surface of a substrate, in accordance with an exemplary embodiment; and -
FIGS. 4A through 4H illustrate an alternative process flow for creating interconnecting elements with solder caps as well as an inductor structure on a surface of a substrate, in accordance with another exemplary embodiment. - For the purposes of clarity, in the following description, numerous specific details are set forth to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
- The present disclosure addresses and solves the problem of a need for additional silicon layers or thick metal layer processing attendant upon creating coupled inductors in an IC device. The present disclosure addresses and solves such problems, for instance, by, inter alia, use of interconnecting elements with solder caps on opposing substrates to implement coupled inductors in an IC device.
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FIGS. 2A through 2H schematically illustrate use of interconnecting elements with solder caps on substrates to implement coupled inductors in an IC device, in accordance with an exemplary embodiment. - A modern IC chip may be bonded to a package substrate by an array of copper pillars. Input-output (IO) circuits in the chip may be connected to some of the copper pillars while power circuits (buses) may be connected to other copper pillars in the array. The copper pillars on the IC chip are a mirror image of the copper pillars on the package substrate. Therefore, when the IC chip is flipped opposing the package substrate, the copper pillars may be bonded together by several techniques (e.g., solder reflow or thermal compression bonding). For example, a small amount of solder material on top of the copper pillars may be the bonding material.
- In some instances, instead of patterning a copper layer in the IC chip into copper pillars, long strips may be patterned on the copper layer. Also, connected copper strips may be formed into a spiral form for use in creating an inductor. Similarly, a spiral of connected copper strips may be formed on the substrate, and once the IC chip and the substrate are bonded together, the two inductor spirals opposing each other form a coupled inductor set. Solder caps placed on top of the other copper pillars can bond the IC chip to the substrate while keeping a space between the copper inductor spirals as no solder material is placed on them. The inductor spirals/elements separated by only a small distance (e.g., a few micrometers) are closely coupled for a very high coupling coefficient.
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FIG. 2A illustrates an example section of asubstrate layer 201 that includes interconnectingelements 203, which may be used to connect thesubstrate 201 to another IC substrate or to a packaging substrate. Instead of placing an IC die/chip into a final IC package, it may be used as a bare die for direct placement (e.g., flip-chip) onto a printed circuit board of an electronic device. Also, a plurality of chips may be stacked upon each other to form a 2.5-dimensional (2.5D) or 3-dimensional (3D) IC chip stack, which may then be packed into a final package. Also illustrated is an inductor structure/coil 205, includingterminals 207 and 209 at opposing ends of thecoil 205 that may be implemented on an upper surface of thesubstrate 201. An example cross sectional view A-A′, as shown inFIG. 2B , may provide a better perspective, which illustrates a partial view of the cross section A-A′ for clarity. As illustrated inFIG. 2B , an interconnectingelement 203 includes a metal (e.g., copper (Cu)) segment/pillar 211 that is connected to a bonding/landing (e.g., Cu)pad 213, which may be connected to a respective node in an IC chip or in a packaging substrate. Further, a bonding cap 215 (e.g., a solder bump) on an upper surface of themetal segment 211 may be used to bond themetal segment 211 to a bonding pad or anothermetal segment 211 on another substrate, wherein thesubstrate 201 can be bonded to the other substrate. To create an inductor structure, thecoil 205, a plurality of connected coil (e.g., Cu)line segments 217 may be created in aninductor area 219 on the upper surface of thesubstrate 201, where thecoil line segments 217 may be connected to a metal layer (e.g., a 25 micrometer Cu layer) in thesubstrate 201. Also, thecoil line segments 217 may be at a same height as themetal segments 211 of the interconnectingelements 203. - Referring to
FIG. 2C now,substrates inductors substrates FIG. 2D illustrates cross sectional views of B-B′ and C-C′ (C-C′ partially being hidden under the diagram of thesubstrate 201 a) shown inFIG. 2C . As shown inFIG. 2D , a surface of thesubstrate 201 a opposes a surface of thesubstrate 201 b, whereincoil line segments 217 a (ofcoil 205 a) as well asmetal segments 211 a (of the interconnectingelements 203 a) on the surface of thesubstrate 201 a are aligned with their respective counterparts ofcoil line segment 217 b (ofcoil 205 b) andmetal segments 211 b (of interconnectingelements 203 b) on the opposing surfaces of the 201 b. In such a configuration, themetal segments caps 215 a and 215 b, which can bond pairs of opposingmetal segments 211 to each other (hence, bonding two substrates to each other). As illustrated, thecoil line segments -
FIG. 2E illustrates asubstrate 201 that includes interconnectingelements 203 and aninductor coil 205. In semiconductor manufacturing, a layer of non-conducting under-fill material 221 may be used (e.g., injected) in the space between adjacent substrates for providing additional mechanical support. The under-fill layer may fill gaps between a single chip and a substrate, the gaps between adjacent chips in a chip stack, or a chip stack and a substrate in a final package. A cross sectional view of bondedsubstrates FIG. 2F , illustrates an under-fill layer 221 that is filling the space between the two bonded substrates. As noted, the under-fill layer 221 is of a non-conductive material that does not affect electrical connections between the two substrates nor should it affect (e.g., non-magnetic) the functionality of the coupledinductors coil line segments - However, as there may be instances where air instead of an under-fill material is more desirable (e.g., due to improved electrical characteristics), it is possible to create a walled structure surrounding the inductor elements to prevent the under-fill material from reaching the inductor elements. As illustrated in
FIG. 2G ,coil 205 of an inductor on asubstrate 201 may be rendered isolated from an under-fill layer 221, for example, by creating a wall/barrier structure 223 on an outermost perimeter of thecoil 205.FIG. 2H illustrates a cross sectional view of bondedsubstrates barrier structure 223 prevents flow of the under-fill material 221 intoinductor areas coil line segments coils barrier structure 223 may be in a same form (e.g., rectangular) of a perimeter (e.g., rectangular) of a coil that is to be isolated from the under-fill material. Thebarrier structure 223 may be formed on the surface of thesubstrate 201 a opposing the surface of thesubstrate 201 b, and once the two substrates are bonded, thebarrier structure 223 would block any under-fill material from flowing into theinductor areas barrier structure 223 may be split into two segments (e.g., height of a rectangular barrier split into two), and created on the twosubstrates barrier structure 223 may be formed by creating a continuous structure, for example, a rectangular structure formed by connected metal line segments, or abarrier structure 223 may be formed by fusing adjacent interconnecting elements surrounding the perimeter of thecoils - It is noted that a thickness of the bonding caps 215 a, 215 b, and/or
bonding pads 213 may be adjusted to vary the spacing between the set of coupled inductor coils 205 a and 205 b. Also, a width of thecoil line segments -
FIGS. 3A through 3H illustrate a process flow for creating interconnecting elements with solder caps as well as an inductor structure on a surface of a substrate, in accordance with exemplary embodiments. -
FIG. 3A illustrates bondingpads 213 on an upper surface of asubstrate layer 201. Further, a protective layer 301 (e.g., for die passivation) is formed on exposed sections of the upper surface of thesubstrate layer 201 and on upper surfaces of thebonding pads 213. Additionally,cavities 303 and cavities 305 (the number of which depends on the number of segments or rings of the inductor coil) may be formed by a lithography process, wherein thecavities bonding pads 213 through theprotective layer 301. InFIG. 3B , a metal bonding layer 307 (e.g., Cu seed layer) is deposited on an upper surface of theprotective layer 301, and in thecavities bonding pads 213.FIG. 3C illustrates afirst photoresist layer 309 formed (e.g., by a lithography process) on upper surfaces of horizontal sections of themetal bonding layer 307, but not in thecavities FIG. 3D , thecavities 303 are filled with a conductive material (e.g., Cu) to form metal segments/pillars 211. Thecavities 305 are also filled with a conductive material (e.g., Cu) to form a plurality of connectedmetal line segments 217 for forming aninductor structure 205 in aninductor area 219 on the upper surface of thesubstrate 201. The filledcavities 305 may form connected metal segments/pillars 211 for forming aninductor structure 205 in aninductor area 219 on the upper surface of thesubstrate 201. -
FIG. 3E illustrates asecond photoresist layer 311 formed on upper surfaces of thefirst photoresist layer 309 and in thecavities 305, wherein upper surfaces of themetal segments 211 are exposed. InFIG. 3F , a layer of metallic bonding material 313 (e.g., solder) is deposited (e.g., by plating or printing) on the upper surfaces of themetal segments 211 in thecavities 303. After a reflow processing of themetallic bonding material 313, as illustrated inFIG. 3G , bonding caps 215 are formed as solder bumps on the upper surfaces of themetal segments 211 incavities 303. The solder bump height may be a few micrometers and will keep the opposing inductors apart. The total height ofmetal segment 211 andsolder cap 215 may be about 25 μm. The width and pitch, however, are not limited and can be optimized for lower inductor resistance. After removal of the second andfirst photoresist layer elements 203 withsolder caps 215 and metal line segments 217 (in the inductor area 219) are formed, as shown inFIG. 3H . -
FIGS. 4A through 4H illustrate an alternative process flow for creating interconnecting elements with solder caps as well as an inductor structure on a surface of a substrate, in accordance with another exemplary embodiment. - After similar processes as discussed with reference to
FIGS. 3A and 3B ,FIG. 4A illustrates afirst photoresist layer 401 formed (e.g., by a lithography process) on upper surfaces of horizontal sections of themetal bonding layer 307 as well as in thecavities 305, but not in thecavities 303. InFIG. 4B , thecavities 303 are filled with a conductive material (e.g., Cu) to form metal segments/pillars 211, which connect to upper surfaces of thebonding pads 213 through themetal bonding layer 307 in thecavities 303. - In
FIG. 4C , a layer of metallic bonding material 313 (e.g., solder) is deposited (e.g., by plating or printing) on the upper surfaces of themetal segments 211 in thecavities 303. After a reflow processing of themetallic bonding material 313, as illustrated inFIG. 4D , bonding caps 215 are formed on the upper surfaces of themetal segments 211 in thecavities 303. -
FIG. 4E illustrates asecond photoresist layer 403 formed on upper surface of thefirst photoresist layer 401 and in thecavities 303 covering the upper surfaces of the bonding caps 215. InFIG. 4F , sections of the second and first photoresist layers, 403 and 401, are removed (e.g., etched), respectively, to expose thecavities 305. InFIG. 4G , thecavities 305 are filled with a conductive material (e.g., Cu), for example, to form a plurality of connectedmetal line segments 217 for forming aninductor structure 205 on the upper surface of thesubstrate 201 in aninductor area 219. Also, the filledcavities 305 may form connected metal segments/pillars 211 for forming aninductor structure 205 on the upper surface of thesubstrate 201 in aninductor area 219. After removal of the second and first photoresist layers 403 and 401, respectively, interconnectingelements 203 and metal line segments 217 (in the inductor area 219) are formed, as shown inFIG. 4H . - The embodiments of the present disclosure can achieve several technical effects, including forming coupled inductors in an IC device with only a small additional cost, only one additional mask, no additional plating costs, and a narrow spacing between the two inductors due to the use of solder caps. Furthermore, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use static-random-access memory (SRAM) cells (e.g., liquid crystal display (LCD) drivers, digital processors, etc.)
- In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
Claims (20)
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US14/798,604 US9646758B2 (en) | 2015-07-14 | 2015-07-14 | Method of fabricating integrated circuit (IC) devices |
US15/430,596 US11557420B2 (en) | 2015-07-14 | 2017-02-13 | Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices |
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Cited By (5)
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---|---|---|---|---|
WO2019221808A1 (en) * | 2018-05-17 | 2019-11-21 | Qualcomm Incorporated | Solenoid structure with conductive pillar technology |
CN111415813A (en) * | 2019-01-07 | 2020-07-14 | 台达电子企业管理(上海)有限公司 | Method for preparing inductor with vertical winding and injection molding die thereof |
US11227856B2 (en) | 2019-01-07 | 2022-01-18 | Delta Electronics (Shanghai) Co., Ltd. | Multi-chip package power module |
US11316438B2 (en) | 2019-01-07 | 2022-04-26 | Delta Eletronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6885090B2 (en) * | 2001-11-28 | 2005-04-26 | North Carolina State University | Inductively coupled electrical connectors |
US7663225B2 (en) * | 2004-07-23 | 2010-02-16 | Murata Manufacturing Co., Ltd. | Method for manufacturing electronic components, mother substrate, and electronic component |
US7583165B2 (en) * | 2005-02-07 | 2009-09-01 | Tessera, Inc. | High Q cavity resonators for microelectronics |
US8362481B2 (en) * | 2007-05-08 | 2013-01-29 | Scanimetrics Inc. | Ultra high speed signal transmission/reception |
EP2242066A1 (en) * | 2009-04-17 | 2010-10-20 | Nxp B.V. | Inductive components for dc/dc converters and methods of manufacture thereof |
KR20130077400A (en) * | 2011-12-29 | 2013-07-09 | 삼성전기주식회사 | Thin film type coil component and fabricating method thereof |
US10002700B2 (en) * | 2013-02-27 | 2018-06-19 | Qualcomm Incorporated | Vertical-coupling transformer with an air-gap structure |
US9160423B2 (en) * | 2013-12-12 | 2015-10-13 | Freescale Semiconductor, Inc. | Die-to-die inductive communication devices and methods |
KR101642610B1 (en) * | 2014-12-30 | 2016-07-25 | 삼성전기주식회사 | Coil component and method of manufacturing the same |
-
2015
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2019221808A1 (en) * | 2018-05-17 | 2019-11-21 | Qualcomm Incorporated | Solenoid structure with conductive pillar technology |
US10693432B2 (en) | 2018-05-17 | 2020-06-23 | Qualcommm Incorporated | Solenoid structure with conductive pillar technology |
CN111415813A (en) * | 2019-01-07 | 2020-07-14 | 台达电子企业管理(上海)有限公司 | Method for preparing inductor with vertical winding and injection molding die thereof |
US11227856B2 (en) | 2019-01-07 | 2022-01-18 | Delta Electronics (Shanghai) Co., Ltd. | Multi-chip package power module |
US11316438B2 (en) | 2019-01-07 | 2022-04-26 | Delta Eletronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
CN111415813B (en) * | 2019-01-07 | 2022-06-17 | 台达电子企业管理(上海)有限公司 | Method for preparing inductor with vertical winding and injection molding die thereof |
US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
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US11557420B2 (en) | 2023-01-17 |
US20170154722A1 (en) | 2017-06-01 |
US9646758B2 (en) | 2017-05-09 |
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