CN106961262A - A kind of delay bistable circuit based on memristor - Google Patents
A kind of delay bistable circuit based on memristor Download PDFInfo
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- CN106961262A CN106961262A CN201710329528.7A CN201710329528A CN106961262A CN 106961262 A CN106961262 A CN 106961262A CN 201710329528 A CN201710329528 A CN 201710329528A CN 106961262 A CN106961262 A CN 106961262A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of delay bistable circuit based on memristor, the external input pulse of bistable circuit, input of the output end of bistable circuit respectively with positive and negative current circuit and voltage follower circuit to be compared is connected, the output end of positive and negative current circuit and the input of division circuit are connected, the output end of division circuit exports a voltage to be compared, the output end of division circuit and the positive input terminal of comparator are connected, under the control that bistable circuit is exported, voltage follower circuit to be compared exports another voltage to be compared, the output end of voltage follower circuit to be compared and the negative input end of comparator are connected, the output end of comparator is the output end of the delay bistable circuit.The present invention is combined due to employing memristor in the design of whole circuit with the science of other elements, eliminate the trouble of external capacitor or inductance, many troubles present in prior art are solved, design science is compact, the more preferable exploitation of favourable bistable circuit market application.
Description
Technical field
The present invention relates to one kind delay bistable circuit, and in particular to a kind of delay bistable circuit based on memristor.
Background technology
Traditional bistable circuit is in order to be delayed, frequently with digital circuit, or is realized using software, these tradition
Bistable circuit be semiconductor circuit, be difficult integrated capacitance in integrated circuit fabrication or inductance, it is necessary to use external capacitor
Or inductance, circuit structure complexity, thus it is unfavorable for the problems such as overall the integrated of delay bistable circuit, miniaturization.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of delay bistable circuit based on memristor.
In order to achieve the above object, the technical solution adopted in the present invention is：
A kind of delay bistable circuit based on memristor, including bistable circuit, the positive counter current electricity based on memristor M
Road, division circuit, comparator and the voltage follower circuit to be compared by bistable circuit output control；
The external input pulse of bistable circuit, the output end of bistable circuit respectively with positive and negative current circuit and electricity to be compared
The input connection of voltage follower circuit, the output end of positive and negative current circuit and the input of division circuit are connected, division circuit
Output end exports a voltage to be compared, and the output end of division circuit and the positive input terminal of comparator are connected, defeated in bistable circuit
Under the control gone out, voltage follower circuit to be compared exports another voltage to be compared, the output end of voltage follower circuit to be compared with
The negative input end connection of comparator, the output end of comparator is the output end of the delay bistable circuit.
Bistable circuit is the bistable circuit that d type flip flop is constituted, the external input pulse in CK ends of d type flip flop, d type flip flop
S ends connection power Vcc, d type flip flop R ends ground connection, the Q ends of d type flip flop andThe output end for bistable circuit is held, D is touched
Send out device D ends withEnd connection.
Positive and negative current circuit is opened including memristor M, resistance R1, resistance R2, analog switch IC1, analog switch IC2, simulation
Close IC3 and analog switch IC4；
Analog switch IC1 and analog switch IC4 control end are the input of positive and negative current circuit, analog switch IC2's
Input connects power Vcc, and analog switch IC2 control end is connected with analog switch IC1 control end, analog switch IC2's
Output end is connected with memristor M anode and analog switch IC4 input respectively, and memristor M negative terminal is opened with simulation respectively
The output end connection of IC1 input and analog switch IC3 is closed, analog switch IC3 input connection power Vcc, simulation is opened
The control end for closing IC3 is connected with analog switch IC4 control end, and analog switch IC4 output end is grounded by resistance R2, simulation
Switch IC1 output end is grounded by resistance R1, and memristor M two ends are the output end of positive and negative current circuit.
The first adjustable constant flow source circuit is provided between analog switch IC2 input and power Vcc；First adjustable constant-flow
Source circuit includes FET T1 and adjustable resistance RP1, FET T1 drain electrode connection power Vcc, FET T1 source
Pole is connected with an adjustable resistance RP1 fixing end, the input of adjustable resistance RP1 another fixing end respectively with analog switch IC2
The grid connection of end connection, adjustable resistance RP1 sliding end and FET T1.
The second adjustable constant flow source circuit is provided between analog switch IC3 input and power Vcc；Second adjustable constant-flow
Source circuit includes FET T2 and adjustable resistance RP2, FET T2 drain electrode connection power Vcc, FET T2 source
Pole is connected with an adjustable resistance RP2 fixing end, the input of adjustable resistance RP2 another fixing end respectively with analog switch IC3
The grid connection of end connection, adjustable resistance RP2 sliding end and FET T2.
Voltage follower circuit to be compared include analog switch IC5, analog switch IC6, resistance R3, resistance R4, resistance R5 and
Resistance R6；
Analog switch IC5 and analog switch IC6 control end are the input of voltage follower circuit to be compared, resistance R3's
One end connects power Vcc, and the resistance R3 other end is connected with analog switch IC5 input and resistance R4 one end respectively, electricity
R4 other end ground connection is hindered, analog switch IC5 output end is connected with analog switch IC6 output end, and resistance R5 one end connects
Power Vcc is connect, the resistance R5 other end is connected with analog switch IC6 input and resistance R6 one end respectively, resistance R6's
The other end is grounded, and analog switch IC6 output end is the output end of voltage follower circuit to be compared.
The beneficial effect that the present invention is reached：The present invention in the design of whole circuit due to employing memristor and other members
The science combination of part, the delay bistable circuit constituted can reach compact effect, whereby also eliminating external capacitor or inductance
Trouble, facilitated in production application circuit it is integrated and miniaturization, solve many troubles present in prior art, design
Science is compact, the more preferable exploitation of favourable bistable circuit market application.
Brief description of the drawings
Fig. 1 is circuit diagram of the invention；
Fig. 2 is delay output voltage waveform.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
As shown in figure 1, a kind of delay bistable circuit based on memristor, including bistable circuit, based on memristor M's
Positive and negative current circuit, division circuit MPY, comparator LM and the voltage follower circuit to be compared by bistable circuit output control.
The external input pulse of bistable circuit, the output end of bistable circuit respectively with positive and negative current circuit and electricity to be compared
The input connection of voltage follower circuit, the output end of positive and negative current circuit is connected with division circuit MPY input, division circuit
MPY output end exports a voltage to be compared, and division circuit MPY output end is connected with comparator LM positive input terminal, double
Under the control of steady-state circuit output, voltage follower circuit to be compared exports another voltage to be compared, voltage follower circuit to be compared
Output end be connected with comparator LM negative input end, comparator LM output end is the output of the delay bistable circuit
End.
Bistable circuit is the bistable circuit that d type flip flop is constituted, the external input pulse in CK ends of d type flip flop, d type flip flop
S ends connection power Vcc, d type flip flop R ends ground connection, the Q ends of d type flip flop andThe output end for bistable circuit is held, D is touched
Send out device D ends withEnd connection.
Positive and negative current circuit is opened including memristor M, resistance R1, resistance R2, analog switch IC1, analog switch IC2, simulation
Close IC3 and analog switch IC4.Analog switch IC1 and analog switch IC4 control end are the input of positive and negative current circuit, mould
Intend switch IC1 control end and the Q ends of d type flip flop are connected, analog switch IC4 control end and d type flip flopEnd connection, mould
Intend switch IC2 input connection power Vcc, analog switch IC2 control end is connected with analog switch IC1 control end, mould
The output end for intending switch IC2 is connected with memristor M anode and analog switch IC4 input respectively, memristor M negative terminal point
It is not connected with analog switch IC1 input and analog switch IC3 output end, analog switch IC3 input connection power supply
Vcc, analog switch IC3 control end are connected with analog switch IC4 control end, and analog switch IC4 output end passes through resistance
R2 is grounded, and analog switch IC1 output end is grounded by resistance R1, and memristor M two ends are the output end of positive and negative current circuit.
The first adjustable constant flow source circuit is provided between analog switch IC2 input and power Vcc.First adjustable constant-flow
Source circuit includes FET T1 and adjustable resistance RP1, FET T1 drain electrode connection power Vcc, FET T1 source
Pole is connected with an adjustable resistance RP1 fixing end, the input of adjustable resistance RP1 another fixing end respectively with analog switch IC2
The grid connection of end connection, adjustable resistance RP1 sliding end and FET T1.
The second adjustable constant flow source circuit is provided between analog switch IC3 input and power Vcc.Second adjustable constant-flow
Source circuit includes FET T2 and adjustable resistance RP2, FET T2 drain electrode connection power Vcc, FET T2 source
Pole is connected with an adjustable resistance RP2 fixing end, the input of adjustable resistance RP2 another fixing end respectively with analog switch IC3
The grid connection of end connection, adjustable resistance RP2 sliding end and FET T2.
Voltage follower circuit to be compared include analog switch IC5, analog switch IC6, resistance R3, resistance R4, resistance R5 and
Resistance R6.Analog switch IC5 and analog switch IC6 control end are the input of voltage follower circuit to be compared, analog switch
IC5 control end and d type flip flopEnd connection, analog switch IC6 control end and the Q ends of d type flip flop are connected, resistance R3's
One end connects power Vcc, and the resistance R3 other end is connected with analog switch IC5 input and resistance R4 one end respectively, electricity
R4 other end ground connection is hindered, analog switch IC5 output end is connected with analog switch IC6 output end, and resistance R5 one end connects
Power Vcc is connect, the resistance R5 other end is connected with analog switch IC6 input and resistance R6 one end respectively, resistance R6's
The other end is grounded, and analog switch IC6 output end is the output end of voltage follower circuit to be compared.
The model CD4013 of above-mentioned d type flip flop, analog switch IC2, analog switch IC3, analog switch IC4, simulation are opened
Close IC5 and analog switch IC6 model CD4066, division circuit MPY model MPY100, comparator LM model
LM339。
The operation principle of foregoing circuit is as follows：Memristor M is a kind of primary element with memory characteristic, as memristor M
Structure it is certain after, memristor M resistance RMFrom minimum value RonIt is gradually increased to maximum RoffRequired time and adjustable perseverance
The size of the output current of current source circuit is relevant, changes the size of adjustable resistance, thus it is possible to vary adjustable constant flow source circuit output electricity
The size of stream, therefore change delay time by changing the size of adjustable constant flow source circuit output current, so as to complete to utilize
Memristor M realizes delay.
When the electric current I for flowing through memristor M is constant current, memristor M resistance RMFrom minimum value RonIt is gradually increased to maximum
Value RoffRequired time t is：
Wherein, C is relevant with memristor M concrete structure, is memristor M structural coefficient.
Specific work process is as follows：
When whole circuit switches on power Vcc, the S termination high level of d type flip flop, the R termination low levels of d type flip flop, D is touched
The Q ends end output high level of device is sent out, analog switch IC1, analog switch IC2 are connected with analog switch IC6；D type flip flopEnd
Low level is exported, analog switch IC3, analog switch IC4 and analog switch IC5 disconnect.Appropriately designed resistance R1's and resistance R2
Resistance, wherein R1=Ron, R2=Roff, because now electric current from memristor M anode flow to negative terminal, through after a while, memristor
Device M resistance RMEqual to minimum value Ron, now memristor M terminal voltage value reach the voltage at minimum, division circuit MPY outputs
(i.e. the positive input terminal input of comparator LM)Appropriately designed resistance R5 and resistance R6 resistance, make resistance
The voltage V- of the negative input end input of voltage between R5 and resistance R6, i.e. comparator LM is 0.5V, and now comparator LM is exported
Pulse V0For high level.
As first input pulse VPDuring arrival, the CK ends of d type flip flop are changed into high level, the Q ends of d type flip flop from low level
Low level is exported, analog switch IC1, analog switch IC2 and analog switch IC6 disconnect；D type flip flopExport high level, mould
Intend switch IC3, analog switch IC4 to connect with analog switch IC5.Electric current from memristor M negative terminal flow to anode, during one section of delay
Between t, memristor M resistance RMEqual to maximum Roff, now memristor M terminal voltage reach maximum, division circuit MPY outputs
The voltage (i.e. the positive input terminal input of comparator LM) at placeAppropriately designed resistance R3 and resistance R4 resistance
Value, the voltage V- for inputting the voltage between resistance R3 and resistance R4, i.e. comparator LM negative input end is 2V, now comparator
LM output pulse V0For high level.It is achieved thereby that comparator LM delay state upset.Change the big of adjustable resistance RP2
It is small, thus it is possible to vary comparator LM output ends export low level delay time.
As second input pulse VPDuring arrival, the CK ends of d type flip flop are changed into high level from low level, d type flip flop
Q ends output high level, analog switch IC1, analog switch IC2 are connected with analog switch IC6；D type flip flopEnd output is low
Level, analog switch IC3, analog switch IC4 and analog switch IC5 disconnect.Electric current from memristor M anode flow to negative terminal, prolong
When t, memristor M resistance R for a period of timeMEqual to minimum value Ron, now memristor M terminal voltage reach minimum.Through division electricity
Road MPY division arithmetics, comparator LM positive input terminals voltage is equal to negative input end voltage, i.e. V+=V-=0.5V, now comparator LM
Output pulse V0For high level.It is achieved thereby that comparator LM delay state upset.Change adjustable resistance RP1 size,
The delay time that comparator LM output ends export high level can be changed.
As the input pulse V that has another oneP, move in circles, each delay state rotary movement completed, specifically such as Fig. 2 institutes
State.Change adjustable resistance RP1 or adjustable resistance RP2 resistance, thus it is possible to vary during the delay of comparator LM output end output levels
Between, it comparator LM output ends is exported low level delay time different with the delay time of output high level.
Foregoing circuit is combined due to employing memristor M in the design of whole circuit with the science of other elements, is constituted
Delay bistable circuit can reach compact effect, the trouble of external capacitor or inductance is whereby also eliminating, in production application
Facilitate circuit it is integrated and miniaturization, solve many troubles present in prior art, design science is compact, favourable bistable state
The more preferable exploitation of circuit markets application.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of the technology of the present invention principle is not departed from, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of delay bistable circuit based on memristor, it is characterised in that：Including bistable circuit, based on memristor M's
Positive and negative current circuit, division circuit, comparator and the voltage follower circuit to be compared by bistable circuit output control；
The external input pulse of bistable circuit, the output end of bistable circuit is defeated with positive and negative current circuit and voltage to be compared respectively
Go out the input connection of circuit, the output end of positive and negative current circuit and the input of division circuit are connected, the output of division circuit
One voltage to be compared of end output, the output end of division circuit and the positive input terminal of comparator are connected, exported in bistable circuit
Under control, voltage follower circuit to be compared exports another voltage to be compared, and the output end of voltage follower circuit to be compared is with being compared
The negative input end connection of device, the output end of comparator is the output end of the delay bistable circuit.
2. a kind of delay bistable circuit based on memristor according to claim 1, it is characterised in that：Bistable circuit
The bistable circuit constituted for d type flip flop, the external input pulse in CK ends of d type flip flop, the S ends connection power Vcc of d type flip flop, D
Trigger R ends ground connection, the Q ends of d type flip flop andHold the output end for bistable circuit, the D ends of d type flip flop withEnd connects
Connect.
3. a kind of delay bistable circuit based on memristor according to claim 1, it is characterised in that：Positive counter current electricity
Road includes memristor M, resistance R1, resistance R2, analog switch IC1, analog switch IC2, analog switch IC3 and analog switch IC4；
Analog switch IC1 and analog switch IC4 control end are the input of positive and negative current circuit, analog switch IC2 input
End connection power Vcc, analog switch IC2 control end is connected with analog switch IC1 control end, analog switch IC2 output
End is connected with memristor M anode and analog switch IC4 input respectively, memristor M negative terminal respectively with analog switch IC1
Input and analog switch IC3 output end connection, analog switch IC3 input connection power Vcc, analog switch IC3
Control end be connected with analog switch IC4 control end, analog switch IC4 output end is grounded by resistance R2, analog switch
IC1 output end is grounded by resistance R1, and memristor M two ends are the output end of positive and negative current circuit.
4. a kind of delay bistable circuit based on memristor according to claim 3, it is characterised in that：Analog switch
The first adjustable constant flow source circuit is provided between IC2 input and power Vcc；First adjustable constant flow source circuit includes field-effect
Pipe T1 and adjustable resistance RP1, FET T1 drain electrode connection power Vcc, FET T1 source electrode is with adjustable resistance RP1's
One fixing end is connected, and adjustable resistance RP1 another fixing end is connected with analog switch IC2 input respectively, adjustable resistance RP1
Sliding end and FET T1 grid connection.
5. a kind of delay bistable circuit based on memristor according to claim 3, it is characterised in that：Analog switch
The second adjustable constant flow source circuit is provided between IC3 input and power Vcc；Second adjustable constant flow source circuit includes field-effect
Pipe T2 and adjustable resistance RP2, FET T2 drain electrode connection power Vcc, FET T2 source electrode is with adjustable resistance RP2's
One fixing end is connected, and adjustable resistance RP2 another fixing end is connected with analog switch IC3 input respectively, adjustable resistance RP2
Sliding end and FET T2 grid connection.
6. a kind of delay bistable circuit based on memristor according to claim 1, it is characterised in that：Voltage to be compared
Output circuit includes analog switch IC5, analog switch IC6, resistance R3, resistance R4, resistance R5 and resistance R6；
Analog switch IC5 and analog switch IC6 control end are the input of voltage follower circuit to be compared, resistance R3 one end
Power Vcc is connected, the resistance R3 other end is connected with analog switch IC5 input and resistance R4 one end respectively, resistance R4
Other end ground connection, analog switch IC5 output end be connected with analog switch IC6 output end, and resistance R5 one end connects electric
Source Vcc, resistance the R5 other end are connected with analog switch IC6 input and resistance R6 one end respectively, and resistance R6's is another
End ground connection, analog switch IC6 output end is the output end of voltage follower circuit to be compared.
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