CN106952946B - 一种过渡区结构 - Google Patents

一种过渡区结构 Download PDF

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CN106952946B
CN106952946B CN201710258517.4A CN201710258517A CN106952946B CN 106952946 B CN106952946 B CN 106952946B CN 201710258517 A CN201710258517 A CN 201710258517A CN 106952946 B CN106952946 B CN 106952946B
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马荣耀
刘春华
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China Resources Microelectronics Chongqing Ltd
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Abstract

本发明提供一种过渡区结构，适用于具有超结结构的半导体器件，包括：衬底；外延层，外延层设置在衬底的上方；多个第一立柱与多个第二立柱形成超结结构；复合结构包括元胞区、终端区及位于元胞区和终端区之间的过渡区；过渡区具有一第二导电类型的第一掺杂区域；元胞区设置有MOS管器件结构，MOS管器件结构设置有具有第二导电类型的第二掺杂区域，用以形成MOS管器件结构的源区或者漏区；临近过渡区的第二掺杂区域通过一设置于外延层内的电阻结构连接第一掺杂区域。本发明的有益效果：在雪崩击穿发生后，由于电阻结构的存在，来自过渡区和终端区的雪崩电流可以更快的扩散到元胞区，从而增大器件抗冲击电流的能力，增大其耐用度。

Description

一种过渡区结构
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种适用于具有超结结构的半导体器件的过渡区结构。
背景技术
现有的高压超结金氧半场效晶体管(Metal-Oxide-Semiconductor Field-EffectTransistor，MOSFET)器件终端结构，包括元胞区和终端区，元胞区和终端区之间具有过渡区。
以图1为例，元胞区1包括衬底11、位于衬底11上的第一导电类型的外延层12、位于第一导电类型的外延层12内的第二导电类型的导柱14、位于第二导电类型的导柱14上方的第二导电类型的第一本体区15和位于第二导电类型的第一本体区15内的第一导电类型的源区16；第二导电类型的导柱14间隔分布，相连两个第二导电类型的导柱14之间的第一导电类型的外延层12为第一导电类型的导柱13，使得第一导电类型的导柱13与第二导电类型的导柱14沿着电流通路的方向在第一导电类型的外延层12内延伸，在垂直电流通路的方向交替连接设置，形成超结结构。第一导电类型的外延层12的上表面形成有多个栅极结构17，每个栅极结构均位于相邻两个第一本体区之间相邻栅极结构17之间设有覆盖第一本体区15和源区16的接触孔18，在元胞区上方填充金属使金属覆盖接触孔和栅极结构形成与第一本体区15和源区16电连接的源极电极19；
继续参照图1，终端区在垂直于电流通路方向上环绕元胞区，终端区包括衬底、位于衬底上的第一导电类型的外延层、位于第一导电类型的外延层内的第一导电类型的导柱113和第二导电类型的导柱114，第一导电类型的导柱113和第二导电类型的导柱114沿着电流通路的方向在外延层12内延伸，在垂直电流通路的方向交替连接设置，形成超结结构；
继续参照图1，过渡区在垂直于电流通路方向上被终端区所环绕，过渡区包括衬底11、位于衬底11上的第一导电类型的外延层12、位于第一导电类型的外延层12内的第一导电类型的导柱110和第二导电类型的导柱111、位于第一导电类型的外延层12内的第二导电类型的第二本体区112；第二本体区112将过渡区内的至少一个第二导电类型的导柱111连接至元胞区内的第一导电类型的源区16。
如图1所示，在传统过渡区设计中，常常需要额外增加一道掩膜工艺来形成一个第二导电类型的区域，该第二导电类型的区域对应上述的第二本体区112，第二本体区112的掺杂浓度比第一本体区15的掺杂浓度较低，因此不会增加此区域的电荷少子注入，该第二导电类型的区域用于在电学上连接所覆盖的过渡区的几个第二导电类型的导柱111，使过渡区和元胞区一样都处于电荷平衡，增大器件抗冲击电流，提高器件耐用度。然而，现有的第二本体区112的设计需要增加工艺成本，在保持过渡区电荷平衡、增大器件抗冲击电流、提高器件耐用度等方面的效果不理想。
发明内容
针对现有技术中存在的问题，本发明提供了一种能够提高具有超结结构的半导体器件的抗冲击电流能力，增大器件耐用度的过渡区结构。
本发明采用如下技术方案：
一种过渡区结构，所述过渡区结构适用于具有超结结构的半导体器件，所述半导体器件包括复合结构，所述复合结构包括：
衬底，由具有第一导电类型的半导体材质形成；
外延层，所述外延层设置在所述衬底的上方，所述外延层的导电类型与所述衬底的导电类型相同；
多个具有第一导电类型的第一立柱及多个具有第二导电类型的第二立柱，相互间隔且垂直于所述衬底的设置于所述外延层中，所述多个第一立柱与所述多个第二立柱形成超结结构；
所述复合结构包括元胞区、终端区及位于所述元胞区和所述终端区之间的过渡区；
所述过渡区具有一第二导电类型的第一掺杂区域，用以连接位于所述过渡区的多个第二导电类型的所述第二立柱的顶部；
所述元胞区设置有MOS管器件结构，所述MOS管器件结构设置有具有第二导电类型的第二掺杂区域，用以形成所述MOS管器件结构的源区或者漏区；
临近所述过渡区的所述第二掺杂区域通过一设置于所述外延层内的电阻结构连接所述第一掺杂区域。
优选的，所述电阻结构由一第二导电类型的第三掺杂区域形成，所述第三掺杂区域的掺杂浓度低于所述第一掺杂区域。
优选的，所述第一掺杂区域的掺杂浓度与所述第二掺杂区域的掺杂浓度相同。
优选的，所述电阻结构上方覆盖有多晶硅层。
优选的，所述MOS管器件结构具有多晶硅结构形成的栅极，所述多晶硅层与所述多晶硅结构由同一掩膜于同一工艺中形成。
优选的，所述第一掺杂区域与所述第二掺杂区域由同一掩膜于同一离子注入工艺中形成。
优选的，所述第三掺杂区域的掺杂浓度为N<1e16cm-3。
优选的，所述元胞区、过渡区及终端区被设置于一具有第一导电类型的阱区内，所述阱区具有一第二导电类型的第四掺杂区域，所述第四掺杂区域成环形或者框形包围所述阱区。
优选的，所述第四掺杂区域具有与所述第三掺杂区域相同的掺杂浓度。
优选的，所述第三掺杂区域成环形或者框形包围所述元胞区。
本发明的有益效果是：临近所述过渡区的所述第二掺杂区域通过一设置于所述外延层内的电阻结构连接所述第一掺杂区域，将该电阻结构作为具有较大电阻值的负反馈电阻，则在雪崩击穿发生后，大量的过渡区和终端区雪崩电流被过渡区的第二立柱收集后经外延层的上表面流入元胞区的接触孔流出，由于负反馈电阻的存在，来自过渡区和终端区的雪崩电流可以更快的扩散到元胞区，从而增大器件抗冲击电流的能力，增大其耐用度。
附图说明
图1为现有技术中，具有超结结构的半导体器件的结构示意图；
图2为本发明的一种优选实施例中，具有超结结构的半导体结构的示意图；
图3为本发明的一种优选的实施例中，雪崩击穿后电流流向示意图之一；
图4为本发明的一种优选的实施例中，雪崩击穿后电流流向示意图之二；
图5为本发明的一种优选的实施例中，雪崩击穿后电流流向示意图之三。；
图6为本发明的一种优选的实施例中，现有过渡区和本申请过渡区的内部电压仿真结果对比示意图。
具体实施方式
需要说明的是，在不冲突的状态下，下述技术方案，技术特征之间可以相互组合。
下面结合附图对本发明的具体实施方式作进一步的说明：
如图2-5所示，一种过渡区结构，上述过渡区结构适用于具有超结结构的半导体器件，上述半导体器件包括复合结构，上述复合结构包括：
衬底1，由具有第一导电类型的半导体材质形成；
外延层2，上述外延层2设置在上述衬底1的上方，上述外延层2的导电类型与上述衬底1的导电类型相同；
多个具有第一导电类型的第一立柱3及多个具有第二导电类型的第二立柱4，相互间隔且垂直于上述衬底1的设置于上述外延层2中，上述多个第一立柱3与上述多个第二立柱4形成超结结构；
上述复合结构包括元胞区、终端区及位于上述元胞区和上述终端区之间的过渡区；
上述过渡区具有一第二导电类型的第一掺杂区域5，用以连接位于上述过渡区的多个第二导电类型的上述第二立柱4的顶部；
上述元胞区设置有MOS管器件结构7，上述MOS管器件结构7设置有具有第二导电类型的第二掺杂区域6，用以形成上述MOS管器件结构7的源区或者漏区；
临近上述过渡区的上述第二掺杂区域6通过一设置于上述外延层2内的电阻结构连接上述第一掺杂区域5。
在本实施例中，临近上述过渡区的上述第二掺杂区域6通过一设置于上述外延层2内的电阻结构连接上述第一掺杂区域5，将该电阻结构作为具有较大电阻值的负反馈电阻，则在雪崩击穿发生后，大量的过渡区和终端区雪崩电流被过渡区的第二立柱4收集后经外延层2的上表面流入元胞区的接触孔流出，由于负反馈电阻的存在，来自过渡区和终端区的雪崩电流可以更快的扩散到元胞区，从而增大器件抗冲击电流的能力，增大其耐用度。
本发明较佳的实施例中，上述电阻结构由一第二导电类型的第三掺杂区域8形成，上述第三掺杂区域8的掺杂浓度低于上述第一掺杂区域5。
本发明较佳的实施例中，上述第一掺杂区域5的掺杂浓度与上述第二掺杂区域6的掺杂浓度相同。
本发明较佳的实施例中，上述电阻结构上方覆盖有多晶硅层9。
本发明较佳的实施例中，上述MOS管器件结构7具有多晶硅结构10形成的栅极，上述多晶硅层9与上述多晶硅结构10由同一掩膜(第一掩膜)于同一工艺中形成。
在本实施例中，利用现有技术中的形成栅极多晶硅结构10的第一掩膜并在第一掩膜对应多晶硅层9的位置开窗，以便形成上述多晶硅层9。
本发明较佳的实施例中，上述第一掺杂区域5与上述第二掺杂区域6由同一掩膜(第二掩膜)于同一离子注入工艺中形成。
在本实施例中，利用现有技术中形成第二掺杂区域6的第二掩膜并在第二掩膜对应第一掺杂区域5的位置开窗，以便形成上述第一掺杂区域5。
相比现有技术，只需要第一掩膜和第二掩膜即可实现过渡区的第二立柱4与元胞区之间的电性连接。在本实施例中，通过对第一掩膜和第二掩膜的控制，使得在第一掺杂区域5进行离子注入时，由于电阻结构处的多晶硅层9阻断了离子注入，使得第一掺杂区域5和第二掺杂区域6断开，同时，在第三掺杂区域8通过低浓度的离子注入，第一掺杂区域5通过第三掺杂区域8与元胞区电学连接。
本发明较佳的实施例中，上述第三掺杂区域8的掺杂浓度为N<1e16cm-3。
本发明较佳的实施例中，上述元胞区、过渡区及终端区被设置于一具有第一导电类型的阱区内，上述阱区具有一第二导电类型的第四掺杂区域11，上述第四掺杂区域11成环形或者框形包围上述阱区。
在本实施例中，第三掺杂区域8和第四掺杂区域11可以通过同一张掩膜在同一离子注入工艺中形成，只需利用现有技术中形成第四掺杂区域11的掩膜，并在该掩膜对应第三掺杂区域8的位置处开窗即可实现。
上述技术方案中，第一掺杂区域5，作为电阻结构的第三掺杂区域8可通过现有的MOS管器件源漏工艺，以及阱区保护环工艺中的掩膜来实现，因此该过渡区结构相较于现有技术，减少了一道掩膜工艺，降低了工艺成本和复杂度。
在本申请中，衬底为硅衬底，外延层为N型外延层，第一立柱为N柱，第二立柱为P柱，第一掺杂区域5、第二掺杂区域6、第三掺杂区域8及第四掺杂区域11利用P型掺杂工艺形成。上述第四掺杂区域11能够用于吸收n阱中的电子，防止n阱中的电子和其他的模块形成放大模块；从而导致产生的一低阻抗通路。
本发明较佳的实施例中，上述第四掺杂区域11具有与上述第三掺杂区域8相同的掺杂浓度。
本发明较佳的实施例中，上述第三掺杂区域8成环形或者框形包围上述元胞区。
对于本领域的技术人员而言，阅读上述说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容，都应认为仍属本发明的意图和范围内。

Claims (9)

1.一种过渡区结构，所述过渡区结构适用于具有超结结构的半导体器件，所述半导体器件包括复合结构，所述复合结构包括：
衬底，由具有第一导电类型的半导体材质形成；
外延层，所述外延层设置在所述衬底的上方，所述外延层的导电类型与所述衬底的导电类型相同；
多个具有第一导电类型的第一立柱及多个具有第二导电类型的第二立柱，相互间隔且垂直于所述衬底设置于所述外延层中，所述多个第一立柱与所述多个第二立柱形成超结结构；
所述复合结构包括元胞区、终端区及位于所述元胞区和所述终端区之间的过渡区；
所述过渡区具有一第二导电类型的第一掺杂区域，用以接触位于所述过渡区的多个第二导电类型的所述第二立柱的顶部；
所述元胞区设置有MOS管器件结构，所述MOS管器件结构设置有具有第二导电类型的第二掺杂区域，用以形成所述MOS管器件结构的源区或者漏区；其特征在于，
临近所述过渡区的所述第二掺杂区域通过一设置于所述外延层内的电阻结构连接所述第一掺杂区域；
所述电阻结构由一第二导电类型的第三掺杂区域形成，所述第三掺杂区域的掺杂浓度低于所述第一掺杂区域；
于所述半导体器件的截面角度，所述第三掺杂区域的一侧接触所述第一掺杂区域，所述第三掺杂区域的另一侧接触所述第二掺杂区域。
2.根据权利要求1所述的过渡区结构，其特征在于，所述第一掺杂区域的掺杂浓度与所述第二掺杂区域的掺杂浓度相同。
3.根据权利要求1所述的过渡区结构，其特征在于，所述电阻结构上方覆盖有多晶硅层。
4.根据权利要求3所述的过渡区结构，其特征在于，所述MOS管器件结构具有多晶硅结构形成的栅极，所述多晶硅层与所述多晶硅结构由同一掩膜于同一工艺中形成。
5.根据权利要求1所述的过渡区结构，其特征在于，所述第一掺杂区域与所述第二掺杂区域由同一掩膜于同一离子注入工艺中形成。
6.根据权利要求1所述的过渡区结构，其特征在于，所述第三掺杂区域的掺杂浓度为N<1e16cm-3。
7.根据权利要求1所述的过渡区结构，其特征在于，所述元胞区、过渡区及终端区被设置于一具有第一导电类型的阱区内，所述阱区具有一第二导电类型的第四掺杂区域，所述第四掺杂区域成环形或者框形包围所述阱区。
8.根据权利要求7所述的过渡区结构，其特征在于，所述第四掺杂区域具有与所述第三掺杂区域相同的掺杂浓度。
9.根据权利要求1所述的过渡区结构，其特征在于，所述第三掺杂区域成环形或者框形包围所述元胞区。
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