CN106952905A - 半导体装置及其制作方法 - Google Patents

半导体装置及其制作方法 Download PDF

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CN106952905A
CN106952905A CN201611184627.2A CN201611184627A CN106952905A CN 106952905 A CN106952905 A CN 106952905A CN 201611184627 A CN201611184627 A CN 201611184627A CN 106952905 A CN106952905 A CN 106952905A
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semiconductor device
doped polysilicon
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fet
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CN106952905B (zh
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大卫·J·鲍德温
加里·尤金·道姆
西蒙·约翰·莫洛伊
阿比迪尔·拉赫曼
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Texas Instruments Inc
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Abstract

本发明揭示一种半导体装置(100B、200A、200B)及制作方法(图6)。装置包含衬底、电力场效应晶体管FET(FET1、FET2)及集成传感器，集成传感器包含电流传感器(130、206，图3)、高电流故障传感器(138、208，图5B)及温度传感器(134、210，图4B)。电力FET(与图3中所展示的引导FET相同)的结构包含：第一导电性类型的漏极触点区域(302)，其安置于衬底中；第一导电性类型的漏极漂移区域(304)，其安置于漏极触点区域上方；经掺杂多晶硅沟槽(306)，其安置于漏极漂移区域中；与第一导电性类型相反的第二导电性类型的主体区域(314)，其安置于经掺杂多晶硅沟槽之间；源极区域(312)，其安置于经掺杂多晶硅沟槽的横向侧上且与主体区域接触；及源极触点沟槽(324)，其与源极区域且与经掺杂多晶硅沟槽接触。

Description

半导体装置及其制作方法
优先权主张及相关专利申请案
此非临时申请案主张基于以下先前美国临时专利申请案的优先权：(i)“运用共同漏极双源极结构来实现温度、电流监测连同电流感测集成而不添加除极低中间范围电压电力FET技术中的固有FET自身之外的任何更多组件(ENABLING TEMPERATURE,CURRENTMONITORING ALONG WITH CURRENT SENSING INTEGRATION WITHOUT ADDING ANY MORECOMPONENTS OTHER THAN INTRINSIC FET ITSELF IN EXTREMELY LOW MID-RANGE VOLTAGEPOWER FET TECHNOLOGY WITH COMMON DRAIN DUAL SOURCE STRUCTURE)”，申请案号为62/270,359，2015年12月21日提出申请；及(ii)“运用共同漏极双源极结构来实现温度、电流监测连同电流感测集成而不添加除极低中间范围电压电力FET技术中的固有FET自身之外的任何更多组件(ENABLING TEMPERATURE,CURRENT MONITORING ALONG WITH CURRENTSENSING INTEGRATION WITHOUT ADDING ANY MORE COMPONENTS OTHER THAN INTRINSICFET ITSELF IN EXTREMELY LOW MID-RANGE VOLTAGE POWER FET TECHNOLOGY WITHCOMMON DRAIN DUAL SOURCE STRUCTURE)”，申请案号为62/294,483，2016年2月12日提出申请；所述两个申请案以大卫·J·鲍德温(David J.Baldwin)、加里·尤金·多姆(GaryEugene Daum)、西蒙·约翰·莫洛伊(Simon John Molloy)及阿比德尔·拉赫曼(AbidurRahman)的名义提出申请，所述两个申请案特此以全文引用的方式并入。
技术领域
所揭示实施例一般来说涉及电力装置的领域。更明确地说且不以任何限制方式，本发明涉及具有集成传感器的电力场效应晶体管(FET)及制造方法。
背景技术
电力FET用于控制到负载的电力供应且经设计以在给定电压及电流范围内运行，在一个实例中，所述负载可为汽车中的各种灯及控制件。期望能够监测FET上的可致使装置发生故障或被损坏的各种状况。优选地，可在不添加装置的成本或不耗费装置上的大量有用有效面积的情况下监测这些状况。
发明内容
所揭示实施例实施利用垂直结构来实现低漏极电阻及高击穿电压两者的电力FET。温度感测、高度准确电流感测及高电流故障感测全部运用使用基于基本FET结构的变化形式的集成传感器而实现，从而允许在不添加工艺步骤或不需要额外掩模的情况下集成这些传感器。
在一个方面中，揭示半导体装置的一实施例。所述半导体装置包含：衬底，其包括半导体；电力场效应晶体管(FET)；集成感测FET，其测量与所述电力FET上的负载电流成比例的第一电流；集成高电流故障传感器，其测量跨越所述电力FET的漏极的电压；及集成温度传感器，其测量与所述电力FET的温度成比例的电压；其中所述电力FET具有第一结构，所述第一结构包括：第一导电性类型的漏极触点区域，其安置于所述衬底中；所述第一导电性类型的漏极漂移区域，其安置于所述漏极触点区域上方；经掺杂多晶硅沟槽，其安置于所述漏极漂移区域中；与所述第一导电性类型相反的第二导电性类型的主体区域，其安置于所述经掺杂多晶硅沟槽之间；源极区域，其安置于所述经掺杂多晶硅沟槽的横向侧上且与所述主体区域接触；及源极触点沟槽，其与所述源极区域且与所述经掺杂多晶硅沟槽接触。
在另一方面中，揭示形成半导体装置的方法的一实施例。所述方法包含：在半导体衬底上界定电力场效应晶体管(FET)区域、感测FET区域、温度传感器区域及高电流故障传感器区域；在所述半导体衬底中形成第一导电性类型的漏极触点区域且形成上覆在所述漏极触点区域上的所述第一导电性类型的漂移区域；在所述漂移区域中形成深沟槽经掺杂多晶硅区域；在除所述高电流故障区域之外的所有区域中形成主体区域，所述主体区域位于所述深沟槽经掺杂多晶硅区域之间；形成上覆在所述主体区域上的栅极；在所述栅极上形成侧壁间隔件；在相应栅极与深沟槽经掺杂多晶硅区域之间形成所述第一导电性类型的源极区域；及形成与所述源极区域且与所述深沟槽经掺杂多晶硅区域中的多晶硅层接触的源极触点沟槽且在所述半导体装置的表面上沉积金属化层，其中所述温度传感器区域中的栅极与源极短接在一起，且进一步地，其中所述高电流故障传感器区域中的栅极与漏极短接在一起。
附图说明
在附图中的各图中以实例方式且不以限制方式图解说明本发明的实施例，在附图中，相似元件符号指示类似元件。应注意，对本发明中的“一”或“一个”实施例的不同提及未必是对相同实施例的提及，且此等提及可意指至少一者。此外，当结合一实施例描述一特定特征、结构或特性时，应认为：无论是否明确描述，结合其它实施例实现此特征、结构或特性在所属领域的技术人员的知识范围内。
附图并入到本说明书中并形成本说明书的一部分以图解说明本发明的一或多个示范性实施例。从结合所附权利要求书且参考所附图式各图所做出的以下具体实施方式将理解本发明的各种优点及特征，在图式中：
图1A描绘根据本发明的实施例的电力FET及相关联控制器的实例性示意图；
图1B描绘根据本发明的实施例的双沟道共同漏极电力FET的实例性示意图；
图2A描绘含有图1B的双沟道共同漏极FET的半导体芯片；
图2B描绘图2A的半导体芯片的一个边缘的特写及识别沿下部FET的边缘的元件的示意图；
图3图解说明根据本发明的实施例的用于准确电流感测的集成感测FET的布局；
图4A图解说明根据本发明的实施例的集成温度传感器的示意图；
图4B图解说明根据本发明的实施例的集成温度传感器的布局；
图5A图解说明根据本发明的实施例的集成高电流故障模式传感器的示意图；
图5B图解说明根据本发明的实施例的集成高电流故障模式传感器的布局；
图5C图解说明根据本发明的实施例的跨越其的电压降由集成高电流故障模式传感器测量的电路；且
图6描绘根据本发明的实施例的形成电力FET及传感器的方法。
具体实施方式
现在将参考附图详细描述本发明的特定实施例。在本发明的实施例的以下详细说明中，陈述众多特定细节以提供对本发明的较透彻理解。然而，所属领域的技术人员将明了，可在不具有这些特定细节的情况下实践本发明。在其它例子中，未详细描述众所周知的特征以避免使本说明不必要地复杂化。
参考图1A，展示系统100A，所述系统向负载(未具体展示)提供受控制电力。电力FET 102是接收VIN及提供VOUT的控制电力供应的开关。电力FET 102用于在其中负载电流可在从约100毫安到约15安培的范围内变化且初始涌入电流可高达90安培的环境中工作。介于200安培到300安培的范围内的较高电流可指示其中应关闭电力FET 102的故障状况。为管理宽范围的负载电流，控制器104需要关于穿过电力FET 102的电流的极准确信息。能够准确地测量此宽范围的电流的传感器可无法检测更高故障状况。另外，由于高涌入电流，因此电力FET 102上的温度可极迅速地上升。为避免超过安全操作温度，需要监测此芯片上温度。
控制器104既负责管理电力FET 102对改变的负载状况的响应，且还负责监测可致使电力FET 102故障或被损坏的故障状况，例如前述高温及高电流故障状况。控制器104经连接以接收来自电力FET 102的传感器输入且还使用栅极信号106来控制电力FET 102的栅极。在此实施例中，控制器104接收关于温度108、负载电流110及电流故障状况112的信号。
图1B图解说明电路100B的示意图，在此实施例中，所述电路是双沟道共同漏极电力FET，例如单个芯片120上并排的两个电力FET。栅极接触垫122A、122B控制两个主要FET124A、124B及引导FET 130A、130B的栅极，主要FET 124A、124B在漏极垫DRN 126上接收VIN且在相应源极垫OUTSENX 128A、128B上提供VOUT，且引导FET 130A、130B在对应垫ISENX 132A、132B上提供对穿过每一相应FET的负载电流的准确测量。温度传感器134A、134B各自构建为FET，但具有彼此短接的源极及栅极；接着将所有FET中所形成的固有主体二极管用作温度传感器以在垫DX 136A、136B上提供温度数据。跨越电力FET 102的衬底的电压在垫DRNSENX138A、138B处进行测量且用于高电流故障检测。
图2A展示芯片200A的俯视图，所述芯片包含两个金属氧化物硅FET(MOSFET)及其相应引脚。所属领域的技术人员将认识到，名称MOSFET用于包含可利用除金属之外的导体、除氧化物之外的电介质及除经掺杂硅之外的半导体但遵循相同一般原理的技术。图2B展示此芯片的右手侧的放大形式及针对下部电力FET而阐释其上所展示的引脚的示意图。在这些图中，电力FET1占据芯片200A的上部半体且电力FET2占据芯片200A的下部半体。图2B的右侧的示意图图解说明电力FET2的接触垫，所述接触垫是电力FET1的接触垫的镜像。在此示意图中，可见，栅极垫引脚202最接近FET1与FET2之间的边界；源极引脚204是下一个，接着为来自引导FET的ISENX引脚206、供与高电流故障检测一起使用的DRNSENX 208及温度感测引脚DX 210。将理解，还可使用这些引脚的其它布置。
图3到5描绘根据本发明的实施例的穿过传感器中的每一者的横截面。注意，这些图的最右边边缘位于芯片的边缘处。图3描绘穿过引导FET 300的横截面，图3还图解说明主要FET的布局，这是因为引导FET 300是主要FET的按比例缩小的版本。在一个实施例中，主要FET与引导FET的比率为约5000:1。因此，虽然引导FET 300可含有此图中所图解说明的小数目个单元，但主要FET将具有成千上万个相同单元。控制器104接收引导FET 300的输出，且在知晓主要FET与引导FET之间的比率的情况下，借此能够在不从主要FET上的实际负载进行汲取的情况下确定主要FET正携载的电流。
漏极302形成于经重掺杂衬底中，所述经重掺杂衬底在本实例中为N++。将理解，所述实例揭示n型MOSFET，但p型MOSFET可通过反转各种区域的掺杂而形成。经轻掺杂外延层304形成漏极漂移区域，在所述漏极漂移区域中，形成有深沟槽306。深沟槽306内衬有内衬氧化物308且填充有经掺杂多晶硅310以形成减小邻近半导体区域(例如，漏极漂移区域)中的电场的降低表面场(RESURF)区域。N+源极区域312位于深沟槽306的一侧上，且P-主体区域314位于邻近源极区域312处。在所揭示实施例中，P+区域316位于邻近深沟槽306处且位于源极区域312下方。P+区域316允许从源极触点沟槽324到P-主体区域314的良好接触。如果P+区域316不提供到P-主体314的稳健连接且不提供低触点电阻(RC)，那么允许P-主体314浮动，此可允许接通寄生N-P-N双极晶体管(源极402到P-主体314到N-外延层304)。
可为WSiX/Poly结构的栅极318上覆在P-主体区域314上。栅极318具有电介质侧壁320，且层间电介质(ILD)322覆盖感测FET 300的不接收金属触点的那些表面。源极触点沟槽324内衬有导电势垒(例如，TiN势垒326)且填充有金属层328，所述金属层在所揭示实施例中为铝。源极触点沟槽324横向接触源极区域312且还接触深沟槽306中的多晶硅层310。引导FET是将与跨越电力FET的电流成比例的电流从漏极302传递到源极312的功能完善FET。
图4A到4B以示意图(400A)形成及以横截面(400B)形式图解说明温度传感器400。已知，二极管可用于感测由于其正向电压随温度的改变而发生的改变所致的温度，其中温度与所施加电压之间存在几乎线性关系。申请人已使用用以连接两个元件的源极金属系件410将晶体管400的源极402与栅极404短接在一起而非在本申请案中形成真实二极管。接着，使用形成于栅极404与漏极406之间的固有二极管408来监测电力FET 102中的温度。在布局400B中可见，除从栅极到源极的连接410之外，温度传感器400几乎等同于引导FET300。尽管此图中未明确看到，但将理解，共同控制栅极404且到单个栅极404的触点影响所有栅极404。使用因此形成的主体二极管，控制器104能够经由指示电力FET的温度的温度传感器400接收电压信息。
如先前所提及，尽管感测FET 300可用于检测正从电力MOSFET 102汲取的负载电流，但感测FET 300无法用于检测高得多的电流故障状况。替代地，申请人使用基于电力MOSFET 102的设计的另一变化形式来监测电流故障。
图5A到5B以示意图(500A)形成及以横截面(500B)形式两者图解说明高电流故障传感器500。高电流故障传感器500在两个方面不同于感测FET 300。首先，如示意图500A中可见，此传感器的栅极504与漏极506短接在一起。此短路在横截面500B中展示为漏极金属系件510。另外，在横截面500B中可见，高电流故障传感器500中缺少P-主体314。将理解，在不具有主体314的情况下，高电流故障传感器500不再操作为FET，而是可替代地用于确定跨越大漏极区域的电压降及其固有电阻。图5C图解说明衬底不充当单个集总感测电阻器，而是包含作为电阻器的三维硅衬底(在此申请案中，两个FET的共用漏极衬底)，可测量跨越所述电阻器的电压降。因此，高电流故障传感器500是给控制器104提供漏极电压感测的开尔文(Kelvin)连接引脚。由于控制器104将知晓跨越整个FET的衬底的电阻且可获得电压降，因此控制器104可使用V＝IR以简明方式确定电流。使用高电流故障传感器500，控制器104可极迅速地检测高电流故障状况且用于在可发生任何损坏之前关断FET 102。
公开为第2013/0193502号美国专利申请公开案(其以引用的方式并入本文中)的相关申请案具有与本申请案稍微不同的布局，但使用类似工艺来形成电力FET。公开案2013/0193502中提供完整工艺及对所述工艺中的不同阶段的图解，但本文中为方便起见仅提供缩短版本。图6揭示形成所揭示电力MOSFET装置的方法，所述所揭示电力MOSFET装置具有用以测量电流的集成引导FET、集成温度传感器及集成高电流故障传感器。
所述方法通过在半导体衬底上界定(605)电力FET区域、引导FET区域206、温度传感器区域210及高电流故障区域208而开始。从图2A可见，大部分半导体用作电力FET区域，其中小得多的面积经界定用于三个传感器区域。在一个实施例中，半导体衬底是硅晶片。漏极触点区域302形成(610)于半导体衬底中且具有第一导电性类型。在实例性实施例中，n型漏极触点区域形成于衬底的顶部表面下方。漏极触点区域可具有1×1018/cm3到1×1021/cm3的掺杂密度且可通过离子植入工艺或炉内扩散工艺形成于衬底的现有顶部表面处。
形成(615)上覆在漏极触点区域上且延伸到衬底的顶部表面的漂移区域304，所述漂移区域还具有第一导电性类型，例如N型。漂移区域可通过半导体材料在漏极触点区域上的外延生长而形成。漂移区域的厚度及掺杂密度可取决于MOSFET的操作电压。以下表1提供针对不同状况而设计的漂移区域的实例参数：
表1
漂移区域中的掺杂可在外延生长期间通过原位掺杂而形成或在热驱动操作期间通过离子植入及后续扩散而形成。
所述方法接下来在漂移区域中形成(620)深沟槽经掺杂多晶硅区域306，所述深沟槽经掺杂多晶硅区域可形成RESURF区域。此工艺可包含(例如)通过在衬底上方形成电介质材料层并使用光致抗蚀剂蚀刻掩模来图案化所述电介质材料层而在衬底上方形成沟槽蚀刻硬掩模。沟槽蚀刻硬掩模可包含20纳米到30纳米的经热生长二氧化硅以及200纳米到300纳米的经沉积二氧化硅。沟槽蚀刻硬掩模可使用反应离子蚀刻(RIE)工艺或使用缓冲含水氢氟酸的湿法蚀刻而图案化。通过移除沟槽蚀刻硬掩模所暴露的区中的外延材料而在漂移区域中形成深沟槽经掺杂多晶硅区域。深沟槽经掺杂多晶硅区域可为0.6微米到1.5微米宽，且间隔达1.5微米到3.5微米。经掺杂多晶硅沟槽的底部可比漏极触点区域高(例如)半微米到一微米。深沟槽经掺杂多晶硅区域可使用RIE工艺而形成，所述RIE工艺在沟槽的侧壁上形成聚合物同时蚀刻沟槽的底部，以维持几乎恒定沟槽宽度。随后可移除沟槽蚀刻硬掩模。
电介质材料沟槽衬里308形成于深沟槽经掺杂多晶硅区域中且还可延伸到在衬底的顶部表面上方。针对经设计以在30伏特下操作的中等电压MOSFET，沟槽衬里可包含(例如)50纳米的经热生长二氧化硅(其接触衬底)及200纳米的经沉积二氧化硅(其使用化学气相沉积(CVD)工艺而形成)。经设计以在200伏特下操作的中等电压MOSFET可具有拥有150纳米的经热生长二氧化硅(其接触衬底)及800纳米的CVD二氧化硅的沟槽衬里。
接着用导电材料填充深沟槽经掺杂多晶硅区域。在一个实施例中，此导电材料是通过在低压反应器内于介于580℃到650℃之间的温度下热分解硅烷气体而形成于深沟槽经掺杂多晶硅区域中的多晶硅310。或者，导电材料可包含通过在低压反应器内于低于580℃的温度下热分解硅烷气体而形成的非晶硅。N型掺杂剂(例如磷)或p型掺杂剂(例如硼)以8×1014/cm2到1×1016/cm2的剂量植入到多晶硅中。热驱动操作使掺杂剂扩散到深沟槽经掺杂多晶硅区域中的多晶硅中。替代地，在使用适当掺杂剂试剂的形成期间可将多晶硅掺杂达所要水平。随后可从深沟槽经掺杂多晶硅区域中的沟槽衬里的顶部表面移除不想要多晶硅，使得所述顶部表面与衬底的顶部表面大致共面或稍低于衬底的顶部表面。
一旦形成深沟槽经掺杂多晶硅区域，所述方法便在除高电流故障传感器区域之外的所有区域中形成(625)主体区域314。在一个实施例中，形成主体植入掩模以暴露栅极与深沟槽经掺杂多晶硅区域之间的区域。在实例性实施例中，P型掺杂剂(例如硼)以3×1013/cm2到2×1014/cm2的剂量植入到邻近于深沟槽经掺杂多晶硅区域的衬底中以形成主体所植入区域。主体植入掩模在植入p型掺杂剂之后被移除且可使用氧灰化、接着运用过氧化氢与硫酸的含水混合物进行湿法清除。热驱动工艺使p型掺杂剂扩散到主体所植入区域中并激活所述p型掺杂剂以形成主体区域。热驱动工艺可包含将衬底在1100℃下持续加热90分钟或等效条件，举例来说，在1125℃下持续加热50分钟或在1050℃下持续加热270分钟。
所述方法接着形成(630)上覆在主体区域上的栅极318。应注意，尽管未在高电流故障传感器区域中形成主体区域，但栅极形成于此区域中且上覆在其中通常已放置主体区域的区域上。在一个实施例中，形成栅极包含在衬底的顶部表面上形成栅极电介质层。在形成栅极电介质层之前可执行清除蚀刻(其可为使用稀氢氟酸的湿法蚀刻)以移除衬底上的任何不想要氧化物。针对经设计以在30伏特下操作的中等电压MOSFET，栅极电介质层可为80纳米到85纳米的经热生长二氧化硅，且针对经设计以在200伏特下操作的中等电压MOSFET，栅极电介质层可为540纳米到560纳米的经热生长二氧化硅。栅极电介质层可包含一或多个其它电介质材料(例如氮氧化硅或氧化铪)层。
以在栅极电介质层上方形成栅极材料层而继续栅极的形成。所述栅极材料层可包含100纳米到200纳米的多晶硅且还可包含多晶硅上的金属硅化物层，例如100纳米到200纳米的硅化钨。用于栅极材料层的其它材料在所揭示方法的范围内。帽盖电介质层可形成于栅极材料层上方。帽盖电介质层可包含通过等离子体增强化学气相沉积(PECVD)工艺而形成的50纳米到150纳米的二氧化硅。栅极蚀刻掩模形成于帽盖电介质层上方；栅极蚀刻掩模可包含光致抗蚀剂、抗反射层及/或硬掩模层。栅极蚀刻工艺从栅极材料层移除不想要材料以形成如各图中所展示的栅极。
接着在栅极上形成(635)侧壁间隔件318。所述侧壁间隔件可通过以下方式而形成：在半导体装置的现有顶部表面上方形成50纳米到100纳米厚的二氧化硅保形层，及使用各向异性蚀刻工艺(例如RIE工艺)将二氧化硅从水平表面移除。
在相应栅极与深沟槽经掺杂多晶硅区域之间形成(640)具有第一导电性类型的源极区域312。源极区域的形成可以在半导体装置的现有顶部表面上方运用小于100兆帕(MPa)的应力形成屏蔽氧化物层而开始。屏蔽氧化物层可包含使用PECVD工艺或低压化学气相沉积(LPCVD)工艺而形成的10纳米到30纳米的二氧化硅。
源极植入掩模形成于半导体装置上，且源极植入工艺将n型掺杂剂(例如磷及/或砷)植入到相应栅极与深沟槽经掺杂多晶硅区域之间的衬底中以形成源极所植入区域。源极植入工艺可包含以8×1014/cm2到1×1016/cm2的剂量及20keV到70keV的能量植入砷。随后，移除源极植入掩模。通过源极退火操作而扩散并激活源极所植入区域中的n型掺杂剂以形成n型源极区域。源极区域在栅极侧壁间隔件下方延伸。源极退火操作可包含在氮气环境中将衬底在1000℃下持续加热20分钟或等效退火条件，举例来说，在1050℃下持续加热5分钟或在975℃下持续加热40分钟。
形成(645)源极触点沟槽324。这些源极触点沟槽与源极区域且与深沟槽经掺杂多晶硅区域中的多晶硅层接触。在半导体装置的现有顶部表面上方形成层间电介质(ILD)层。所述ILD可包含(例如)使用PECVD工艺而形成的70纳米到200纳米的二氧化硅。在ILD上方形成源极触点蚀刻掩模。在一个实施例中，源极触点蚀刻掩模暴露沿深沟槽经掺杂多晶硅区域的区域及衬底的直接邻接深沟槽经掺杂多晶硅区域的部分。源极触点蚀刻工艺从ILD、衬底、沟槽衬里及深沟槽经掺杂多晶硅区域移除材料以形成源极触点沟槽。源极触点沟槽延伸到低于衬底的顶部表面200纳米到400纳米处且暴露源极触点沟槽的一侧上的源极区域并暴露源极触点沟槽的底部上的深沟槽经掺杂多晶硅区域。形成源极触点沟槽以暴露源极区域及深沟槽经掺杂多晶硅区域有利地减小MOSFET所需的面积。在源极触点蚀刻之后植入P+区域316，从而允许到P-主体314的低电阻触点。
在半导体装置的表面上沉积(650)金属化层328以形成触点金属堆叠。触点金属化工艺可以在半导体装置的现有顶部表面上形成接触源极区域及深沟槽经掺杂多晶硅区域的钛衬里而开始。钛衬里可为通过溅镀工艺而形成的25纳米到50纳米厚。使用反应性溅镀工艺在钛层上形成第一氮化钛层。第一氮化钛层180可为15纳米到30纳米厚。将钛层及第一氮化钛层加热(例如)到700℃到740℃持续20秒到60秒，以形成到源极区域及深沟槽经掺杂多晶硅区域的欧姆接触。
使用CVD工艺在第一氮化钛层上形成8纳米到15纳米厚的第二氮化钛层以提供保形层。使用反应性溅镀工艺在第二氮化钛层上形成15纳米到30纳米厚的第三氮化钛层。在触点金属堆叠上形成源极金属层，在一个实施例中，所述源极金属层为2微米到5微米的经溅镀铝。(例如)使用蚀刻掩模及反应离子蚀刻工艺而图案化源极金属层及触点金属堆叠。这些经组合金属化层将温度传感器区域中的栅极与源极短接在一起且还将高电流故障传感器区域中的栅极与漏极短接在一起。
所揭示实施例仅使用基于固有FET的变化形式而不具有其它额外组件，且可提供以下各项中的一或多者：
●在电力FET局部的温度传感器使用FET的主体二极管来获得真实峰值温度信息；
●高电流故障检测使用垂直漏极电阻作为传感器；
●准确电流感测电流；及
●小解决方案大小使用共同漏极结构以极低接通电阻(例如8mΩ)支持双沟道模式。
尽管已详细展示及描述各种实施例，但权利要求书不限于任何特定实施例或实例。上述具体实施方式中没有一者应视为暗示任何特定组件、元件、步骤、动作或功能是必要的，使得其必须包含于权利要求书的范围中。以单数形式对一元件的提及不打算意指“一个且仅一个”(除非明确陈述为如此)，而是指“一或多个”。所属领域的技术人员已知的上文所描述的实施例中的元件的所有结构及功能等效物以引用方式明确并入本文中且打算由本发明权利要求书囊括。因此，所属领域的技术人员将认识到，本文中所描述的示范性实施例可在下文所附权利要求书的精神及范围内以各种修改及变更形式实践。

Claims (16)

1.一种半导体装置，其包括：
衬底，其包括半导体；
电力场效应晶体管FET；
集成感测FET，其测量与所述电力FET上的负载电流成比例的第一电流；
集成高电流故障传感器，其测量跨越所述电力FET的漏极的电压；及
集成温度传感器，其测量与所述电力FET的温度成比例的电压；
其中所述电力FET具有第一结构，所述第一结构包括：
第一导电性类型的漏极触点区域，其安置于所述衬底中；
所述第一导电性类型的漏极漂移区域，其安置于所述漏极触点区域上方；
经掺杂多晶硅沟槽，其安置于所述漏极漂移区域中；
与所述第一导电性类型相反的第二导电性类型的主体区域，其安置于所述经掺杂多晶硅沟槽之间；
源极区域，其安置于所述经掺杂多晶硅沟槽的横向侧上且与所述主体区域接触；及
源极触点沟槽，其与所述源极区域且与所述经掺杂多晶硅沟槽接触。
2.根据权利要求1所述的半导体装置，其中所述集成高电流故障传感器包括不具有所述主体区域的所述第一结构，且进一步地，其中所述高电流故障传感器的栅极短接到所述漏极触点区域。
3.根据权利要求2所述的半导体装置，其中所述集成温度传感器包括所述第一结构，且进一步地，其中所述集成温度传感器的栅极与所述集成温度传感器的源极区域短接在一起。
4.根据权利要求3所述的半导体装置，其中所述集成感测FET具有所述第一结构及为所述电力FET的大小的一小部分的大小。
5.根据权利要求4所述的半导体装置，其中跨越所述电力FET的阻抗为约8毫欧姆。
6.根据权利要求5所述的半导体装置，其中所述经掺杂多晶硅沟槽包括内衬有电介质且填充有具有所述第二导电性类型的多晶硅的深沟槽。
7.根据权利要求6所述的半导体装置，其进一步包括所述第二导电性类型的经重掺杂区域，所述经重掺杂区域位于邻近所述经掺杂多晶硅沟槽处且由所述源极触点沟槽接触。
8.根据权利要求1所述的半导体装置，其中所述第一导电性类型为N型，且所述第二导电性类型为P型。
9.一种形成半导体装置的方法，其包括：
在半导体衬底上界定电力场效应晶体管FET区域、感测FET区域、温度传感器区域及高电流故障传感器区域；
在所述半导体衬底中形成第一导电性类型的漏极触点区域且形成上覆在所述漏极触点区域上的所述第一导电性类型的漂移区域；
在所述漂移区域中形成深沟槽经掺杂多晶硅区域；
在除所述高电流故障区域之外的所有区域中形成主体区域，所述主体区域位于所述深沟槽经掺杂多晶硅区域之间；
形成上覆在所述主体区域上的栅极；
在所述栅极上形成侧壁间隔件；
在相应栅极与深沟槽经掺杂多晶硅区域之间形成所述第一导电性类型的源极区域；及
形成与所述源极区域且与所述深沟槽经掺杂多晶硅区域中的多晶硅层接触的源极触点沟槽，且在所述半导体装置的表面上沉积金属化层，其中所述温度传感器区域中的栅极与源极短接在一起，且进一步地，其中所述高电流故障传感器区域中的栅极与漏极短接在一起。
10.根据权利要求9所述的形成半导体装置的方法，其中形成所述深沟槽经掺杂多晶硅区域包括：形成内衬于所述深沟槽经掺杂多晶硅区域的表面上的电介质层；及形成填充所述深沟槽经掺杂多晶硅区域的经掺杂多晶硅层。
11.根据权利要求10所述的形成半导体装置的方法，其中形成所述经掺杂多晶硅层包括：将掺杂剂植入到所述深沟槽经掺杂多晶硅区域中；及执行热驱动工艺以使所述掺杂剂扩散穿过所述深沟槽经掺杂多晶硅区域。
12.根据权利要求10所述的形成半导体装置的方法，其中形成所述相应主体区域包括：在所述半导体装置上形成主体植入掩模；以介于3×1013/cm2与2×1014/cm2之间的剂量将掺杂剂植入于所述漂移区域中；及执行热驱动工艺。
13.根据权利要求12所述的形成半导体装置的方法，其中形成所述栅极包括：在所述半导体的表面上形成栅极电介质层；形成上覆在所述栅极电介质层上的多晶硅层；形成上覆在所述多晶硅层上的帽盖电介质层；形成栅极蚀刻掩模；及蚀刻所述半导体装置以移除不想要材料。
14.根据权利要求13所述的形成半导体装置的方法，其中形成所述相应源极区域包括：在所述半导体装置上形成源极植入掩模；以介于8×1014/cm2与1×1016/cm2之间的剂量将掺杂剂植入于所述漂移区域中；及执行热驱动工艺。
15.根据权利要求14所述的形成半导体装置的方法，其中形成所述源极触点沟槽包括：在所述半导体装置的现有顶部表面上方形成层间电介质层；在所述层间电介质上方形成源极触点蚀刻掩模；及将源极触点沟槽蚀刻到比所述半导体装置的顶部表面低200纳米到400纳米之间的深度。
16.根据权利要求15所述的形成半导体装置的方法，其中形成所述源极触点沟槽进一步包括：在所述半导体装置的所述现有顶部表面上形成钛衬里；及在所述钛衬里上方形成源极金属层。
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