CN106935652B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN106935652B CN106935652B CN201611248267.8A CN201611248267A CN106935652B CN 106935652 B CN106935652 B CN 106935652B CN 201611248267 A CN201611248267 A CN 201611248267A CN 106935652 B CN106935652 B CN 106935652B
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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Abstract
一种半导体装置及其制造方法被揭露。半导体装置包括一基板、于基板之上的一隔离结构、于基板之上且突出于隔离结构的二鳍片以及于二鳍片上的一磊晶特征。磊晶特征包括二下部与一上部。二下部分别位于二鳍片上。上部位于二下部上,且连接二下部。上部具有与二下部不同的掺杂浓度。上部的一顶表面实质上平坦。
Description
技术领域
本揭露是关于一种半导体装置及其制造方法。
背景技术
半导体集成电路(Integrated circuit;IC)产业历经了快速的成长。集成电路材料及设计的技术进步已生产许多世代的IC,且每一世代都较前一代具有较小及更复杂的电路。在集成电路的演化中,功能密度(即每个晶片面积中交联装置的数目)普遍随着几何尺寸(即一次制程所能创造最小的组件(或线))的减小而增加。尺寸的缩小提供了诸多好处,例如产品效能以及降低成本。而尺寸的缩小亦增加了制程及生产的复杂性。
举例而言,随着半导体装置尺寸逐渐缩小,已采用磊晶(epi)半导体材料实现应变源/漏极(source/drain;S/D)特征(即应力源区域),以增强载子迁移率并改善装置性能。形成具有应力源区域的金氧半导体场效晶体管通常会磊晶成长硅(Si)以形成用于n型装置的凸起源/漏极特征,并且磊晶成长锗化硅,以形成用于p型装置的凸起源/漏极特征。针对这些源/漏极特征的形状、配置和材料的各种技术已经被实现,以进一步改善晶体管的装置性能。尽管现有源/漏极的形成方法已普遍足以达成预期的目标,然而这些装置与方法却无法完全满足各方面的所有需求。举例而言,随着晶体管的尺寸缩小,源/漏极的接触电阻已经成为电路性能中日益突出的因素。因此,具有降低的源/漏极接触电阻以令其能致使降低的功率消耗和更快的电路速度是被期待的。
发明内容
本揭露的一实施例的半导体装置包括一基板;于基板之上的一隔离结构;于基板之上且突出于隔离结构的二鳍片;以及于二鳍片上的一磊晶特征。磊晶特征包括二下部与一上部。二下部分别位于二鳍片上。上部位于二下部上。上部具有不同于二下部的掺杂浓度。上部的一表面实质上平坦。
本揭露的另一实施例包括一半导体装置包括一基板;于基板之上的一隔离结构;于基板之上且突出于隔离结构的二鳍片;以及于二鳍片上的一磊晶特征。磊晶特征包括二下部与一上部。二下部分别位于二鳍片上。上部位于二下部上,且物性连接二下部。上部的一顶表面实质上平坦,且实质上与基板的一顶表面平行。上部与二下部具有同型的掺杂剂,但有不同的掺杂浓度。
本揭露的又一实施例包括一种制造半导体装置的方法。提供一基板、一于基板之上的隔离结构,以及从基板延伸并穿过隔离结构的至少二鳍片。方法还包括蚀刻此至少二鳍片,从而形成至少两个沟槽。方法还包括在第一成长条件下于至少两个沟槽中成长第一磊晶特征,并在第一磊晶特征上成长第二磊晶特征。在第二磊晶特征达到目标临界尺寸之后,方法还包括在不同于第一成长条件的第二成长条件下成长第二磊晶特征。
附图说明
阅读以下详细叙述并搭配对应的附图,可了解本揭露的多个态样。应注意,根据业界中的标准做法,多个特征并非按比例绘制。事实上,多个特征的尺寸可任意增加或减少以利于讨论的清晰性。
图1A、图1B、图1C与图1D绘示了依据本揭露的各方面构建的不同实施例的半导体装置;
图2绘示了依据本揭露的各方面构建的形成半导体装置的方法的方块图;
图3绘示了依据图2实施例的方法在制造的中间步骤中的半导体装置的透视图。
图4A、图4B、图4C、图5A、图5B、图5C、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10与图11绘示了依据部分实施例根据图2的方法所形成的目标半导体装置的截面图。
具体实施方式
以下揭露提供众多不同的实施例或范例,用于实施本案提供的主要内容的不同特征。下文描述一特定范例的组件及配置以简化本揭露。当然,此范例仅为示意性,且并不拟定限制。举例而言,以下描述“第一特征形成在第二特征的上方或之上”,于实施例中可包括第一特征与第二特征直接接触,且亦可包括在第一特征与第二特征之间形成额外特征使得第一特征及第二特征无直接接触。此外,本揭露可在各范例中重复使用元件符号及/或字母。此重复的目的在于简化及厘清,且其自身并不规定所讨论的各实施例及/或配置之间的关系。并且,为使说明简化及明确,不同特征亦将任意地以不同尺度绘制。
此外,空间相对术语,诸如“下方(beneath)”、“以下(below)”、“下部(lower)”、“上方(above)”、“上部(upper)”等等在本文中用于简化描述,以描述如附图中所图示的一个元件或特征结构与另一元件或特征结构的关系。除了描绘图示的方位外,空间相对术语也包含元件在使用中或操作下的不同方位。举例而言,如果在附图中的装置被翻转,则被描述为“下方(beneath)”或“以下(below)”的其它元件或特征将会被转向为“上方(above)”的其它元件或特征。因此,示例性术语“以下(below)”可以包含上方和下方的方位。此装置可以其他方式定向(旋转90度或处于其他方位上),而本案中使用的空间相对描述词可相应地进行解释。
本揭露的各种实施例一般涉及了半导体装置及其形成方法。更具体而言,本揭露是关于在包括具有鳍状通道的场效晶体管(鳍状场效晶体管)的场效晶体管中形成凸起源/漏极特征。在部分实施例中,本揭露提供自多个磊晶特征合并的凸起源/漏极特征,且凸起源/漏极特征各提供一实质上平顶表面。此平坦的顶表面提供比多个并极的个别磊晶特征更大的接触面积。当源/漏极接点形成在凸起源/漏极特征上时,因着大的接触面积,平坦的顶表面有助于减小源/漏极接点的相应电阻。
图1A绘示了依据本揭露的各方面构建的不同实施例的半导体装置100。半导体装置100可以是集成电路的制程中所制造出的中介装置或其中的一部分,其可包括静态随机存取记忆体(static random access memory;SRAM)及/或其它逻辑电路,被动元件如电阻器、电容器和电感器,以及主动元件如p型场效晶体管(PFETs)、n型场效晶体管(NFETs)、鳍状场效晶体管、金氧半导体场效晶体管(metal-oxide semiconductor field effecttransistor;MOSFET)、互补金氧半导体(complementary metal-oxide semiconductor;CMOS)晶体管、双极型晶体管、高电压晶体管、高频晶体管、其它记忆元件及其组合。此外,各种实施例中的各种特征,包括晶体管、鳍片、栅极堆叠、装置区域以及其它特征,是被提供来用于简化与易于理解,且并不会对这些实施例中超出具体权利范围的任何装置的类型、任何装置的数量、任何区域的数量或者任何结构或区域的配置做出必要的限制。举例而言,相同的发明概念可以用于制造平面场效晶体管(field-effect transistor;FET)装置和多栅极场效晶体管装置。
请参照图1A,在本实施例中,半导体装置100包括一基板102、于基板102之上的隔离结构104以及于基板102之上且突出于隔离结构104的两个或多个鳍片106(图1A中所示的为两个)。此外,在本实施例中,半导体装置100包括磊晶特征122,其包括上部122U以及两个或更多的下部122L(图1A中所示的为两个)。下部122L设置在相应的鳍片106上方,并且至少部分被鳍状侧壁介电层110环绕。在本实施例中,沿着z方向(一鳍片高度方向),下部122L低于鳍状侧壁介电层110。下部122L通过上部122U而彼此物性连接。上部122U提供实质上平坦的顶表面124。在一实施例中,顶表面124实质上平行于基板102的顶表面102'。在各种实施例中,上部122U的底表面125可以是平坦的或非平坦的。下面将进一步描述半导体装置100的各种特征。
在本实施例中,基板102是硅基板。可变地,基板102可以包括另一元素半导体,诸如锗;含有碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟的化合物半导体;含有锗化硅、磷砷化镓、砷铟化铝、砷镓化铝、磷铟化镓、磷铟化镓和/或磷砷铟化镓的合金半导体;或其组合。在另一变化中,基板102是例如具有掩埋介电层的硅基绝缘体(silicon-on-insulator;SOI)。在实施例中,基板102包括用以形成主动装置的主动区域,例如p阱和n阱。
鳍片106可以是用于形成p型场效晶体管的p型鳍片或用于形成n型场效晶体管的n型鳍片。鳍片106可以包括与基板102实质上相同的半导体材料。虽图1A未示出,但鳍片106中的各者包括一通道区域与两个夹着通道区域的源/漏极区域。图1A示出了横越鳍片106的源/漏极区域的一而切割的半导体装置100的截面图。鳍片106通过隔离结构104而分离。隔离结构104可以包括氧化硅、氮化硅、氧氮化硅、氟化硅玻璃(fluorinated silica glass;FSG)、低介电系数介电材料及/或其它合适的绝缘材料。在部分实施例中,隔离结构104可以是浅沟槽隔离(shallow trench isolation;STI)特征。介电层110设置在隔离结构104之上,且与鳍片106的源/漏极区域相邻。介电层110至少部分地环绕下部122L。在一实施例中,介电层110包括氮化物,例如氮化硅、氮氧化硅或氮碳化硅。上部122U设置在介电层110和下部122L之上。
在一实施例中,下部122L和上部122U的各者包括掺杂有诸如磷(P)或砷(As)的n型掺杂剂的硅,用以形成n型场效晶体管装置。此外,上部122U包括一较下部122L高的n型掺杂剂的浓度。在一实例中,上部122U包括硅掺杂有一浓度范围自每立方厘米1e21至每立方厘米5e21的磷,而下部122L包括硅掺杂有一浓度范围自每立方厘米1e20至每立方厘米1e21的磷。在另一实施例中,下部122L和上部122U的各者包括掺杂有诸如硼(B)或铟(In)的p型掺杂剂的锗化硅,用以形成p型场效晶体管装置。在进一步的实施例中,上部122U包括一较下部122L高的p型掺杂剂的浓度。
请参照图1B,在一实施例中,半导体装置100还包括在磊晶特征122上形成的一接触特征126。具体而言,接触特征126设置在平顶表面124上。在实施例中,接触特征126可以包括一阻障层126a和一在阻障层126a上的导电层126b。举例而言,导电层126b可以包括铝、钨、铜、钴、其组合或其它合适的材料;并且阻障层126a可以包括诸如氮化钽的金属氮化物,用以防止导电层126b的金属元素迁移到相邻的特征。在各种实施例中,与传统的结构相比,接触特征126和磊晶特征122之间的接面提供减小的电阻。传统的磊晶特征通常具有类似菱形的截面轮廓,并且不是彼此隔离(未合并),就是合并成具有带有脊和谷的非平顶表面的形状。在具有传统磊晶特征的许多情况下,只有磊晶特征的部分顶表面(例如脊)与之上的接触特征直接相接。相较之下,磊晶特征122的顶表面124实质上是平坦的,能与接触特征126提供比传统磊晶特征更大的接面。
请参照图1C,在另一实施例中,半导体装置100包括区域102a和相邻区域102b。区域102a包括上述的各种特征(即鳍片106和磊晶特征122)。区域102b包括鳍片146和在鳍片146上的磊晶特征152。磊晶特征152包括下部152L和在下部152L上的上部152U。介电层110至少部分地环绕下部152L。在本实施例中,沿着z方向,下部152L低于鳍状侧壁介电层110。上部152U设置在介电层110上。此外,在本实施例中,半导体装置100包括与磊晶特征122和152两者相接的接触特征128。接触特征128包括阻障层128a和在阻障层128a上的导电层128b。阻障层128a和导电层128b可以分别具有与阻障层126a和导电层126b相同或相似的组成。在所示的此实施例中,磊晶特征152具有菱形的截面轮廓,且接触特征128的一部分设置在磊晶特征152的一侧之上。特别是,在此实施例中,接触特征128的一部分设置在磊晶特征122的上部122U和磊晶特征152的上部152U之间以及磊晶特征122的上部122U及/或磊晶特征152的上部152U的最宽部分(沿着x方向)之下。在另一实施例中,区域102b可以包括形状类似于磊晶特征122的磊晶特征,即具有可以在其上设置接触特征128的实质上的平坦顶表面。在一实施例中,在区域102a中的特征形成n型晶体管(如n型金氧半导体),并且在区域102b中的特征形成p型晶体管(如p型金氧半导体)。在变化实施例中,区域102a中的特征形成p型晶体管(如p型金氧半导体),并且区域102b中的特征形成n型晶体管(如n型金氧半导体)。
请参照图1D,绘示了在另一实施例中的半导体装置100的各种尺寸,特别是磊晶特征122。图1D中的上部122U的形状接近一矩形长条:其顶表面和底表面都是平坦的或几乎平坦的。在两个实施例(图1C和图1D)中的上部122U之间的差异的一是它们的侧表面。图1C的上部122U具有面向上和向下的倾斜侧表面,而图1D的上部122U具有接近垂直的侧表面。在两个实施例(图1C和图1D)中的上部122U之间的另一差异是它们的底表面。图1C的上部122U具有面向下的倾斜底表面,而图1D的上部122U具有接近平坦(水平)的底表面。在图1D所示的实施例中,鳍片106沿着鳍片宽度方向(“x”方向)具有一鳍片节距p。鳍片节距p也是下部122L的节距。在实施例中,鳍片节距p被调节用于制程节点,并且在磊晶特征122中形成平坦顶表面124。如果鳍片节距p太小,上部122U可能在磊晶成长过程中过早融合,以致成长成菱形,而不是具有平顶表面的形状。如果鳍片节距p太大,上部122U可能根本不会合并。在一个例子中,鳍片节距p被调整为在从30纳米(nm)到50纳米的范围内。
在如图1A和图1D所示的各种实施例中,上部122U沿着x方向延伸超过下部122L和鳍片106。上部122U具有沿着x方向的尺寸b和沿着鳍片高度方向(z方向)的尺寸h。在实施例中,尺寸b大于尺寸h。举例而言,尺寸b的范围自55纳米到75纳米。此外,上部122U延伸超过下部122L(以及两个鳍片106)的左侧和右侧的部分可以是不对称的。在图1D所示的实施例中,上部122U延伸超过下部122L的左侧的尺寸为b1,右侧的尺寸为b2。在部分实施例中,尺寸b1和尺寸b2之中的各者的范围可以介于10纳米至25纳米之间。
请继续参照图1D,在各种实施例中,介电层110沿着z方向具有高度d,并且高度d的范围可以介于5纳米到25纳米之间。如下面将讨论的,高度d对磊晶特征122的各种形状和尺寸有所贡献。下部122L各自具有沿x方向的宽度c,在下部122L的近半高度处所测。在部分实施例中,宽度c的范围可以介于6纳米到15纳米。此外,下部122L各自具有沿z方向的高度e。在部分实施例中,高度e的范围可以从3纳米到15纳米。在部分实施例中,导电层128b具有一宽度g,其范围可以介于约100纳米至约250纳米之间。导电层128b在其顶部可以比在其底部更宽(即梯形)。导电层128b的一下部自阻障层128a的顶表面向下延伸。此下部设置在磊晶特征122的上部122U和磊晶特征152的上部152U之间,且在部分实施例中,其范围自20至50纳米的深度f(沿着z方向)。由于导电层128b的此下部的存在,进一步扩大了接触特征128和磊晶特征之间的接面。
图2绘示了依据本揭露的各方面构建的形成半导体装置诸如半导体装置100)的方法200的方块图。方法200是一个例子,并且不用以限制本揭露所超出的权利要求书中明确记载的内容。额外的操作可在方法200的之前、期间以及之后时提供,并且,所述的一些操作在此方法的其他实施例中可以被取代、消除或重置。方法200结合依据本揭露的各个方面的半导体装置100的透视图和截面图的图3至图11在下面进行叙述。
在操作步骤202中,方法200(图2)接收半导体装置100的前体。为了方便讨论,半导体装置100的前体也称为半导体装置100。图3绘示了半导体装置100的透视图。图4A、图4B与图4C分别绘示了沿着图3中的“1—1”、“2—2”和“3—3”线的半导体装置100的截面图。“1-1”线于xz平面上切割在鳍片106的源/漏极区域中的半导体装置100。“2-2”线沿着鳍片106的一长度,于yz平面上切割半导体装置100。“3-3”线于yz平面上切割在鳍片106外部的半导体装置100。
请参照图3、图4A、图4B与图4C,半导体装置100包括基板102、于基板102之上的隔离结构104与自基板102延伸并穿过隔离结构104的两个鳍片106。两个鳍片106各自具有源/漏极区106a和插入源/漏极区106a的通道区106b。半导体装置100还包括接合通道区域106b中的鳍片106的栅极堆叠108。特别是,栅极堆叠108在其多个侧面上接合鳍片106,其形成多栅极装置(在这种情况下为鳍状场效晶体管)。
鳍片106可以使用包括微影和蚀刻制程的合适制程来制造。微影制程可以包括形成覆盖基板102的光阻层(抗蚀剂),将抗蚀剂暴露于一图案,执行曝光后烘烤的制程,以及成长抗蚀剂以形成包括抗蚀剂的遮罩元件。然后,遮罩元件用于将凹陷蚀刻到基板102中,而在基板102上留下鳍片106。蚀刻制程可以包括湿式蚀刻、干式蚀刻、反应离子蚀刻(reactive ion etching;RIE)及/或其他合适的制程。举例而言,干式蚀刻制程可以含氧气体、含氟气体(如四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及/或乙氟烷(C2F6))、含氯气体(如氯气(Cl2)、氯仿(CHCl3)、四氯化碳(CCl4)及/或三氯化硼(BCl3))、含溴气体(例如氢溴酸(HBr)及/或三溴甲烷(CHBr3))、含碘气体、其它适合的气体及/或电浆,及/或其组合来执行。举例而言,湿式蚀刻制程可以包括在稀释的氢氟酸(DHF)、氢氧化钾(KOH)溶液、氨、含有氢氟酸(HF)、硝酸(HNO3)、及/或乙酸(CH3COOH)的溶液、或其它适合的湿蚀刻剂中蚀刻。鳍片106还可以使用双图案化微影(double-patterninglithography;DPL)制程形成。有许多形成鳍片106的其它实施例的方法可以是合适的。
隔离结构104可以通过蚀刻基板102中的沟槽而形成,即作为鳍片106形成制程的一部分。然后可以用隔离材料填充沟槽,接着进行化学机械研磨(chemical mechanicalpolishing;CMP)。其它隔离结构例如场氧化物、局部硅氧化技术(LOCal Oxidation ofSilicon;LOCOS)及/或其它合适的结构是可能的。隔离结构104可以包括多层结构,例如,具有一个或多个热氧化物衬层。
栅极堆叠108包括栅极介电层和栅极电极层。栅极介电层可以包括氧化硅或高介电系数介电质材料诸如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇和钛酸锶。栅极介电层可以通过化学氧化、热氧化、原子层沉积(atomic layer deposition;ALD)、化学气相沉积(chemical vapor deposition;CVD)和/或其他合适的方法形成。在一实施例中,栅极电极层包括多晶硅,并且可以通过诸如低压化学气相沉积(low-pressure chemical vapordeposition;LPCVD)和等离子体增强化学气相沉积(plasma-enhanced chemical vapordeposition;PECVD)的合适沉积制程形成。在部分实施例中,栅极电极层包括n型或p型功函数层和金属填充层。举例而言,n型功函数层可以包括具有足够低的有效功函数的金属,例如钛、铝、碳化钽、氮碳化钽、氮硅化钽或其组合。举例而言,p型功函数层可以包括具有足够大的有效功函数的金属,例如氮化钛,氮化钽、钌、钼、钨、铂或其组合。举例而言,金属填充层可以包括铝、钨、钴、铜及/或其它合适的材料。栅极电极层可以通过化学气相沉积、物理气相沉积、电镀及/或其它合适的制程形成。在部分实施例中,栅极堆叠108是牺牲栅极结构,即用于最后栅极堆叠的占位。在部分实施例中,栅极堆叠108包括其栅极介电层与鳍片106之间的介面层。介面层可包括介电材料,例如氧化硅或氮氧化硅,且可通过化学氧化、热氧化、原子层沉积、化学气相沉积及/或其它合适的制程而形成。栅极堆叠108可包括其它层,例如硬遮罩层。
在操作步骤204中,方法200(图2)在相应源/漏极区106a中的鳍片106的侧壁上形成介电层110。图5A、图5B与图5C分别绘示了在沿着图3中的“1—1”、“2—2”和“3—3”线的半导体装置100在这步骤之后的截面图。请参照图5A、图5B与图5C,介电层110可以包括单层或多层结构,并且可以包括诸如氮化硅(SiN)或氮氧化硅的介电质材料。介电层110可以通过化学气相沉积、等离子体增强化学气相沉积、原子层沉积、热沉积或其他合适的方法形成。在本实施例中,介电层110也设置在栅极堆叠108的侧壁上。在一实施例中,操作步骤204包括沉积制程,而随后是蚀刻制程。举例而言,其可以在半导体装置100上沉积介电材料作为毯覆层,覆盖隔离结构104、鳍片106和栅极堆叠108。然后,其可以执行各异向性蚀刻制程以移除部分来自隔离结构104、鳍片106和栅极堆叠108的顶表面的介电质材料,而留下栅极堆叠108与鳍片106的侧壁上的介电质材料剩余部分来作为介电层110。在实施例中,在鳍片106的侧壁上的介电层110具有大约5至25纳米的高度。
在操作步骤206中,方法200(图2)选择性地蚀刻鳍片106的源/漏极区106a,以在其中形成一个或多个沟槽(或凹陷)114。图6A与图6B分别绘示了在沿着图3中的“1—1”、“2—2”和“3—3”线的半导体装置100在这制造步骤之后的截面图。请参照图6A与图6B,在本实施例中,鳍片106在隔离结构104的一顶表面下被蚀刻。操作步骤206可以包括一个或多个微影制程和蚀刻制程。举例而言,微影制程可以形成覆盖半导体装置100的不倾向被蚀刻的区域的遮罩元件。遮罩元件提供开口,鳍片106通过其开口而被蚀刻。鳍片106可以通过干式蚀刻制程、湿式蚀刻制程或其他蚀刻技术来蚀刻。在本实施例中,蚀刻制程被选择性地调整以移除鳍片106的材料,而栅极堆叠108、介电层110和隔离结构104实质上保持不变。操作步骤206形成四个沟槽114,以在栅极堆叠108的各侧上形成两个的形式。各沟槽114可具有锥形截面轮廓(在xz平面中),其具有在其底部比在其顶部更宽的开口。在蚀刻制程之后,一清洁制程可以执行,其用清洁化学品清洁沟槽114,以使其中的各个表面能预备好用于随后的磊晶成长制程。清洁化学品可以是氢氟酸(hydrofluoric acid;HF)溶液、稀释的氢氟酸溶液或其他合适的清洁溶液。
在操作步骤208中,方法200(图2)在四个沟槽114中成长四个磊晶特征122L(即上文所述的磊晶特征122的下部122L的前身,为了方便讨论,也称为磊晶特征122L),以在各沟槽中具有一个(图7A与图7B)的形式。磊晶特征122L部分地填充相应的沟槽114。磊晶成长制程可以是具有硅基前体、选择性磊晶成长(selective epitaxial growth;SEG)制程或循环沉积和蚀刻(cyclic deposition and etching;CDE)制程的低压化学气相沉积制程。举例而言,硅晶体可以用低压化学气相沉积制程,以二氯硅烷(SiH2Cl2)作为前体生长。再举另一例而言,锗化硅晶体可以使用盐酸作为蚀刻气体以及四氢化锗(锗烷)和氢气的气体混合物来作为循环沉积和蚀刻制成的沉积气体来形成,其在氢气中包含约1%至约10%的四氢化锗。介电层110的高度被调整以促进磊晶特征122L的成长到期望的高度,而不具太多的横向成长。在各种实施例中,磊晶特征122L被成长为具有一高度,其范围自3纳米到15纳米之间。磊晶特征122L包括适于形成凸起源/漏极特征的半导体材料。在一实施例中,磊晶特征122L包括掺杂有一种或多种p型掺杂剂(例如硼或铟)的锗化硅。在一实施例中,磊晶特征122L包括掺杂有一种或多种n型掺杂剂(例如磷或砷)的硅。此掺杂可以利用临场掺杂或非临场掺杂的磊晶成长制程进行。
在操作步骤210中,方法200(图2)在磊晶特征122L上方成长磊晶特征122U(即上文所述的磊晶特征122的上部122U的前身,为了方便讨论,也称为磊晶特征122U)。在本实施例中,磊晶特征122U是用与磊晶特征122L相同的半导体材料生长,但掺杂剂浓度不同。举例而言,磊晶特征122L和122U可以各自包括掺杂有n型掺杂剂的硅,而磊晶特征122U具有更高的n型掺杂剂浓度。再举例而言,磊晶特征122L和122U可以各自包括掺杂有p型掺杂剂的锗化硅,但磊晶特征122U具有更高的p型掺杂剂浓度。类似于磊晶特征122L的形成,磊晶特征122U可以使用低压化学气相沉积制程、选择性磊晶成长制程或循环沉积和蚀刻制程的技术形成。
如图8A与图8B所示,磊晶特征122U填充在相应的沟槽114中的剩余空间中,并且,一旦它们从相应的沟槽114伸出,就进一步横向扩展。随着磊晶特征122U变得更高和更宽,它们开始合并。如图8A所示,其是沿着图3中的“1—1”线的半导体装置100的截面图。图8B绘示了沿着图3中的“2—2”线的半导体装置100在这步骤的截面图。请参照图8A,磊晶特征122U合并为一连接的磊晶特征,为了方便讨论,也称其为磊晶特征122U。此外,在此制造阶段,磊晶特征122U尚未具有平顶表面。反而,其具有带有一凹陷116的曲顶表面115。本揭露的发明人已经发现,在相同的磊晶成长条件下,持续成长磊晶特征122U可能不会导致其具有平顶表面。
在操作步骤212中,方法200(图2)改变磊晶特征122U的成长条件,并且持续生长磊晶特征122U以具有实质上平坦的顶表面124,如图9A所示,其是沿着图3中的“1—1”线的半导体装置100的截面图。图9B绘示了沿着图3中的“2—2”线的半导体装置100在这步骤的截面图。在一实施例中,当个别磊晶特征122U开始合并且合并磊晶特征122U达到目标临界尺寸(CD)时,方法200从操作步骤210切换至操作步骤212。举例而言,当其尺寸b(图1D)达到一定值(如,节距p的至少1.5倍),或者当其在凹陷116的底部处的厚度h1达到某一值(如图8A所示),例如自期望尺寸h的1/4到1/3。在一实施例中,当h1为大约5到10纳米时,方法200从操作步骤210切换到操作步骤212。
在一实施例中,操作步骤212使用与操作步骤210不同的沉积前体或不同的蚀刻气体。在另一实施例中,操作步骤212使用与操作步骤210(在类型或数量上)不同的蚀刻气体,但使用相同的沉积前驱物。不同的沉积前体或蚀刻气体导致在凹陷116(图8A)中的晶体生长(或沉积)比在磊晶特征122U的其他区域中更多的晶体生长(或沉积)。换句话说,虽然半导体材料也在磊晶特征122U的侧表面和底表面上生长(或沉积),但是其顶表面115上的生长(或沉积)要快得多。如此,凹陷116被相应的半导体材料(例如,硅或锗化硅)填充,并且磊晶特征122U被成长为具有实质上平坦的顶表面124。
在一实施例中,操作步骤210使用二氯硅烷(dichlorosilane;SiH2Cl2,也称为DCS)作为前体成长磊晶特征122U以形成硅晶体。为了进一步描述实施例,操作步骤212向前体中添加硅烷,以便在凹陷116中具有较高的生长(或沉积)速率。在一实施例中,硅烷是SiH4。在一实施例中,操作步骤212中硅烷与二氯硅烷的比率在约0.005至约0.05的范围内。在另一实施例中,操作步骤210使用盐酸作为蚀刻气体以及四氢化锗和氢气的气体混合物作为沉积气体来成长磊晶特征122U,以形成锗化硅晶体。为了进一步描述实施例,操作步骤212减少盐酸的流速,使得锗化硅在凹陷116中比在磊晶特征122U的其他区域更快地沉积。在一实施例中,操作步骤212中的盐酸流速范围为每分钟自约100至约400标准立方厘米(sccm)。通过操作步骤208、210和212,半导体装置100设置有具有实质上平坦的顶表面124的凸起源极/漏极特征122。在各种实施例中,操作步骤210和212可以是在自200至350托的压力下和在自650至720℃的温度下执行。
在操作步骤214中,方法200(图2)进行到进一步的操作步骤以形成最后的装置。这包括各种过程。在一个例子中,硅化物或锗硅化物会形成在磊晶特征122U上。举例而言,硅化物,如硅化镍,可以通过在磊晶特征122U上沉积金属层,对金属层进行退火,使得金属层与磊晶特征122U中的硅反应以形成金属硅化,且其后除去未反应的金属层,而形成。
在另一例子中,操作步骤214用最后的栅极堆叠108a代替栅极堆叠108,如图10所示。为了进一步描述此例子,栅极堆叠108是具有虚设栅极介电层(如氧化硅)和虚设栅极电极层(如多晶硅)的占位,而栅极堆叠108a是具有一高介电系数栅极介电层、一适当的n型或p型功函数层和一金属填充层的高介电系数金属栅极。高介电系数栅极介电层、功函数层和金属填充层可以使用参照图3所述的合适材料。为了进一步描述此例子,操作步骤214可以在基板102上沉积低介电系数介电层130以覆盖其上的形貌。介电层130可以包括诸如四乙氧基硅烷(tetraethylorthosilicate;TEOS)氧化物、掺杂或未掺杂的硅酸盐玻璃、熔融石英玻璃(FSG)和/或其它合适的介电质材料的材料。介电层130可以通过等离子体增强化学气相沉积制程,可流动化学气相沉积制程(FCVD)或其他合适的沉积技术来沉积。在部分实施例中,一具有诸如氮化硅的介电质材料的接触蚀刻停止层(未示出)可以被沉积在低介电系数介电层130下方。在已经沉积了介电层130之后,操作步骤214移除栅极堆叠108,且使用一个或一个以上的沉积制程形成最后的栅极堆叠108a以代替栅极堆叠108。
在另一例子中,操作步骤214在磊晶特征122U上形成源/漏极接触特征126或128,并且电性连接到磊晶特征122U,如图11所示。这包括各种过程。举例而言,操作步骤214可以执行一个或多个微影制程和蚀刻制程以形成穿过介电层130的接触孔。接触孔暴露磊晶特征122U(或其上的硅化物或锗硅化物)。在一实施例中,接触孔在磊晶特征122U的最宽部分下方延伸,如图1C和图1D所示。之后,操作步骤214在接触孔的底部和侧壁上沉积阻障层(如126a或128a),以防止源/漏极接触特征126或128的金属材料扩散到相邻特征中。阻障层包括介电材料,例如在一个例子中的氮化钽。随后,操作步骤214沉积金属层(如126b或128b)以填充接触孔中的剩余空间。在本实施例中,源/漏极接触特征126或128包括阻障层和金属层。阻障层和金属层的沉积可以使用共形或非共形的沉积制程。在这两种情况下,源/漏极接触特征126或128与下面的磊晶特征122U之间的大的介面导致了磊晶特征122U的实质上平坦的顶表面124。此一大的介面有利地降低了源/漏极接触电阻。
尽管不意欲对此进行限制,本揭露的一或多个实施例为半导体装置及其形成提供了许多益处。例如,凸起源/漏极特征可以成长为具有实质上平坦的顶表面。实质上平坦的顶表面在源/漏极特征和设置在其上的源极/漏极接触之间提供大的界面。大界面可以用共形或非共形的源/漏极接触沉积来实现,而简化了制造制程。在本揭露的实施例中,源/漏极特征的几何形状可以通过在某个制造阶段改变磊晶成长条件来调整。本揭露的各种实施例可以容易地整合到现有的制造制程中。
本揭露的一实施方式包括一半导体装置。半导体装置包括一基板;于基板之上的一隔离结构;于基板之上且突出于隔离结构的二鳍片;以及于二鳍片上的一磊晶特征。磊晶特征包括二下部与一上部。二下部分别位于二鳍片上。上部位于二下部上。上部具有不同于二下部的掺杂浓度。上部的一顶表面实质上平坦。
在一实施例中,上述的上部沿着一鳍片宽度方向的一第一尺寸大于上部沿着一鳍片高度方向的一第二尺寸。
在一实施例中,上述的上部沿着鳍片宽度方向延伸超过二下部,并且上部到二下部的左侧和右侧的延伸部具有不同的厚度。
在一实施例中,上述的磊晶特征包括具有一n型掺杂剂的硅。
在一实施例中,上述的上部具有一较二下部高的n型掺杂剂的浓度。
在一实施例中,上述的二鳍片具有一插入二源/漏极区域的通道区域,且磊晶特征位于二源/漏极区域的一上,半导体装置还包括一于隔离结构之上的栅极堆叠,以及接合二鳍片的通道区域。
在一实施例中,上述的半导体装置还包括一于基板之上与二鳍片的侧壁上的介电层,其中磊晶特征的二下部至少部分被介电层环绕。
在一实施例中,上述的半导体装置还包括一于顶表面的磊晶特征上的接触特征,且其电性连接至磊晶特征。
在一实施例中,上述的半导体装置还包括于基板之上且突出于隔离结构的一第三鳍片以及于第三鳍片上的另一磊晶特征。磊晶特征与另一磊晶特征包括不同的半导体材料;以及接触特征位于另一磊晶特征的一表面上,且电性连接至另一磊晶特征。
在一实施例中,上述的磊晶特征包括n型掺杂硅,且另一磊晶特征包括p型掺杂锗化硅。
本揭露的另一实施方式包括一半导体装置。半导体装置包括一基板;于基板之上的一隔离结构;于基板之上且突出于隔离结构的二鳍片;以及于二鳍片上的一磊晶特征。磊晶特征包括二下部与一上部。二下部分别位于二鳍片上。上部位于二下部上,且物性连接二下部。上部的一顶表面实质上平坦,且实质上与基板的一顶表面平行。上部与二下部具有同型的掺杂剂,但有不同的掺杂浓度。
在一实施例中,上述的二鳍片具有一范围介于30纳米至50纳米的间距,且上部沿一鳍片宽度方向的一尺寸范围介于55纳米至75纳米。
在一实施例中,上述的下部包括具有一n型掺杂剂的一第一浓度的硅,上部包括具有n型掺杂剂的一第二浓度的硅,且第二浓度高于第一浓度。
本揭露的又一实施方式包括一种制造半导体装置的方法。此方法包括提供一基板、一于基板之上的隔离结构,以及从基板延伸并穿过隔离结构的至少二鳍片。方法还包括蚀刻此至少二鳍片,从而形成至少两个沟槽。方法还包括于在至少两个沟槽中成长第一磊晶特征,并在第一成长条件下于第一磊晶特征上成长第二磊晶特征。在第二磊晶特征达到目标临界尺寸之后,方法还包括在不同于第一成长条件的第二成长条件下成长第二磊晶特征。
在一实施例中,上述的第二磊晶特征包括硅,第一成长条件使用具有二氯硅烷(SiH2Cl2)的第一前体,且第二成长条件使用第一前体和硅烷。
在一实施例中,上述的硅烷是四氢化硅(SiH4)。
在一实施例中,上述的第二磊晶特征包括硅,第二成长条件使用比第一成长条件少的盐酸。
在一实施例中,上述的方法还包括以一第一掺杂剂将第一磊晶特征掺杂至一第一掺杂浓度以及以第一掺杂剂将第二磊晶特征掺杂至高于第一掺杂浓度的一第二掺杂浓度。
在一实施例中,上述的方法还包括在蚀刻至少二鳍片之前,在至少二鳍片的侧壁部分上形成一介电层,其中第一磊晶特征至少部分被介电层环绕。
在一实施例中,上述的第二磊晶特征被成长为具有一实质上平坦的顶表面,且方法还包括于实质上平坦的顶表面上形成接触特征。
上文概述了若干实施例的特征,以便本领域熟悉此项技艺者可更好地理解本揭露的态样。本领域熟悉此项技艺者应当了解到他们可容易地使用本揭露作为基础来设计或者修改其他制程及结构,以实行相同目的及/或实现相同优势的。本领域熟悉此项技艺者亦应当了解到,此类等效构造不脱离本揭露的精神及范畴,以及在不脱离本揭露的精神及范畴的情况下,其可对本文进行各种改变、取代及变更。
Claims (20)
1.一种半导体装置,其特征在于,包括:
一基板;
一隔离结构,于所述基板之上;
二鳍片,于所述基板之上,且突出于所述隔离结构;
一磊晶特征,于所述二鳍片上;以及
一鳍状侧壁介电层,于所述基板之上与所述二鳍片的侧壁上,
其中:
所述磊晶特征包括二下部与一上部;
所述二下部分别位于所述二鳍片上;
所述上部位于所述二下部上;
一部分的所述二下部的一者横向位于所述鳍状侧壁介电层及所述上部之间;
所述上部具有不同于所述二下部的掺杂浓度;以及
所述上部的一顶表面实质上平坦。
2.根据权利要求1所述的半导体装置,其特征在于,所述上部沿着一鳍片宽度方向的一第一尺寸大于所述上部沿着一鳍片高度方向的一第二尺寸。
3.根据权利要求1所述的半导体装置,其特征在于,所述上部沿着所述鳍片宽度方向延伸超过所述二下部,并且所述上部到所述二下部的左侧和右侧的延伸部具有不同的厚度。
4.根据权利要求1所述的半导体装置,其特征在于,所述磊晶特征包括具有一n型掺杂剂的硅。
5.根据权利要求4所述的半导体装置,其特征在于,所述上部具有一较所述二下部高的n型掺杂剂的浓度。
6.根据权利要求1所述的半导体装置,其特征在于,所述二鳍片具有一插入二源/漏极区域的通道区域,且所述磊晶特征位于所述二源/漏极区域之一上,所述半导体装置还包括一于所述隔离结构之上的栅极堆叠,以及接合所述二鳍片的通道区域。
7.根据权利要求1所述的半导体装置,其特征在于,所述磊晶特征的所述二下部至少部分被所述鳍状侧壁介电层环绕。
8.根据权利要求1所述的半导体装置,其特征在于,还包括一于所述顶表面的磊晶特征上的接触特征,且其电性连接至所述磊晶特征。
9.根据权利要求8所述的半导体装置,其特征在于,还包括:
一第三鳍片于所述基板之上,且突出于所述隔离结构;以及
另一磊晶特征,于所述第三鳍片上,其中:
所述磊晶特征与所述另一磊晶特征包括不同的半导体材料;以及
所述接触特征位于所述另一磊晶特征的一表面上,且电性连接至所述另一磊晶特征。
10.根据权利要求9所述的半导体装置,其特征在于,所述磊晶特征包括n型掺杂硅,且所述另一磊晶特征包括p型掺杂锗化硅。
11.一种半导体装置,其特征在于,包括:
一基板;
一隔离结构,于所述基板之上;
二鳍片,于所述基板之上,且突出于所述隔离结构;
一磊晶特征,于所述二鳍片上;以及
一鳍状侧壁介电层,于所述基板之上与所述二鳍片的侧壁上,
其中:
所述磊晶特征包括二下部与一上部;
所述二下部分别位于所述二鳍片上;
所述上部位于所述二下部上,且物性连接所述二下部;
一部分的所述二下部的一者横向位于所述鳍状侧壁介电层及所述上部之间;以及
所述上部的一顶表面实质上平坦,且实质上与所述基板的一顶表面平行,其中所述上部与所述二下部具有同型的掺杂剂,但有不同的掺杂浓度。
12.根据权利要求11所述的半导体装置,其特征在于,还包括:
一第三鳍片于所述基板之上,且突出于所述隔离结构;
另一磊晶特征,于所述第三鳍片上;以及
一接触特征,与所述磊晶特征和所述另一磊晶特征相接,所述接触特征的一部分设置在所述磊晶特征的上部和所述另一磊晶特征的上部之间。
13.根据权利要求11所述的半导体装置,其特征在于,所述下部包括具有一n型掺杂剂的一第一浓度的硅,所述上部包括具有所述n型掺杂剂的一第二浓度的硅,且所述第二浓度高于所述第一浓度。
14.一种制造半导体装置的方法,其特征在于,该方法包括:
提供一基板、于所述基板之上的一隔离结构,以及从所述基板延伸并穿过所述隔离结构的至少二鳍片;
蚀刻所述至少二鳍片,从而形成至少二沟槽;
于所述至少二沟槽中成长第一磊晶特征;
在一第一成长条件下于在所述第一磊晶特征上成长第二磊晶特征,使得所述第二磊晶特征被成长为具有带有一凹陷的曲顶表面;以及
在所述第二磊晶特征达到目标临界尺寸之后,在不同于所述第一成长条件的一第二成长条件下成长所述第二磊晶特征,使得所述第二磊晶特征被成长为具有一实质上平坦的顶表面。
15.根据权利要求14所述的制造半导体装置的方法,其特征在于,所述第二磊晶特征包括硅,所述第一成长条件使用具有二氯硅烷的第一前体,且所述第二成长条件使用所述第一前体和硅烷。
16.根据权利要求15所述的制造半导体装置的方法,其特征在于,所述硅烷是四氢化硅(SiH4)。
17.根据权利要求14所述的制造半导体装置的方法,其特征在于,所述第二磊晶特征包括硅,所述第二成长条件使用比所述第一成长条件少的盐酸。
18.根据权利要求14所述的制造半导体装置的方法,其特征在于,还包括:
以一第一掺杂剂将所述第一磊晶特征掺杂至一第一掺杂浓度;以及
以所述第一掺杂剂将所述第二磊晶特征掺杂至高于所述第一掺杂浓度的一第二掺杂浓度。
19.根据权利要求14所述的制造半导体装置的方法,其特征在于,还包括:
在蚀刻所述至少二鳍片之前,在所述至少二鳍片的侧壁部分上形成一介电层,其中所述第一磊晶特征至少部分被所述介电层环绕。
20.根据权利要求14所述的制造半导体装置的方法,其特征在于,还包括:
于实质上平坦的顶表面上形成接触特征。
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