CN106896608B - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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CN106896608B
CN106896608B CN201710293911.1A CN201710293911A CN106896608B CN 106896608 B CN106896608 B CN 106896608B CN 201710293911 A CN201710293911 A CN 201710293911A CN 106896608 B CN106896608 B CN 106896608B
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gate line
array substrate
pixel electrode
gate
common electrode
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CN106896608A (zh
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刘立伟
严允晟
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种阵列基板及采用该阵列基板的显示面板、显示装置。所述阵列基板包括绝缘基板、沿第一方向延伸设于绝缘基板上的栅极线及沿第二方向延伸并与栅极线绝缘的数据线，所述栅极线与数据线交叉形成像素区域，并且像素区域在第一方向上的长度大于其在第二方向的长度，其中，所述栅极线上方依次设有栅绝缘层、钝化层及像素电极，并且所述像素电极覆盖所述栅极线。本发明的阵列基板中，将子像素分割方向由传统的沿栅极线方向变更为沿数据线方向，并采用像素电极覆盖栅极线信号，减少BM的使用，提高了开口率，同时像素电极与栅极线之间具有两层绝缘介质，间距得以增大，减少了栅极负载，提高了充电效率。

Description

阵列基板、显示面板及显示装置
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板、应用该阵列基板的显示面板及采用该显示面板的显示装置。
背景技术
众所周知，画面质量是显示器件最主要的追求方向，画质的细腻主要由分辨率的大小决定。分辨率越高，像素越小，由于需要对应在彩膜侧设置遮光单元，以消除数据线/栅极线附近电场紊乱导致的液晶紊乱进而引发出射光不可控的漏光影响，开口率也越小是毋庸置疑的。所以提升开口率是设计人员不断努力的方向。
专利申请US20100079695A1中公开了一种液晶显示器，其包括栅极线、设于栅极线上方的栅绝缘层、存储电极钝化层及像素电极，其将子像素的分割方向由传统的沿栅信号线方向变更为沿数据线方向，并采用在栅极线上覆盖存储电极来屏蔽栅极线信号，从而可以减少黑色矩阵(Black Matrix，BM)的使用，提升了开口率。
然而，由于在栅极线与存储电极之间的绝缘介质厚度过小，导致栅极线与存储电极之间的电容过大，使得栅极充电时间约为传统设计(子像素分割方向为栅极信号方向)的1/3，当前工艺难以满足充电率要求。同时，由于采用存储电极来覆盖栅极信号，导致栅极位置上存在两层金属，使得栅极信号对应位置高度过高，容易导致后期液晶配向时出现不均匀的问题。
发明内容
本发明的首要目的旨在提供一种可以在提高开口率基础上减小栅极负载的阵列基板。
本发明的另一目的在于提供一种采用上述阵列基板来提升分辨率的显示面板。
本发明的又一目的在于提供一种采用上述显示面板的显示装置，其具有较高的分辨率，画面质量较为优异。
为了实现上述目的，本发明提供以下技术方案：
一种阵列基板，包括绝缘基板、沿第一方向延伸设于绝缘基板上的栅极线及沿第二方向延伸并与栅极线绝缘的数据线，所述栅极线与数据线交叉形成像素区域，并且像素区域在第一方向上的长度大于其在第二方向的长度，其中，所述栅极线上方依次设有栅绝缘层、钝化层及像素电极，并且所述像素电极覆盖所述栅极线。
该阵列基板还包括共电极，所述栅极线沿宽度方向的至少一侧的栅绝缘层与钝化层之间限定出收容空间，所述共电极置于所述收容空间内，并且其边缘与所述像素电极在绝缘基板上的正投影至少部分重叠。
优选地，所述共电极靠近所述栅极线设置，以通过共电极屏蔽部分栅极信号，进一步减少彩膜侧的BM，提升开口率。
优选地，所述共电极与栅极线之间的水平距离为1.5μm～2μm。
优选地，所述共电极与像素电极相交叠部分的宽度范围为1.5μm～2.5μm。
优选地，所述共电极与像素电极之间的钝化层的厚度范围为150～250nm。
优选地，所述共电极沿宽度方向的两侧中，仅一侧边缘与像素电极相互交叠。
优选地，所述共电极与所述数据线同层设置且互不交叠。
优选地，所述栅极线与像素电极间的栅绝缘层的厚度为300～400nm，钝化层的厚度为150～250nm。
相比现有技术，本发明的方案具有以下优点：
本发明的阵列基板通过将子像素分割方向由沿栅极线信号方向变更为沿数据线方向，并采用像素电极覆盖栅极线，从而屏蔽了栅极线信号，减少了BM，提高了开口率。同时，由于栅极线与像素电极之间的绝缘层设有两层，使得栅极线与像素电极之间的间距得以增大，从而减小了栅极主要负载电容，提升充电效率。
第二方面，本发明还提供一种显示面板，包括相对设置的阵列基板、对位基板及设于二者间的液晶，其中，所述阵列基板为上述阵列基板。由于采用上述阵列基板，所述显示面板具有较高的开口率和分辨率，分辨率越高，开口率的提升效果越明显。
第三方面，本发明还提供一种显示装置，包括上述显示面板。其具有较高的开口率和分辨率，画面质量较为优异。
本发明附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本发明一种实施方式的阵列基板的结构示意图；
图2为图1所示阵列基板的A-A向截面图；
图3为图1所示阵列基板的B-B向截面图；
图4为本发明另一种实施方式的阵列基板的结构示意图；
图5为图4所示阵列基板的A-A向截面图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
第一方面，本发明提供一种阵列基板，解决传统工艺的阵列基板开口率低的问题，并针对性地克服专利申请(其公开号为US20100079695A1)所存在的栅极负载大、栅极位置过高容易导致液晶配向时造成的不均匀问题。
请参考图1至图3，图1～图3共同示出了本发明一种实施方式的阵列基板的结构。
在本实施方式中，所述阵列基板包括绝缘基板1、栅极线2、数据线8、共电极5、栅绝缘层3、钝化层4及像素电极6。
所述栅极线2沿第一方向延伸设于所述绝缘基板1上，所述数据线8沿第二方向延伸且与所述栅极线2绝缘地设于绝缘基板1上。所述栅极线2与数据线8交叉限定出像素区域(未标号，下同)，并且像素区域沿第一方向的长度大于第二方向的长度。
所述栅极线2上方依次设置所述栅绝缘层3、钝化层4及像素电极6，并且所述像素电极6覆盖所述栅极线2。优选地，栅极线2被下一行像素电极6所覆盖，即第N行栅极线2被第N+1行像素电极6覆盖，以通过像素电极6屏蔽栅极信号。
在本发明的阵列基板中，将子像素的分割方向由传统的沿栅极信号线方向变更为沿数据线方向，并通过像素电极6来覆盖栅极线2，从而屏蔽栅极信号，以避免栅极线2附近电场紊乱导致的液晶紊乱进而引发出射光不可控的漏光问题，可以减少彩膜侧作为遮光单元的黑色矩阵7(Black Matrix，BM)，从而提升了开口率。
在本发明中，栅极主要负载由栅极线2和像素电极6及二者间的绝缘介质构成，由于二者间绝缘介质设有两层(即栅绝缘层3和钝化层4)，增大了栅极线2与像素电极6之间的间距，从而减小了栅极主要负载，提升充电效率。
优选地，所述栅绝缘层3的厚度为300～400nm，钝化层4的厚度为150～250nm。
本实施方式中，通过像素电极6屏蔽栅极线2向外辐射的信号，与US20100079695A1实施方案相比可减少约40％的栅极信号负载电容。
在一帧图像显示中，一根栅极信号打开时间即充电时间极短，其余时间液晶分子需要维持不变，需要为其设置一个用于维持取向所需电压的电容，即存储电容。
优选地，在本发明中，所述存储电容主要在所述像素电极6与共电极5之间形成。具体地，所述栅极线2沿宽度方向一侧的钝化层4朝上拱起，与下方的栅绝缘层3限定出收容空间(未标号，下同)，所述共电极5设于该收容空间内，且其边缘与位于钝化层4上的像素电极6相互交叠，从而形成所需的存储电容。在本实施例中，所述共电极5宽度方向两侧边缘与所述像素电极6在绝缘基板上的正投影相互交叠。
本发明中，将共电极5设在所述栅极线2旁侧，避免了栅极线2位置设有两层金属而造成栅极线2位置过高，进而导致液晶配向时造成不均匀问题。优选地，所述共电极5靠近栅极线2设置，以屏蔽栅极线2向外辐射的信号，进一步减少BM范围，提升开口率。
考虑到工艺波动能力，保证共电极5与栅极线2无交叠，共电极5与栅极线2间距至少1.5μm以上。然而共电极为不透光金属，不宜距离栅极电极过远，防止其对开口率造成过大损失，二者的间距在2μm左右。
由于像素区域设有由金属制成的共电极5，导致开口率受到一定的降低。为此，本发明在保证所需存储电容大小的前提下，减少了共电极5与像素电极6的交叠面积，从而减少了遮光层的宽度，提升了开口率。优选地，本发明的共电极5与像素电极6的交叠宽度范围为1.5～2.5μm，具有较大的开口率。
在本实施方式中，在共电极5与像素电极6较小交叠面积的前提下，为了保证达到所需大小的存储电容，所述共电极5与像素电极6之间的钝化层4的厚度相应被减小。优选地，该位置处的钝化层4的厚度为150～250nm。
请结合图3，优选地，所述共电极5与所述数据线8同层设置，并且共电极5与数据线为同层金属互不交叠，以避免在二者间构成电容，减少了数据线负载，进而有利于降低能量损耗。
根据前文可知，所述栅极线2与像素电极6之间具有绝缘介质，并且栅极信号一帧时间仅有非常短的时间信号变化，其他时间均为固定值，栅极线2与像素电极6之间也可构成一存储电容，用以维持液晶完成其取向。其中栅极线2作为电位参考电极。
参见图4和图5，图4和图5示出了本发明另一种实施方式的阵列基板的结构。
本实施方式的阵列基板与上一个实施方式中的类似，即也具有玻璃基板、栅极线2、数据线8、栅绝缘层3、钝化层4、像素电极6及共电极5，其中玻璃基板、栅极线2、数据线8、栅绝缘层3、钝化层4、像素电极6的相对关系与上述实施方式中相同。其不同在于，所述栅极线2宽度方向的两侧均设有所述共电极5，所述共电极5宽度方向的一侧边缘与所述像素电极6相互交叠而形成所述存储电容。
优选地，两根所述共电极5的位置与BM的位置重叠，以免因增加的共电极而增加的挡光面积，由于只需采用1个电极转接孔，相对于上述现有的方案增加了开口率。在该方案中，共电极的一侧与像素电极在绝缘基板上的正投影存在交叠，而另一侧并没有交叠，以避免增加遮光面积而导致开口率的降低。
作为一种应用，本发明提供一种采用上述阵列基板的显示面板，其还包括对位基板和液晶盒，对位基板具有滤色镜、黑色矩阵等，液晶盒内填充有液晶。其中，所述对位基板与所述阵列基板相对设置，所述液晶盒设置于二者之间。由于采用像素电极6屏蔽栅极信号，减少了彩膜侧的BM，可以大幅提升了开口率，也减少了组盒过程中对位膜基板与阵列基板的对位导致的开口率损失。由于每个像素的开口率得到了提高，采用本发明的阵列基板，显示面板的分辨率越高，开口率增加效果越明显，显示面板显示的画质也就越细腻。
作为一种应用，本发明还提供一种采用上述显示面板的显示装置，由于采用的显示面板中阵列基板的开口率较高，其画面质量较为细腻。
以上所述仅是本发明的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

1.一种阵列基板，包括绝缘基板、沿第一方向延伸设于绝缘基板上的栅极线及沿第二方向延伸并与栅极线绝缘的数据线，所述栅极线与数据线交叉形成像素区域，并且像素区域在第一方向上的长度大于其在第二方向的长度，其特征在于，所述栅极线上方依次设有栅绝缘层、钝化层及像素电极，并且所述像素电极覆盖所述栅极线，所述阵列基板还包括与所述像素电极之间形成存储电容的共电极，所述共电极和所述栅极线在所述绝缘基板上的正投影不重叠。
2.根据权利要求1所述的阵列基板，其特征在于，所述栅极线沿宽度方向的至少一侧的栅绝缘层与钝化层之间限定出收容空间，所述共电极置于所述收容空间内，并且其边缘与所述像素电极在所述绝缘基板上的正投影至少部分交叠。
3.根据权利要求2所述的阵列基板，其特征在于，所述共电极靠近所述栅极线设置。
4.根据权利要求3所述的阵列基板，其特征在于，所述共电极与栅极线之间的水平距离为1.5μm～2μm。
5.根据权利要求2所述的阵列基板，其特征在于，所述共电极与像素电极相交叠部分的宽度范围为1.5μm～2.5μm。
6.根据权利要求5所述的阵列基板，其特征在于，所述共电极与像素电极之间的钝化层的厚度范围为150～250nm。
7.根据权利要求2所述的阵列基板，其特征在于，所述共电极沿宽度方向的两侧中，仅一侧边缘与像素电极相互交叠。
8.根据权利要求2所述的阵列基板，其特征在于，所述共电极与所述数据线同层设置，且互不交叠。
9.根据权利要求1所述的阵列基板，其特征在于，所述栅极线与像素电极间的栅绝缘层的厚度为300～400nm，钝化层的厚度为150～250nm。
10.一种显示面板，包括相对设置的阵列基板、对向基板及设于二者间的液晶，其特征在于，所述阵列基板为权利要求1至9任意一项所述的阵列基板。
11.一种显示装置，其特征在于，包括权利要求10所述的显示面板。
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