CN106887456A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN106887456A CN106887456A CN201611156536.8A CN201611156536A CN106887456A CN 106887456 A CN106887456 A CN 106887456A CN 201611156536 A CN201611156536 A CN 201611156536A CN 106887456 A CN106887456 A CN 106887456A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title abstract description 73
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- 230000008569 process Effects 0.000 description 14
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 2
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- 239000004964 aerogel Substances 0.000 description 1
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- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
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- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
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- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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- 239000010944 silver (metal) Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Condensed Matter Physics & Semiconductors (AREA)
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- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供了一种半导体器件,该半导体器件包括衬底、栅极结构、介电层、蚀刻停止层和粘合层。栅极结构形成在衬底上方。介电层形成在栅极结构旁边。粘合层覆盖栅极结构的顶面且延伸至介电层的第一顶面。蚀刻停止层在粘合层上方且与介电层的第二顶面接触。本发明实施例涉及半导体器件及其制造方法。
Description
技术领域
本发明实施例涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)产业经历了快速增长。在该发展的过程中,器件的功能密度由器件部件尺寸通常已经增加。
这种按比例缩小工艺通常通过提高生产效率、降低成本和/或改善性能来提供益处。这种按比例缩小工艺也增加了处理和制造IC的复杂度,并且为了要实现这些进步,需要在IC制造方面中的相似的发展。
随着技术节点缩小,在一些IC设计中,用金属栅电极来替换多晶硅栅电极,以提高具有减小的特征尺寸的器件性能。然而,对于金属栅电极的技术,仍然具有相当多的挑战要应对。
发明内容
根据本发明的一个实施例,提供了一种半导体器件,包括:栅极结构,位于衬底上方;介电层,位于所述栅极结构旁边;粘合层,位于所述栅极结构的顶面上方并且延伸至所述介电层的第一顶面;以及蚀刻停止层,位于所述粘合层上方并且与所述介电层的第二顶面接触。
根据本发明的另一实施例,还提供了一种半导体器件,包括:栅极结构,位于衬底上方;介电层,位于所述栅极结构旁边;蚀刻停止层,位于所述栅极结构和所述介电层上方;以及粘合层,位于所述栅极结构和所述蚀刻停止层之间,其中,所述粘合层包括:位于所述栅极结构上方的主要部分;以及与所述主要部分连接且填充至所述介电层的凹槽内的延伸部分。
根据本发明的又一实施例,还提供了一种半导体器件的制造方法,包括:在衬底上方形成栅极结构;在所述栅极结构旁边形成介电层;在所述介电层中和所述栅极结构中形成凹槽;在所述凹槽中形成粘合层,其中,所述粘合层覆盖所述栅极结构的顶面和所述介电层的第一顶面;以及在所述粘合层上方和所述介电层的第二顶面上方形成蚀刻停止层。
附图说明
图1是根据本发明的一些实施例示出的半导体器件的制造方法的流程图。
图2A至图2G是根据本发明的第一实施例示出的半导体器件的制造方法的示意性截面图。
图3是根据本发明的第二实施例的半导体器件的截面图。
图4是根据本发明的第三实施例的半导体器件的截面图。
图5是根据本发明的第四实施例的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
图1是根据本发明的一些实施例示出的半导体器件的制造方法的流程图。图2A至图2G是根据本发明的第一实施例示出的半导体器件的制造方法的示意性截面图。
同时参照图1和图2A,在步骤S001中,提供衬底100。在一些实施例中,衬底100是由硅或其他半导体材料制成的。可选地或附加地,衬底100包括其它元素半导体材料,诸如锗、砷化镓或其它合适的半导体材料。在一些实施例中,衬底100可以进一步包括其它部件,诸如各种掺杂区、掩埋层和/或外延层。此外,在一些实施例中,衬底100由诸如硅锗、碳化硅锗、磷砷化镓或磷铟化镓的合金半导体制成。此外,衬底100可为绝缘体上半导体,诸如绝缘体上硅(SOI)或蓝宝石上硅。
然后,在衬底100上方形成栅极结构102。在一些实施例中,栅极结构102包括从底至顶按顺序排列的栅极介电层106和栅电极108'。在可选实施例中,栅极结构102还可以包括衬底100和栅电极108'之间的界面层(IL)104。换言之,在IL 104和栅电极108'之间形成栅极介电层106。在一些实施例中,IL 104包括介电材料,诸如氧化硅层或氮氧化硅层。通过热氧化工艺、化学汽相沉积(CVD)工艺或原子层沉积(ALD)工艺形成IL 104。
在一些实施例中,栅极介电层106包括氧化硅、氮化硅、氮氧化硅、高k介电材料或它们的组合。高k介电材料通常是具有大于4的介电常数的介电材料。高k介电材料包括金属氧化物。在一些实施例中,用作高k介电材料的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物和/或它们的组合。通过热氧化工艺、CVD工艺或ALD工艺来形成栅极介电层106。
在一些实施例中,栅电极108'是伪栅极。例如,伪栅极包括由CVD工艺形成的多晶硅层。在可选实施例中,栅电极108'是金属栅极,且栅电极108'包括阻挡件、功函层、晶种层、粘合层、阻挡层或它们的组合。在一些实施例中,栅电极108'包括合适的金属,诸如用于PMOS器件的TiN、WN、TaN或Ru。在一些可选实施例中,栅电极108包括合适的金属,诸如用于NMOS器件的Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。
此外,栅极结构102还包括在栅极结构102的侧壁上方形成的间隔件112。在一些实施例中,间隔件112由氧化硅、氮化硅、氮氧化硅、碳化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料或它们的组合形成。间隔件112具有包括一个或多个衬垫层的多层结构。衬垫层包括诸如氧化硅、氮化硅和/或其他合适的材料的介电材料。可以通过沉积合适的介电材料和各向异性蚀刻掉介电材料来实现间隔件112的形成。
参照图2A,在衬底100中形成源极和漏极(S/D)区110以提供低电阻接触。通过硼或磷的离子注入取得掺杂区。可选地,在一些其它实施例中,通过蚀刻或其它合适的工艺去除衬底100的部分且通过外延生长在中空区域中形成掺杂剂。具体地,外延层包括SiGe、SiC或其它合适的材料。应该理解,可以通过CMOS技术处理形成半导体器件,并且因此在此不详细地描述一些工艺。
在一些实施例中,硅化物区(未示出)可以通过自对准硅化(硅化)工艺在S/D区110上可选择地形成。硅化物区包括硅化钛、硅化钴、硅化镍、硅化铂、硅化铒和硅化钯。在一些实施例中,如果衬底100包括Ge,锗化物区可以通过自对准锗化物工艺可选地形成在S/D区110上。在一些实施例中,锗化物区包括NiGe、PtGe、TiGe2、CoGe2或PdGe。
参照图2A,蚀刻停止层114'形成在栅极结构102和衬底100上方。在一些实施例中,共形地形成蚀刻停止层114'以覆盖栅极结构102和S/D区110的侧壁和顶面。在一些实施例中,蚀刻停止层114'是接触蚀刻停止层(CESL)。例如,蚀刻停止层114'包括氮化硅或碳掺杂的氮化硅。在一些实施例中,使用CVD、HDPCVD、SACVD、分子层沉积(MLD)或其它合适的方法沉积蚀刻停止层114'。在一些实施例中,在形成蚀刻停止层114之前,可以在衬底100上方进一步形成缓冲层(未示出)。在实施例中,缓冲层是诸如氧化硅的氧化物。然而,其它组分可以是可能的。在一些实施例中,使用CVD、HDPCVD、SACVD、MLD或其它合适的方法沉积缓冲层。
同时参照图1和图2A,在步骤S002中,在蚀刻停止层114'上方和栅极结构102旁边形成介电层116'。介电层116'包括介电材料。介电材料包括氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、旋涂玻璃(SOG)、氟化硅玻璃(FSG)、碳掺杂的氧化硅(例如,SiCOH)、聚酰亚胺和/或它们的组合。在一些其他实施例中,介电层116'包括低k介电材料。应该理解,低k介电材料通常是具有低于3.9的介电常数的介电材料。低k介电材料的实例包括BLACK(加利福尼亚圣克拉拉的应用材料公司)、XEROGEL、AEROGEL、氟化非晶碳、聚对二甲苯、BCB(双苯并环丁烯)、FLARE、(密歇根州米兰的陶氏化学公司)、氢倍半硅氧烷(HSQ)或氟化氧化硅(SiOF)和/或它们的组合。应该理解,介电层116'可以包括一种或多种介电材料和/或一个或多个介电层。在一些实施例中,通过CVD、HDPCVD、SACVD、旋涂或其它合适的方法沉积介电层116。
参照图2B,去除介电层116'的部分和蚀刻停止层114'的部分从而暴露出栅极结构102的顶面,且保留介电层116和蚀刻停止层114。通过化学机械抛光(CMP)工艺、蚀刻工艺或其它合适的工艺实现去除介电层116'的部分和蚀刻停止层114'的部分的工艺。
参照图2B,在一些实施例中,当栅电极108’是伪栅极时,实施栅极置换工艺。在栅极置换工艺中,去除栅电极108'以形成栅极沟槽,并且然后,栅电极108填充至栅极沟槽内。栅电极108可以包括阻挡件、功函层、晶种层、粘合层、阻挡层或它们的组合。在一些实施例中,栅电极108包括合适的金属,诸如用于PMOS器件的TiN、WN、TaN或Ru。在一些可选实施例中,栅电极108包括合适的金属,诸如用于NMOS器件的Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn或Zr。
参照图2B,在介电层116上方形成图案化的掩模层118。图案化的掩模层118具有暴露出介电层116的顶面的部分、栅极结构102的顶面和蚀刻停止层114的顶面的开口10。使用诸如旋涂掩模材料层,对掩模材料层实施光刻工艺和/或其它工艺的工艺形成图案化的掩模层118。具体地,光刻工艺包括曝光、烘烤和显影。掩模材料层对诸如KrF、ArF、EUV或电子束光的特定曝光束感光。在一些实施例中,掩模材料层可以包括聚合物、猝光剂、发色团、溶剂和/或化学放大剂(CA)。
同时地参照图1、图2B和图2C,在步骤S003中,实施蚀刻工艺以去除介电层116的部分、蚀刻停止层114的部分和栅极结构102的部分,从而在介电层116a、蚀刻停止层114a以及栅极结构102中形成凹槽20。凹槽20包括在栅电极108上方的凹槽22以及蚀刻停止层114a和介电层116a上方的凹槽24。在一些实施例中,当介电层116的部分的去除速率不等于栅极结构102的部分的去除速率时,介电层116a的由凹槽20暴露的表面具有阶梯形状。例如,如图2C所示,间隔件112a的顶面高于栅电极108a的顶面。在完成蚀刻工艺之后,去除图案化的掩模层118。通过干剥离工艺、湿剥离工艺或其它合适的工艺去除图案化的掩模层118。
同时参照图1、图2D和图2E,在步骤S004中,在去除图案化的掩模层118之后,在凹槽20中填充粘合材料层120以覆盖介电层116a、蚀刻停止层114a以及栅极结构102a。在一些实施例中,该粘合材料层120的材料是高k介电材料。高k介电材料通常是具有大于4的介电常数的介电材料。在一些实施例中,高k介电材料具有大于氮化硅的介电常数。高k介电材料包括含氮材料、金属氮化物材料、金属氧化物材料或它们的组合。含氮材料包括SiCN、SiOCN或它们的组合。金属氮化物材料包括AlN、TiN、TaN或它们的组合。金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu或它们混合物。在一些可选实施例中,粘合材料层120的材料可以是包括Al、Ti、Ta、W或它们的组合的金属材料。在一些实施例中,粘合材料层120的材料不同于随后形成的介电层116的材料、栅电极108a的材料和蚀刻停止层122的材料。本发明不旨在限制粘合材料层120的材料且只要粘合材料层120和栅电极108a之间的粘合性比栅电极108a和随后形成的蚀刻停止层122之间的粘合性好,则未列出的其它材料也可以是适合的。在另一方面,只要粘合材料层120和随后形成的蚀刻停止层122之间的粘合性比栅电极108a和随后形成的蚀刻停止层122之间的粘合性好,则本发明不限制粘合材料层120的材料。
参照图2E,去除粘合材料层120的部分,从而暴露出介电层116a的第二顶面S2。换言之,粘合层120a填充至凹槽22和凹槽24内。更具体地,粘合层120a覆盖栅极结构102a和蚀刻停止层114a的顶面且延伸至介电层116a的第一顶面S1。在一些实施例中,粘合层120a的顶面与介电层116a的第二顶面S2共面。例如,去除粘合材料层120的部分的方法可以包括化学机械抛光(CMP)工艺,回蚀刻工艺或它们的组合。
同时参照图1和图2F,在步骤S005中,在粘合层120a和介电层116a上方形成蚀刻停止层122。在接触孔蚀刻工艺期间,蚀刻停止层122能够保护栅极结构102a。例如,蚀刻停止层122包括氮化硅、氮氧化硅、碳化硅、碳掺杂的氮化硅或它们的组合。蚀刻停止层122可以具有任何合适的厚度,只要蚀刻停止层122的厚度足以在接触孔蚀刻工艺期间保护栅极结构102a免受损坏。在一些实施例中,可以使用CVD、HDPCVD、SACVD、分子层沉积(MLD)或其他合适的方法沉积蚀刻停止层122。
在一些实施例中,蚀刻停止层114a、122包括相同的材料。在一些可选实施例中,蚀刻停止层114a、122可以包括不同的材料。例如,在特定实施例中,蚀刻停止层114a是氮化硅,蚀刻停止层122是碳掺杂的氮化硅,反之亦然。
参考图2G,在蚀刻停止层122上方形成介电层124。在介电层124、蚀刻停止层122a和粘合层120b中形成接触孔125。在一些实施例中,通过光刻工艺和蚀刻工艺形成接触孔125。在一些实施例中,介电层124、116a可以包括相同的材料和相同的形成方法,但是本发明不限制于此。在其它实施例中,蚀刻停止层122a、114a可以包括不同的材料和不同的形成方法。已经在前面的段落中描述了材料和形成方法,且不在此重复细节。
之后,可以形成导电材料(未示出)以填充在接触孔125中,从而形成接触件126。接触件126形成在栅极结构102a上方且穿过介电层124、蚀刻停止层122a和粘合层120b以与栅电极108a电连接。例如,导电材料可以包括金属材料或合金。在一些实施例中,金属材料包括铜、铜合金、铝、铝合金、钨或它们的组合。在其它实施例中,接触件126可以包括衬垫层、晶种层、粘合层、阻挡层等。然后,去除导电材料的部分以暴露出介电层124的顶面。在一些实施例中,接触件126的顶面与介电层124的顶面共面。
参照回图2F,第一实施例的半导体器件包括衬底100、栅极结构102a、介电层116a、蚀刻停止层122和粘合层120a。第一实施例的半导体器件还包括介电层124和接触件126(图2G中示出)。在衬底100上方形成栅极结构102a。在栅极结构102a旁边形成介电层116a。粘合层120a填充在由蚀刻停止层122、栅极结构102a和介电层116a形成的凹槽20中。换言之,粘合层120a覆盖栅极结构102a的顶面且填充至介电层116a的凹槽24内。更具体地,栅极结构102a的顶面和蚀刻停止层122的底面之间存在高度差H。在一些实施例中,高度差H是指粘合层120a的厚度,且高度差H在至的范围内。蚀刻停止层122覆盖粘合层120a且与介电层116a的第二顶面S2接触。
在另一方面,粘合层120a包括主要部分121和连接至主要部分121的延伸部分123。如图2F所示,延伸部分123填充至介电层116a的凹槽24中。例如,粘合层120a和介电层116a之间的界面的轮廓可以是阶梯形状。在一些实施例中,粘合层120a的顶面面积T大于粘合层120a的底面面积B。
参照回图2F,应该注意,可以获得栅极结构102a和蚀刻停止层122之间的更好的粘合,从而防止诸如蚀刻停止层122的分层或剥离的问题。此外,粘合层120a不仅覆盖栅极结构102a的顶面,并且还覆盖介电层116a的第一顶面S1。因此,本发明的粘合层120a能够保护栅极结构102a和介电层116a之间的界面免受由接下来的湿化学清洗工艺提供的侵害路径的影响,湿化学清洗工艺提供的侵害路径将可能导致栅极结构102a的损失。此外,由于粘合层120a覆盖介电层116a的第一顶面S1,并且介电层的第二顶面与蚀刻停止层接触,本发明能够在减小半导体器件的RC延迟的同时增强粘合性。
图3是根据本发明的第二实施例的半导体器件的截面图。在下面的实施例中,相似的参考标号指示相似的组件,因此,这些组件的材料和形成方法不在此重复。
图3中示出的第二实施例的半导体器件相似于图2F中示出的第一实施例的半导体器件。第一实施例和第二实施例之间的不同在于第二实施例的粘合层220具有矩形且粘合层220和介电层116a之间的界面的轮廓是阶梯形状。在制造方法的视角中,当介电层116的部分的去除速率等于栅极结构102的部分的去除速率时,在其中形成的凹槽20a是矩形,且因此粘合层220具有矩形(如图3中所示)。在一些实施例中,粘合层220的顶面面积T等于粘合层220的底面面积B。
图4是根据本发明的第三实施例的半导体器件的截面图。
图4中示出的第三实施例的半导体器件相似于图2F中示出的第一实施例的半导体器件。例如,第一实施例和第三实施例之间的不同在于第三实施例的粘合层320具有倒梯形形状且粘合层320和介电层116a之间的界面的轮廓是坡形形状。在制造方法的视角中,当介电层116的部分的去除速率不等于栅极结构102的部分的去除速率时,在其中形成的凹槽20b具有倒梯形状(如图4中所示),并且因此,粘合层320具有倒梯形状。在一些实施例中,粘合层320的顶面面积T大于粘合层320的底面面积B。
图5是根据本发明的第四实施例的半导体器件的截面图。
图5中示出的第四实施例的半导体器件相似于图2F中示出的第一实施例的半导体器件。例如,第一实施例和第四实施例之间的不同在于第四实施例的粘合层420具有碗形形状且粘合层420和介电层116a之间的界面的轮廓是弧形形状。在制造方法的视角中,当介电层116的部分的去除速率不等于栅极结构102的部分的去除速率时,在其中形成的凹槽20c是碗形,且因此粘合层420具有碗形(如图5中所示)。在一些实施例中,粘合层420的顶面面积T大于粘合层420的底面面积B。
本发明不限制其中半导体器件包括MOS晶体管的应用,且本发明可以是延伸至具有动态随机存取存储器(DRAM)单元、单一电子晶体管(SET)和/或其它微电子器件(本文中共同地称为微电子器件)的其它集成电路。在另一实施例中,例如,半导体器件可以包括FinFET晶体管。
在本发明的实施例中,由于粘合层覆盖栅极结构的顶面且延伸至介电层的第一顶面,可以获得栅极结构和蚀刻停止层之间的更好的粘合形成,从而防止诸如蚀刻停止层的分层或剥离的问题。此外,本发明的粘合层能够保护栅极结构和介电层之间的界面免受由接下来的湿化学清洗工艺提供的侵害路径的影响,湿化学清洗工艺提供的侵害路径将可能导致栅极结构的损失。此外,由于粘合层覆盖介电层的第一顶面,并且介电层的第二顶面与蚀刻停止层接触,本发明能够在减小半导体器件的RC延迟的同时增强粘合性。
根据本发明的一些实施例,一种半导体器件包括衬底、栅极结构、介电层、蚀刻停止层和粘合层。栅极结构形成在衬底上方。介电层形成在栅极结构旁边。粘合层覆盖栅极结构的顶面且延伸至介电层的第一顶面。蚀刻停止层形成在粘合层上方且与介电层的第二顶面接触。
根据本发明的又可选的实施例,一种半导体器件包括栅极结构、介电层、蚀刻停止层和粘合层。栅极结构形成在衬底上方。介电层形成在栅极结构旁边。蚀刻停止层形成在栅极结构和介电层上方。粘合层形成在蚀刻停止层和栅极结构之间,其中,粘合层包括主要部分和延伸部分。延伸部分与主要部分连接且填充至介电层的凹槽内。
根据本发明的可选实施例,一种半导体器件的制造方法的步骤包括如下。在衬底上方形成栅极结构。在栅极结构旁边形成介电层。在介电层中和栅极结构中形成凹槽。在凹槽中形成粘合层。粘合层覆盖栅极结构的顶面和介电层的第一顶面。在粘合层和介电层的第二顶面上方形成蚀刻停止层。
根据本发明的一个实施例,提供了一种半导体器件,包括:栅极结构,位于衬底上方;介电层,位于所述栅极结构旁边;粘合层,位于所述栅极结构的顶面上方并且延伸至所述介电层的第一顶面;以及蚀刻停止层,位于所述粘合层上方并且与所述介电层的第二顶面接触。
在上述半导体器件中,所述粘合层的形状包括T形、倒梯形、碗形、矩形或它们的组合。
在上述半导体器件中,所述粘合层的顶面与所述介电层的所述第二顶面共面。
在上述半导体器件中,所述粘合层的材料是高k介电材料,且所述高k介电材料是具有大于4的介电常数的介电材料。
在上述半导体器件中,所述高k介电材料包括含氮材料、金属氮化物材料、金属氧化物材料或它们的组合。
在上述半导体器件中,所述蚀刻停止层的材料包括氮化硅、氮氧化硅、碳化硅、碳掺杂的氮化硅或它们的组合。
在上述半导体器件中,所述栅极结构包括:栅电极;以及间隔件,位于所述栅电极和所述介电层之间,其中,所述间隔件被所述粘合层覆盖。
根据本发明的另一实施例,还提供了一种半导体器件,包括:栅极结构,位于衬底上方;介电层,位于所述栅极结构旁边;蚀刻停止层,位于所述栅极结构和所述介电层上方;以及粘合层,位于所述栅极结构和所述蚀刻停止层之间,其中,所述粘合层包括:位于所述栅极结构上方的主要部分;以及与所述主要部分连接且填充至所述介电层的凹槽内的延伸部分。
在上述半导体器件中,所述粘合层和所述介电层之间的界面的轮廓包括阶梯形、坡形、弧形或它们的组合。
在上述半导体器件中,所述粘合层的顶面面积大于或等于所述粘合层的底面面积。
根据本发明的又一实施例,还提供了一种半导体器件的制造方法,包括:在衬底上方形成栅极结构;在所述栅极结构旁边形成介电层;在所述介电层中和所述栅极结构中形成凹槽;在所述凹槽中形成粘合层,其中,所述粘合层覆盖所述栅极结构的顶面和所述介电层的第一顶面;以及在所述粘合层上方和所述介电层的第二顶面上方形成蚀刻停止层。
在上述的半导体器件的制造方法中,形成所述粘合层的步骤包括:在所述介电层上方和所述凹槽中形成粘合材料层;以及去除所述粘合材料层的部分,从而暴露出所述介电层的所述第二顶面。
在上述的半导体器件的制造方法中,去除所述粘合材料层的所述部分的方法包括化学机械抛光(CMP)工艺、回蚀刻工艺或它们的组合。
在上述的半导体器件的制造方法中,形成所述凹槽的步骤包括:在所述介电层上方形成图案化的掩模层,其中,所述图案化的掩模层具有开口,所述开口暴露出所述栅极结构以及暴露出所述介电层的部分;以及实施蚀刻工艺以去除所述栅极结构的部分和所述介电层的部分。
在上述的半导体器件的制造方法中,在所述蚀刻工艺中,所述介电层的所述部分的去除速率等于所述栅极结构的所述部分的去除速率。
在上述的半导体器件的制造方法中,在所述蚀刻工艺中,所述介电层的所述部分的去除速率不等于所述栅极结构的所述部分的去除速率。
在上述的半导体器件的制造方法中,所述粘合层的形状包括T形、倒梯形、碗形、矩形或它们的组合。
在上述的半导体器件的制造方法中,所述粘合层的材料和所述介电层的材料不同。
在上述的半导体器件的制造方法中,所述粘合层的材料包括高k介电材料,所述高k介电材料包括含氮材料、金属氮化物材料、金属材料或它们的组合。
在上述的半导体器件的制造方法中,还包括在所述栅极结构上方形成接触件,其中,所述接触件穿过所述蚀刻停止层和所述粘合层以与所述栅极结构电连接。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (1)
1.一种半导体器件,包括:
栅极结构,位于衬底上方;
介电层,位于所述栅极结构旁边;
粘合层,位于所述栅极结构的顶面上方并且延伸至所述介电层的第一顶面;以及
蚀刻停止层,位于所述粘合层上方并且与所述介电层的第二顶面接触。
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