CN106876477B - 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法 - Google Patents

一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法 Download PDF

Info

Publication number
CN106876477B
CN106876477B CN201710166641.8A CN201710166641A CN106876477B CN 106876477 B CN106876477 B CN 106876477B CN 201710166641 A CN201710166641 A CN 201710166641A CN 106876477 B CN106876477 B CN 106876477B
Authority
CN
China
Prior art keywords
layer
pattern
photoresist layer
thin film
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201710166641.8A
Other languages
English (en)
Other versions
CN106876477A (zh
Inventor
张慧文
占建英
王志鹏
于凯
李铁朋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201710166641.8A priority Critical patent/CN106876477B/zh
Publication of CN106876477A publication Critical patent/CN106876477A/zh
Application granted granted Critical
Publication of CN106876477B publication Critical patent/CN106876477B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Abstract

本申请实施例提供一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法,以简化图案化目标膜层的制作工艺,降低图案化目标膜层的制作成本。所述制作方法包括:在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;在所述光刻胶层上形成目标层薄膜;去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。

Description

一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法
技术领域
本申请涉及显示领域,尤其涉及一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法。
背景技术
平面显示器(F1at Pane1Disp1ay,FPD)己成为市场上的主流产品,平面显示器的种类也越来越多,如液晶显示器(Liquid Crysta1Disp1ay,LCD)、有机发光二极管(OrganicLight Emitted Diode,OLED)显示器、等离子体显示面板(P1asma Disp1ay Pane1,PDP)及场发射显示器(Field Emission Display,FED)等。作为FPD产业核心技术的薄膜晶体管(Thin Film Transistor,TFT)背板技术,也在经历着深刻的变革。
现有技术中的薄膜晶体管,在制作图案化的源漏极层和/或栅极层时,通常是先形成一层金属薄膜,再在金属薄膜上形成图案化的光刻胶层,在图案化的光刻胶层的遮挡下对金属薄膜进行单独刻蚀,形成图案化的源漏极层和/或栅极层,最后将图案化的光刻胶层去除。即,现有技术在形成图案化的目标膜层(例如,图案化的目标膜层为源漏极层)时,通常都需要对目标膜层进行单独刻蚀,使图案化的目标膜层的制作工序较多,制作成本较高。
发明内容
本申请实施例提供一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法,以简化图案化目标膜层的制作工艺,降低图案化膜层的制作成本。
本申请实施例提供一种图案化目标膜层的制作方法,包括:
在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;
在所述光刻胶层上形成目标层薄膜;
去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
优选的,所述目标膜层为薄膜晶体管的源漏极膜层和/或栅极膜层;
所述在所述光刻胶层上形成目标层薄膜,具体包括:在所述光刻胶层上形成至少一层金属层薄膜。
优选的,所述在所述光刻胶层上形成至少一层金属层薄膜,具体包括:
在所述光刻胶层上依次形成银薄膜和铜薄膜。
优选的,在所述光刻胶层上依次形成银薄膜和铜薄膜,具体包括:
通过银镜反应,在所述光刻胶层上形成银薄膜;
通过铜镜反应,在所述银薄膜上形成铜薄膜。
优选的,所述去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案,具体包括:
采用丙酮溶液或无水乙醇溶液对所述光刻胶层进行剥离,以去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。
实施例还提供一种薄膜晶体管的制作方法,包括:形成栅极、有源层、源漏极的图形;
其中,采用本申请实施例所述的制作方法形成所述栅极和/或源漏极的图形。
本申请实施例还提供一种图案化的目标膜层,采用本申请实施例所述的制作方法制作。
本申请实施例还提供一种薄膜晶体管,包括本申请实施例所述的目标膜层,所述目标膜层为源漏极和/或栅极。
本申请实施例还提供一种阵列基板,包括本申请实施例提供的所述薄膜晶体管。
本申请实施例还提供一种显示装置,包括本申请实施例还提供所述的阵列基板。
本申请实施例的有益效果如下:本申请实施例提供的图案化膜层的制作方法,在形成图案化的目标膜层时,先形成具有与目标膜层的图案相互补的图案的光刻胶层,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化目标膜层制作成本。
附图说明
图1为本申请实施例提供的一种图案化目标膜层的制作流程图;
图2为在有源层上形成光刻胶后的结构示意图;
图3为将光刻胶层进行图案化后的结构示意图;
图4为在图案化的光刻胶层上形成银薄膜后的结构示意图;
图5为在银薄膜上形成铜薄膜后的结构示意图;
图6为去除图案化的光刻胶层后的结构示意图。
具体实施方式
下面结合说明书附图对本发明实施例的实现过程进行详细说明。需要注意的是,自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。
参见图1,本申请实施例提供一种图案化目标膜层的制作方法,包括:
步骤101,在衬底基板上形成图案化的光刻胶层,其中,光刻胶层的图案为与目标膜层的图案互补的图案。
步骤102,在光刻胶层上形成目标层薄膜。
步骤103,去除图案化的光刻胶层,并同时去除与光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
在具体实施时,可以采用丙酮溶液或无水乙醇溶液对光刻胶层进行剥离,以去除图案化的光刻胶层,并同时去除与光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。进一步的,可以在剥离的过程中增加超声、震荡等辅助手段增强剥离光刻胶的力度。
本申请实施例提供一种图案化膜层的制作方法,在形成图案化的目标膜层时,先形成与目标膜层的图案相互补的光刻胶层图案,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化膜层的制作成本。
需要说明的是,由于在具体实施时,在制作薄膜晶体管的源漏极时,一般还同时形成与源漏极同层的数据线,在制作薄膜晶体管的栅极时,一般还同时形成与栅极同层的栅线,进而本申请实施例中目标膜层的图案具体可以为包括源漏极和/或数据线的源漏极层图案,也可以是包括栅极和/或栅线的栅极层图案。
优选的,若目标膜层为薄膜晶体管的源漏极膜层和/或栅极膜层,则关于步骤102,在光刻胶层上形成目标层薄膜,具体包括,在光刻胶层上形成至少一层金属层薄膜。
进一步地,考虑到现有技术中的源漏极层一般采用Al、Mo复合金属膜层制作,而Al和Mo的电导率较低,形成的源漏极电阻较大,进而导致形成的薄膜晶体管的功耗较高。优选的,在光刻胶层上形成至少一层金属层薄膜,具体包括:在光刻胶层上依次形成银薄膜和铜薄膜。由于银和铜的导电率大于铝和钼的电导率,进而采用银薄膜和铜薄膜的复合膜层作为源漏极,可以降低薄膜晶体管的源漏极电阻,降低薄膜晶体管的功耗。另外,由于铜的粘附性较差,不易直接附着在一般膜层(衬底基板或栅极绝缘层)上,因此,在形成铜薄膜时,先形成银薄膜,进而可以避免铜薄膜易脱落的问题。
在具体实施时,具体可以在光刻胶层上通过银镜反应形成银薄膜,在银薄膜上通过铜镜反应形成铜薄膜。关于通过银镜反应在光刻胶层上形成银薄膜,以及通过铜镜反应在银薄膜上形成铜薄膜,进行如下详细说明。
分别配制酒石酸钾钠溶液和银氨溶液。具体的,将8g四水酒石酸钾钠和2.6g氢氧化钠加到20ml蒸馏水中,形成酒石酸钾钠溶液。在质量分数为5%的硝酸银溶液中,滴加质量分数为5%的氢氧化钠溶液,并在不断振荡下滴加稀氨水至沉淀刚好溶解为止,形成银氨溶液。
将上述银氨溶液与质量分数为3%的葡萄糖溶液以体积比为2:1进行混合,形成第一混合溶液,在该第一混合溶液中于光刻胶层上形成银薄膜。在具体实施时,可以将银氨溶液缓慢滴加到葡萄糖溶液中,并在滴加的过程中进行震荡以降低反应速度,使生成的银晶粒较小,银膜较为致密,提高形成的银膜的质量。具体实施时,可以通过反应时间来控制形成的银薄膜的厚度。
将质量分数为7%的硫酸铜溶液、酒石酸钾钠溶液和质量分数为37%甲醛溶液进行等体积混合,形成第二混合溶液,并将该第二混合溶液加入到上述第一混合溶液中,形成第三混合溶液,并在该第三混合溶液中于银薄膜上形成铜薄膜。当然,上述溶液的具体百分数以及其它的具体用量只是为了更清楚的理解本申请而进行的举例说明,在具体实施时,可以根据需要进行适当调整,本申请并不以此为限。
相比于现有技术在制作铜膜的源漏极膜层和/或栅极膜层时,通常先通过镀膜工艺形成铜薄膜,再通过双氧水刻蚀铜薄膜使铜薄膜图案化,在制作过程中,由于双氧水溶液挥发,浓度较难控制,存在使铜薄膜图案化较困难的问题。本申请实施例中,在形成薄膜晶体管的源漏极层时,先形成图案化的光刻胶层,再在图案化的光刻胶层上通过银镜反应形成银薄膜,通过铜镜反应形成铜薄膜,在去除图案化的光刻胶时,可以同时去除与光刻胶的图案对应区域的银薄膜和铜薄膜,形成图案化的源漏极层,不需要通过对铜薄膜进行单独的刻蚀工艺,避免由于刻蚀液较易挥发导致的源漏极膜层和/或栅极膜层刻蚀较难的问题,且采用铜镜反应代替镀膜工艺形成源漏极层和/或栅极层,可以简化源漏极膜层和/或栅极层的制作工序,降低源漏极膜层和/或栅极层的制作成本。
为了更清楚的理解本申请实施例提供的图案化的目标膜层的制作方法进行说明,以下以图案化的目标膜层为薄膜晶体管的源漏极层为例,结合附图2至附图6进行如下说明:
步骤一,在有源层4上涂覆具有预设厚度的光刻胶层5。光刻胶层5的厚度具体可以为2~3微米,优选的,例如光刻胶层5的厚度为2.2微米。在有源层4上形成光刻胶层5后的结构示意图如图2所示。需要说明的是,该步骤是以薄膜晶体管为底栅型薄膜晶体管为例进行举例说明,且在有源层4上形成光刻胶层5之前,薄膜晶体管的制作方法还包括,在衬底基板1上形成栅极2,在栅极2上形成栅极绝缘层3,在栅极绝缘层3上形成有源层4。
步骤二,利用掩膜版,通过曝光、显影技术,将光刻胶层5形成与源漏极层的图案相互补的图案,即,将需要形成的源极和漏极的地方的光刻胶去掉,不需要形成源极和漏极的地方的光刻胶留下。将光刻胶5进行图案化后的示意图如图3所示。
步骤三,利用银镜反应,在图案化的光刻胶层上形成银薄膜6。在光刻胶层5上形成银薄膜6后的示意图如图4所示。
步骤四,利用铜镜反应,在银薄膜6上形成铜薄膜7。在银薄膜6上形成铜薄膜7后的示意图如图5所示。
步骤五,通过丙酮溶液,将图案化的光刻胶层5去掉,与此同时,具有光刻胶层5地方的银薄膜6和铜薄膜7也被去掉,形成由部分银薄膜和部分铜薄膜组成的源漏极膜层。去除图案化的光刻胶层后的示意图如图6所示。在具体实施时,可以增加超声、震荡等辅助手段增强剥离的力度。
本申请实施例还提供一种图案化的目标膜层,采用本申请实施例提供的图案化的目标膜层的制作方法制作。
本申请实施例还提供一种薄膜晶体管,包括本申请实施例提供的目标膜层,目标膜层为源漏极和/或栅极。
本申请实施例提供的阵列基板,包括本申请实施例提供的薄膜晶体管。
本申请实施例提供的显示装置,包括本申请实施例提供的阵列基板。
本申请实施例的有益效果如下:本申请实施例提供一种图案化膜层的制作方法,在形成图案化的目标膜层时,先形成与目标膜层的图案相互补的光刻胶层图案,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化膜层的制作成本。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。

Claims (7)

1.一种图案化目标膜层的制作方法,其特征在于,所述制作方法包括:
在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;
通过银镜反应,在所述光刻胶层上形成银薄膜;
通过铜镜反应,在所述银薄膜上形成铜薄膜;
去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的银薄膜和铜薄膜,形成银薄膜和铜薄膜的图案。
2.如权利要求1所述的制作方法,其特征在于,所述去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案,具体包括:
采用丙酮溶液或无水乙醇溶液对所述光刻胶层进行剥离,以去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。
3.一种薄膜晶体管的制作方法,其特征在于,包括:形成栅极、有源层、源漏极的图形;
其中,采用如权利要求1或2所述的制作方法形成所述栅极和/或源漏极的图形。
4.一种图案化的目标膜层,其特征在于,采用如权利要求1或2所述的制作方法制作。
5.一种薄膜晶体管,其特征在于,包括如权利要求4所述的目标膜层,所述目标膜层为源漏极和/或栅极。
6.一种阵列基板,其特征在于,包括如权利要求5所述的薄膜晶体管。
7.一种显示装置,其特征在于,包括如权利要求6所述的阵列基板。
CN201710166641.8A 2017-03-20 2017-03-20 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法 Expired - Fee Related CN106876477B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710166641.8A CN106876477B (zh) 2017-03-20 2017-03-20 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710166641.8A CN106876477B (zh) 2017-03-20 2017-03-20 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法

Publications (2)

Publication Number Publication Date
CN106876477A CN106876477A (zh) 2017-06-20
CN106876477B true CN106876477B (zh) 2019-09-03

Family

ID=59173257

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710166641.8A Expired - Fee Related CN106876477B (zh) 2017-03-20 2017-03-20 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法

Country Status (1)

Country Link
CN (1) CN106876477B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265303B (zh) * 2019-06-12 2021-04-02 深圳市华星光电半导体显示技术有限公司 一种显示面板的制作方法
CN114023848A (zh) * 2021-11-03 2022-02-08 广东工业大学 一种图案化二维半金属薄膜的方法及其应用

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000871A (zh) * 2007-01-04 2007-07-18 京东方科技集团股份有限公司 金属导线、电极及薄膜晶体管阵列基板的制造方法
CN103367166A (zh) * 2013-07-19 2013-10-23 京东方科技集团股份有限公司 薄膜晶体管制备方法和系统、以及薄膜晶体管、阵列基板
CN105529274A (zh) * 2016-02-02 2016-04-27 京东方科技集团股份有限公司 薄膜晶体管的制作方法、阵列基板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000871A (zh) * 2007-01-04 2007-07-18 京东方科技集团股份有限公司 金属导线、电极及薄膜晶体管阵列基板的制造方法
CN103367166A (zh) * 2013-07-19 2013-10-23 京东方科技集团股份有限公司 薄膜晶体管制备方法和系统、以及薄膜晶体管、阵列基板
CN105529274A (zh) * 2016-02-02 2016-04-27 京东方科技集团股份有限公司 薄膜晶体管的制作方法、阵列基板和显示装置

Also Published As

Publication number Publication date
CN106876477A (zh) 2017-06-20

Similar Documents

Publication Publication Date Title
US6627544B2 (en) Method of making a metal film pattern
WO2009093602A1 (ja) 表示装置
US9685556B2 (en) Thin film transistor and preparation method therefor, array substrate, and display apparatus
CN106876477B (zh) 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法
TWI711950B (zh) 觸控面板感測器
US20130075266A1 (en) Method of manufacturing touch panel
CN103295970A (zh) 阵列基板、其制造方法及显示装置
US20160011457A1 (en) Fabrication method of substrate
JP2014218747A (ja) マスクおよびマスクの製造方法
JP2006187856A (ja) 炭素ナノチューブの合成のための触媒層のパターニング方法及びそれを利用した電界放出素子の製造方法
US7393259B2 (en) Method of forming emitters and method of manufacturing field emission device (FED)
TW200705655A (en) Method for manufacturing liquid crystal display substrates
US9128377B2 (en) Method for forming graphene pattern
JP2016113668A (ja) 蒸着マスクの製造方法、蒸着マスクを作製するために用いられる金属板および蒸着マスク
KR20130022170A (ko) 터치패널 및 그 제조방법
WO2021031368A1 (zh) 显示面板及其制备方法和终端
JP2014122384A (ja) 蒸着マスクの製造方法及び蒸着マスク
CN106057667B (zh) 膜层图案的制作方法、基板的制作方法及基板、显示装置
CN106200258B (zh) 一种掩膜板、对其曝光的方法以及电路面板的制造方法
CN111326290B (zh) 透明导电膜的制造方法
US20130252177A1 (en) Method for manufacturing a fine metal electrode
JP2003213436A (ja) 金属膜パターンおよびその製造方法
CN108449927B (zh) 一种金属薄膜及其制作方法
JP2002353167A (ja) 金属配線基板及び金属配線基板の製造方法並びに反射型液晶表示装置用金属配線基板
US20090022900A1 (en) Method for manufacturing wire grid device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190903

Termination date: 20210320

CF01 Termination of patent right due to non-payment of annual fee