CN106876477A - 一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法 - Google Patents
一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法 Download PDFInfo
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- 239000010408 film Substances 0.000 title claims abstract description 110
- 239000010409 thin film Substances 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 90
- 238000000059 patterning Methods 0.000 claims abstract description 48
- 230000000295 complement effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 28
- 229910052802 copper Inorganic materials 0.000 claims description 28
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- 229910000906 Bronze Inorganic materials 0.000 claims description 7
- 239000010974 bronze Substances 0.000 claims description 7
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 239000000243 solution Substances 0.000 description 12
- 239000011259 mixed solution Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- LJCNRYVRMXRIQR-OLXYHTOASA-L potassium sodium L-tartrate Chemical compound [Na+].[K+].[O-]C(=O)[C@H](O)[C@@H](O)C([O-])=O LJCNRYVRMXRIQR-OLXYHTOASA-L 0.000 description 4
- 235000011006 sodium potassium tartrate Nutrition 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229940074439 potassium sodium tartrate Drugs 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 2
- WQZGKKKJIJFFOK-GASJEMHNSA-N Glucose Natural products OC[C@H]1OC(O)[C@H](O)[C@@H](O)[C@@H]1O WQZGKKKJIJFFOK-GASJEMHNSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000009514 concussion Effects 0.000 description 2
- 239000008103 glucose Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- SQGYOTSLMSWVJD-UHFFFAOYSA-N silver(1+) nitrate Chemical compound [Ag+].[O-]N(=O)=O SQGYOTSLMSWVJD-UHFFFAOYSA-N 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonium chloride Substances [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 1
- 102100035366 Centromere protein M Human genes 0.000 description 1
- 101000737696 Homo sapiens Centromere protein M Proteins 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 229910001961 silver nitrate Inorganic materials 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1259—Multistep manufacturing methods
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- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- Thin Film Transistor (AREA)
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Abstract
本申请实施例提供一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法,以简化图案化目标膜层的制作工艺,降低图案化目标膜层的制作成本。所述制作方法包括:在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;在所述光刻胶层上形成目标层薄膜;去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
Description
技术领域
本申请涉及显示领域,尤其涉及一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法。
背景技术
平面显示器(F1at Pane1Disp1ay,FPD)己成为市场上的主流产品,平面显示器的种类也越来越多,如液晶显示器(Liquid Crysta1Disp1ay,LCD)、有机发光二极管(OrganicLight Emitted Diode,OLED)显示器、等离子体显示面板(P1asma Disp1ay Pane1,PDP)及场发射显示器(Field Emission Display,FED)等。作为FPD产业核心技术的薄膜晶体管(Thin Film Transistor,TFT)背板技术,也在经历着深刻的变革。
现有技术中的薄膜晶体管,在制作图案化的源漏极层和/或栅极层时,通常是先形成一层金属薄膜,再在金属薄膜上形成图案化的光刻胶层,在图案化的光刻胶层的遮挡下对金属薄膜进行单独刻蚀,形成图案化的源漏极层和/或栅极层,最后将图案化的光刻胶层去除。即,现有技术在形成图案化的目标膜层(例如,图案化的目标膜层为源漏极层)时,通常都需要对目标膜层进行单独刻蚀,使图案化的目标膜层的制作工序较多,制作成本较高。
发明内容
本申请实施例提供一种图案化目标膜层、薄膜晶体管、阵列基板及制作方法,以简化图案化目标膜层的制作工艺,降低图案化膜层的制作成本。
本申请实施例提供一种图案化目标膜层的制作方法,包括:
在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;
在所述光刻胶层上形成目标层薄膜;
去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
优选的,所述目标膜层为薄膜晶体管的源漏极膜层和/或栅极膜层;
所述在所述光刻胶层上形成目标层薄膜,具体包括:在所述光刻胶层上形成至少一层金属层薄膜。
优选的,所述在所述光刻胶层上形成至少一层金属层薄膜,具体包括:
在所述光刻胶层上依次形成银薄膜和铜薄膜。
优选的,在所述光刻胶层上依次形成银薄膜和铜薄膜,具体包括:
通过银镜反应,在所述光刻胶层上形成银薄膜;
通过铜镜反应,在所述银薄膜上形成铜薄膜。
优选的,所述去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案,具体包括:
采用丙酮溶液或无水乙醇溶液对所述光刻胶层进行剥离,以去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。
实施例还提供一种薄膜晶体管的制作方法,包括:形成栅极、有源层、源漏极的图形;
其中,采用本申请实施例所述的制作方法形成所述栅极和/或源漏极的图形。
本申请实施例还提供一种图案化的目标膜层,采用本申请实施例所述的制作方法制作。
本申请实施例还提供一种薄膜晶体管,包括本申请实施例所述的目标膜层,所述目标膜层为源漏极和/或栅极。
本申请实施例还提供一种阵列基板,包括本申请实施例提供的所述薄膜晶体管。
本申请实施例还提供一种显示装置,包括本申请实施例还提供所述的阵列基板。
本申请实施例的有益效果如下:本申请实施例提供的图案化膜层的制作方法,在形成图案化的目标膜层时,先形成具有与目标膜层的图案相互补的图案的光刻胶层,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化目标膜层制作成本。
附图说明
图1为本申请实施例提供的一种图案化目标膜层的制作流程图;
图2为在有源层上形成光刻胶后的结构示意图;
图3为将光刻胶层进行图案化后的结构示意图;
图4为在图案化的光刻胶层上形成银薄膜后的结构示意图;
图5为在银薄膜上形成铜薄膜后的结构示意图;
图6为去除图案化的光刻胶层后的结构示意图。
具体实施方式
下面结合说明书附图对本发明实施例的实现过程进行详细说明。需要注意的是,自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。
参见图1,本申请实施例提供一种图案化目标膜层的制作方法,包括:
步骤101,在衬底基板上形成图案化的光刻胶层,其中,光刻胶层的图案为与目标膜层的图案互补的图案。
步骤102,在光刻胶层上形成目标层薄膜。
步骤103,去除图案化的光刻胶层,并同时去除与光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
在具体实施时,可以采用丙酮溶液或无水乙醇溶液对光刻胶层进行剥离,以去除图案化的光刻胶层,并同时去除与光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。进一步的,可以在剥离的过程中增加超声、震荡等辅助手段增强剥离光刻胶的力度。
本申请实施例提供一种图案化膜层的制作方法,在形成图案化的目标膜层时,先形成与目标膜层的图案相互补的光刻胶层图案,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化膜层的制作成本。
需要说明的是,由于在具体实施时,在制作薄膜晶体管的源漏极时,一般还同时形成与源漏极同层的数据线,在制作薄膜晶体管的栅极时,一般还同时形成与栅极同层的栅线,进而本申请实施例中目标膜层的图案具体可以为包括源漏极和/或数据线的源漏极层图案,也可以是包括栅极和/或栅线的栅极层图案。
优选的,若目标膜层为薄膜晶体管的源漏极膜层和/或栅极膜层,则关于步骤102,在光刻胶层上形成目标层薄膜,具体包括,在光刻胶层上形成至少一层金属层薄膜。
进一步地,考虑到现有技术中的源漏极层一般采用Al、Mo复合金属膜层制作,而Al和Mo的电导率较低,形成的源漏极电阻较大,进而导致形成的薄膜晶体管的功耗较高。优选的,在光刻胶层上形成至少一层金属层薄膜,具体包括:在光刻胶层上依次形成银薄膜和铜薄膜。由于银和铜的导电率大于铝和钼的电导率,进而采用银薄膜和铜薄膜的复合膜层作为源漏极,可以降低薄膜晶体管的源漏极电阻,降低薄膜晶体管的功耗。另外,由于铜的粘附性较差,不易直接附着在一般膜层(衬底基板或栅极绝缘层)上,因此,在形成铜薄膜时,先形成银薄膜,进而可以避免铜薄膜易脱落的问题。
在具体实施时,具体可以在光刻胶层上通过银镜反应形成银薄膜,在银薄膜上通过铜镜反应形成铜薄膜。关于通过银镜反应在光刻胶层上形成银薄膜,以及通过铜镜反应在银薄膜上形成铜薄膜,进行如下详细说明。
分别配制酒石酸钾钠溶液和银氨溶液。具体的,将8g四水酒石酸钾钠和2.6g氢氧化钠加到20ml蒸馏水中,形成酒石酸钾钠溶液。在质量分数为5%的硝酸银溶液中,滴加质量分数为5%的氢氧化钠溶液,并在不断振荡下滴加稀氨水至沉淀刚好溶解为止,形成银氨溶液。
将上述银氨溶液与质量分数为3%的葡萄糖溶液以体积比为2:1进行混合,形成第一混合溶液,在该第一混合溶液中于光刻胶层上形成银薄膜。在具体实施时,可以将银氨溶液缓慢滴加到葡萄糖溶液中,并在滴加的过程中进行震荡以降低反应速度,使生成的银晶粒较小,银膜较为致密,提高形成的银膜的质量。具体实施时,可以通过反应时间来控制形成的银薄膜的厚度。
将质量分数为7%的硫酸铜溶液、酒石酸钾钠溶液和质量分数为37%甲醛溶液进行等体积混合,形成第二混合溶液,并将该第二混合溶液加入到上述第一混合溶液中,形成第三混合溶液,并在该第三混合溶液中于银薄膜上形成铜薄膜。当然,上述溶液的具体百分数以及其它的具体用量只是为了更清楚的理解本申请而进行的举例说明,在具体实施时,可以根据需要进行适当调整,本申请并不以此为限。
相比于现有技术在制作铜膜的源漏极膜层和/或栅极膜层时,通常先通过镀膜工艺形成铜薄膜,再通过双氧水刻蚀铜薄膜使铜薄膜图案化,在制作过程中,由于双氧水溶液挥发,浓度较难控制,存在使铜薄膜图案化较困难的问题。本申请实施例中,在形成薄膜晶体管的源漏极层时,先形成图案化的光刻胶层,再在图案化的光刻胶层上通过银镜反应形成银薄膜,通过铜镜反应形成铜薄膜,在去除图案化的光刻胶时,可以同时去除与光刻胶的图案对应区域的银薄膜和铜薄膜,形成图案化的源漏极层,不需要通过对铜薄膜进行单独的刻蚀工艺,避免由于刻蚀液较易挥发导致的源漏极膜层和/或栅极膜层刻蚀较难的问题,且采用铜镜反应代替镀膜工艺形成源漏极层和/或栅极层,可以简化源漏极膜层和/或栅极层的制作工序,降低源漏极膜层和/或栅极层的制作成本。
为了更清楚的理解本申请实施例提供的图案化的目标膜层的制作方法进行说明,以下以图案化的目标膜层为薄膜晶体管的源漏极层为例,结合附图2至附图6进行如下说明:
步骤一,在有源层4上涂覆具有预设厚度的光刻胶层5。光刻胶层5的厚度具体可以为2~3微米,优选的,例如光刻胶层5的厚度为2.2微米。在有源层4上形成光刻胶层5后的结构示意图如图2所示。需要说明的是,该步骤是以薄膜晶体管为底栅型薄膜晶体管为例进行举例说明,且在有源层4上形成光刻胶层5之前,薄膜晶体管的制作方法还包括,在衬底基板1上形成栅极2,在栅极2上形成栅极绝缘层3,在栅极绝缘层3上形成有源层4。
步骤二,利用掩膜版,通过曝光、显影技术,将光刻胶层5形成与源漏极层的图案相互补的图案,即,将需要形成的源极和漏极的地方的光刻胶去掉,不需要形成源极和漏极的地方的光刻胶留下。将光刻胶5进行图案化后的示意图如图3所示。
步骤三,利用银镜反应,在图案化的光刻胶层上形成银薄膜6。在光刻胶层5上形成银薄膜6后的示意图如图4所示。
步骤四,利用铜镜反应,在银薄膜6上形成铜薄膜7。在银薄膜6上形成铜薄膜7后的示意图如图5所示。
步骤五,通过丙酮溶液,将图案化的光刻胶层5去掉,与此同时,具有光刻胶层5地方的银薄膜6和铜薄膜7也被去掉,形成由部分银薄膜和部分铜薄膜组成的源漏极膜层。去除图案化的光刻胶层后的示意图如图6所示。在具体实施时,可以增加超声、震荡等辅助手段增强剥离的力度。
本申请实施例还提供一种图案化的目标膜层,采用本申请实施例提供的图案化的目标膜层的制作方法制作。
本申请实施例还提供一种薄膜晶体管,包括本申请实施例提供的目标膜层,目标膜层为源漏极和/或栅极。
本申请实施例提供的阵列基板,包括本申请实施例提供的薄膜晶体管。
本申请实施例提供的显示装置,包括本申请实施例提供的阵列基板。
本申请实施例的有益效果如下:本申请实施例提供一种图案化膜层的制作方法,在形成图案化的目标膜层时,先形成与目标膜层的图案相互补的光刻胶层图案,再在图案化的光刻胶层上形成目标层薄膜,进而在去除光刻胶层时,可以同时去除掉与光刻胶层的图案相对应区域的目标层薄膜,进而可以形成目标膜层的图案,相比于现有技术,本申请实施例提供的图案化膜层的制作方法,在形成目标层薄膜后不需要进行对目标层薄膜进行单独刻蚀,进而可以简化图案化膜层的制作工艺,降低图案化膜层的制作成本。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种图案化目标膜层的制作方法,其特征在于,所述制作方法包括:
在衬底基板上形成图案化的光刻胶层,其中,所述光刻胶层的图案为与所述目标膜层的图案互补的图案;
在所述光刻胶层上形成目标层薄膜;
去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应区域的目标层薄膜,形成目标膜层的图案。
2.如权利要求1所述的制作方法,其特征在于,所述目标膜层为薄膜晶体管的源漏极膜层和/或栅极膜层;
所述在所述光刻胶层上形成目标层薄膜,具体包括:在所述光刻胶层上形成至少一层金属层薄膜。
3.如权利要求2所述的制作方法,其特征在于,所述在所述光刻胶层上形成至少一层金属层薄膜,具体包括:
在所述光刻胶层上依次形成银薄膜和铜薄膜。
4.如权利要求3所述的制作方法,其特征在于,在所述光刻胶层上依次形成银薄膜和铜薄膜,具体包括:
通过银镜反应,在所述光刻胶层上形成银薄膜;
通过铜镜反应,在所述银薄膜上形成铜薄膜。
5.如权利要求1-4任一项所述的制作方法,其特征在于,所述去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案,具体包括:
采用丙酮溶液或无水乙醇溶液对所述光刻胶层进行剥离,以去除图案化的所述光刻胶层,并同时去除与所述光刻胶层的图案相对应的区域的目标层薄膜,形成目标膜层的图案。
6.一种薄膜晶体管的制作方法,其特征在于,包括:形成栅极、有源层、源漏极的图形;
其中,采用如权利要求2-5任一项所述的制作方法形成所述栅极和/或源漏极的图形。
7.一种图案化的目标膜层,其特征在于,采用如权利要求1-5任一项所述的制作方法制作。
8.一种薄膜晶体管,其特征在于,包括如权利要求7所述的目标膜层,所述目标膜层为源漏极和/或栅极。
9.一种阵列基板,其特征在于,包括如权利要求8所述的薄膜晶体管。
10.一种显示装置,其特征在于,包括如权利要求9所述的阵列基板。
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