CN106876255B - Sic semiconductor device and preparation method thereof - Google Patents

Abstract

The invention provides a silicon carbide semiconductor device, which can be applied to the high-voltage field and is formed by a plurality of cells in parallel. Each cell structure includes: a p+ substrate; an epitaxial layer located on the substrate; two ion implantation The n-barrier regions are respectively stacked on both sides of the epitaxial layer; the two ion-implanted p+ shielding regions are respectively stacked on each of the n-barrier regions; the two p+ base regions are respectively connected with each the p+ shielding region is adjacent; two n+ source regions are respectively superimposed on each of the p+ base regions and adjacent to the p+ base region; a collector layer is located under the substrate; two Emitters are respectively located on each of the p+ base regions and each of the n+ source regions; a gate oxide layer is located on the two n+ source regions; and a gate electrode is located on the gate oxide layer. In addition, the present invention also provides a preparation method of a silicon carbide semiconductor device. Through ion implantation, a hole potential barrier is formed inside the device, the injection ratio of the emitter is increased, and the conduction performance of the device is greatly improved.

Description

Silicon carbide semiconductor device and preparation method thereof

technical field

The invention belongs to the field of silicon carbide semiconductor devices, in particular to a silicon carbide semiconductor device and a preparation method thereof.

Background technique

Silicon carbide (SiC), as an emerging third-generation semiconductor material, has excellent physical and electrical properties. It has broad application prospects in electric vehicles, rail transit, smart grid, green energy and other fields.

SiC IGBT (Insulated Gate Bipolar Transistor) device has the characteristics of fast switching speed of MOSFET (Metal Oxide Semi Field Effect Transistor) device and low on-resistance of BJT (Bipolar Transistor) device, and has a wide range of applications in the field of power electronics prospect. By utilizing the modulation effect of the drift region conductance, the drift region resistance of the IGBT is greatly reduced relative to that of the MOSFET. As a power device, IGBT requires a thicker, lower-doped epitaxial drift region to support higher voltage, so the drift region voltage drop of SiC IGBT devices is still high, which limits the application of SiC IGBT devices.

SUMMARY OF THE INVENTION

(1) Technical problems to be solved

The purpose of the present invention is to provide a silicon carbide semiconductor device and a preparation method thereof to solve at least one of the above technical problems.

(2) Technical solutions

According to an aspect of the present invention, a silicon carbide semiconductor device is provided, which is formed by a plurality of cells in parallel, and each of the cell structures includes:

a p+ substrate;

an epitaxial layer on the p+ substrate;

Two ion-implanted n-barrier regions are respectively stacked on both sides of the epitaxial layer;

Two ion-implanted p+ shielding regions are respectively superimposed on each of the n-barrier regions;

two p+ base regions, respectively adjacent to each of the p+ shielding regions;

Two n+ source regions are respectively stacked on each of the p+ base regions and adjacent to the p+ base regions.

Preferably, the cell structure further includes:

a collector layer under the p+ substrate;

two emitters, respectively located on each of the p+ base regions and each of the n+ source regions;

a gate oxide layer located on the two n+ source regions;

a gate electrode on the gate oxide layer.

Preferably, the implanted ions in the n barrier region are N or P, and the doping concentration of the implanted ions is 5×10 ¹⁶ cm ^-3 to 3×10 ¹⁷ cm ^-3 , where 3×10 ¹⁷ can also be expressed as 3.00 E+017.

Preferably, the distance between the two n-barrier regions (ie, the potential barrier distance) is 1 μm˜8 μm.

Preferably, the implanted ions of the p+ shielding region are Al or B, and the doping concentration of the implanted ions is 5×10 ¹⁷ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ .

Preferably, the distance between the two p+ shielding regions is 8 μm˜16 μm.

Preferably, the epitaxial layer includes: an n buffer layer and an n-drift region, the n buffer layer is located above the p+ substrate, and the n-drift region is located above the n buffer layer; the thickness of the n buffer layer is 1 μm～ 5μm, the implanted ions include N or P, and the doping concentration of the implanted ions is 5×10 ¹⁶ cm ^-3 to 1×10 ¹⁸ cm ^-3 ; the thickness of the n-drift region is greater than 100 μm, the implanted ions include N or P, and the implanted ions are The doping concentration is less than 5×10 ¹⁴ em ⁻³ .

According to another aspect of the present invention, there is also provided a preparation method of a silicon carbide semiconductor device, comprising:

S1, growing an epitaxial layer on the p+ substrate;

S2, forming n barrier regions on both sides of the epitaxial layer by ion implantation on the epitaxial layer;

S3, forming a p+ shielding region on each of the n barrier regions by ion implantation;

S4, forming an n+ source region by ion implantation on each of the p+ shielding regions;

S5, forming a p+ base region by ion implantation on the outer side of each n+ source region.

Preferably, after step S5, it also includes:

S61, growing a gate oxide layer on the n+ source region;

S62, growing emitters on both sides of the gate oxide layer;

S63, growing a gate electrode on the gate oxide layer;

S64, growing a collector layer under the p+ substrate.

Preferably, after the ion implantation in the steps S2 to S5, all are annealed and activated, and the annealing and activation temperatures are all above 1500°C.

(3) Beneficial effects

Compared with conventional IGBT devices, the silicon carbide semiconductor device provided by the present invention has the following advantages:

1. The silicon carbide semiconductor device can be applied in the high voltage field and has good conduction and switching characteristics. The structure has the characteristics that the preparation process is compatible with the existing process, and the conduction characteristic of the device is obviously better than that of the conventional silicon carbide IGBT.

2. On the basis of conventional IGBT devices, the present invention uses ion implantation to form a hole potential barrier inside the device, improve the emitter injection ratio, form an injection enhancement effect, and greatly improve the conduction performance of the device.

Description of drawings

1 is a schematic diagram of a cell structure according to an embodiment of the present invention;

Fig. 2 is the step flow chart of the embodiment of the present invention;

3 is a schematic diagram showing the comparison of the output characteristic curves of the silicon carbide device according to the embodiment of the present invention and the conventional silicon carbide IGBT device;

FIG. 4A is an electron distribution diagram at the top of the silicon carbide device in the forward conduction state of the silicon carbide device according to the embodiment of the present invention;

Fig. 4B is the electron distribution diagram of the top of the device in the forward conduction state of the conventional silicon carbide IGBT device;

FIG. 5 is a schematic diagram of the blocking voltage of a silicon carbide device according to an embodiment of the present invention changing with the doping of the n-barrier region and the barrier spacing.

Detailed ways

In the present invention, directional terms such as "upper", "lower", "adjacent", "lower" or "above" only refer to the directions of the attached drawings. "Under" or "over" means both contact and non-contact with a single element or elements. These directional terms are used to illustrate, not to limit the invention.

In order to reduce the high drift region resistance of the silicon carbide IGBT device, reduce the turn-on voltage drop of the device, and improve the conduction capability of the silicon carbide IGBT device. The invention provides a silicon carbide device structure, which can be applied to high-voltage conditions such as traction drives and smart grids, etc. In addition, the device can greatly increase the carrier concentration in the drift region during the conduction process of the device, so that the device conducts Extremely low drift region on-resistance during turn-on.

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In one aspect of the embodiment of the present invention, a silicon carbide semiconductor device is provided, which is formed by a plurality of cells in parallel. FIG. 1 is a schematic diagram of the cell structure of the embodiment of the present invention. As shown in FIG. 1 , each cell structure includes : a p+ substrate 1; an epitaxial layer located on the p+ substrate 1, including an n buffer layer 2 and an n-drift region 3; two ion-implanted n barrier regions 8, respectively stacked on the On both sides of the epitaxial layer; two ion-implanted p+ shielding regions 7 are respectively superimposed on each of the n barrier regions 8; two p+ base regions 6 are respectively adjacent to each of the p+ shielding regions 7; Two n+ source regions 5 are respectively stacked on the p+ base regions 6 and adjacent to the p+ base regions 6; a collector layer 10 is located under the p+ substrate 1; two An emitter 9 is located on each of the p+ base regions 6 and each of the n+ source regions 5; a gate oxide layer 4 is located on the two n+ source regions 5; a gate electrode 11 is located on the gate oxide above layer 4.

The p+ substrate 1, the p+ shield region 7, the n+ source region 5 and the p+ base region 6 are heavily doped regions, the n buffer layer 2 and the n barrier region 8 are medium doped regions, and the n - Drift region 3 is a lightly doped region.

The embodiment of the present invention provides a silicon carbide device structure that can work under 30kV. The p+ substrate 1 of the embodiment of the present invention is selected from the p+ substrate of a conventional IGBT device, and at the same time, the thickness of the gate oxide layer 4 is selected to be 40 nm.

The n-barrier region 8 is formed by annealing activation after ion implantation, N or P can be selected as the implanted ions, and the doping concentration of the implanted ions is 5×10 ¹⁶ cm ^-3 to 3×10 ¹⁷ cm ^-3 . The spacing W _n of the n-barrier regions 8 is 1 μm to 8 μm. By changing the doping concentration of the n-barrier regions 8 and the spacing of the n-barrier regions 8 , an optimization can be made between the on-resistance and the turn-off loss. The n-barrier region 8 is relatively thin, so only one ion implantation is needed to form a buried layer. The top of the buried layer is 0.7 μm away from the upper surface of the SiC wafer, and the bottom is 0.9 μm away from the upper surface of the wafer. In the embodiment of the present invention, P is selected as the implanted ion, and the doping concentration of P is 2×10 ¹⁷ cm ⁻³ , and the distance W _n between the two n barrier regions 8 is selected as 4 μm.

The p+ shielding region 7 is formed by annealing and activation after ion implantation. Al or B can be selected as the implanted ions. The doping concentration of the implanted ions is 5×10 ¹⁷ cm ^-3 to 1×10 ¹⁹ cm ^-3 . By changing the p+ shielding With the doping concentration of region 7, a suitable threshold voltage can be obtained. The spacing W _p+ of the two p+ shielding regions 7 is 8 μm to 16 μm, which affects the channel density of the device and the resistance of the JFET region. By optimizing the spacing W _p+ of the p+ shielding regions 7 and the doping concentration of the implanted ions, conduction can be obtained. Optimum device structure. In addition, the device relies on the depletion of the p+ shielding region 7 to isolate the n-drift region 3 and the n+ source region 5, and the width of the depletion region decreases after the positive gate voltage is applied to form an accumulation channel. Compared with the inversion channel, the accumulation channel has higher channel carrier mobility. The p+ shielding region 7 is relatively thick, so it is necessary to form a uniformly doped buried layer through three ion implantations. In the embodiment of the present invention, Al is selected as the implanted ions, and the doping concentration of Al is 2×10 ¹⁸ cm ⁻³ . The two The spacing W _p+ of the p+ shielding region 7 is selected to be 10 μm, the top of the buried layer is 0.2 μm from the upper surface of the SiC wafer, and the bottom is 0.7 μm from the upper surface of the wafer.

The n+ source region 5 and the p+ base region 6 are also formed by annealing activation after ion implantation. The n+ source region 5 selects N or P as the implanted ions, and the distance W _n+ between the two n+ source regions 5 is 12-18 μm , the p+ base region 6 selects Al or B as the implanted ions, and the doping concentrations of the implanted ions are all greater than 1×10 ¹⁹ cm ⁻³ . In the embodiment of the present invention, the n+ source region 5 selects P as the implanted ions, the distance W _n+ between the two n+ source regions 5 is 12 μm, and the doping concentration of the implanted ions is 5×10 ¹⁹ cm ⁻³ , the p+ base region 6. Al is selected as the implanted ion, and the doping concentration of the implanted ion is 5×10 ¹⁹ cm ⁻³ , and the width is 2 μm.

The epitaxial layer is grown on the p+ substrate 1 by means of epitaxy, including: an n buffer layer 2 and an n-drift region 3, the n buffer layer 2 is located above the p+ substrate 1, and the n-drift region 3 is located in the n buffer Above layer 2. The thickness of the n buffer layer 2 is 1 μm˜5 μm, the implanted ions are N or P, and the doping concentration of the implanted ions is 5×10 ¹⁶ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ ; the thickness of the n-drift region 3 is greater than 100 μm , the implanted ions are N or P, and the doping concentration of the implanted ions is less than 5×10 ¹⁴ cm ^-3 . And corresponding to a device with a higher blocking voltage requirement, the thickness of the n-drift region 3 is selected to be thicker and the doping is lower. In the embodiment of the present invention, the thickness of the n-buffer layer 2 is 2 μm, the implanted ions are P, and the doping concentration of the implanted ions is 2×10 ¹⁷ cm ⁻³ ; the thickness of the n-drift region 3 is 250 μm, and the implanted ions are P, The doping concentration of the implanted ions was 1.8×10 ¹⁴ cm ^-3 .

In addition, in this embodiment, the depth of the p+ base region 6 is greater than that of the n+ source region 5, which can reduce the latch-up effect.

Another aspect of the embodiment of the present invention further provides a method for preparing a silicon carbide semiconductor device. FIG. 2 is a flow chart of the steps of the embodiment of the present invention. As shown in FIG. 2 , the method includes:

S1, growing an epitaxial layer on the p+ substrate;

S2, forming n barrier regions on both sides of the epitaxial layer by ion implantation on the epitaxial layer;

S3, forming a p+ shielding region on each of the n barrier regions by ion implantation;

S4, forming an n+ source region by ion implantation on each of the p+ shielding regions;

S5 , forming a p+ base region by ion implantation on the outer side of each n+ source region, wherein the outer side refers to both ends of the device.

Wherein, the n barrier region, p+ shield region, n+ source region and p+ base region are formed by annealing activation after ion implantation, and the activation annealing temperature is above 1500°C. The activation annealing temperature in the embodiment of the present invention is 1800°C.

Further, after step S5, it also includes:

S61, growing a gate oxide layer on the n+ source region;

S62, growing emitters on both sides of the gate oxide layer;

S63, growing a gate electrode on the gate oxide layer;

S64, growing a collector layer under the p+ substrate.

Wherein, the fabrication process of the gate oxide layer may be thermal oxidation, and the fabrication process of the electrode may be evaporation electrode or sputtering. In the embodiment of the present invention, an evaporation electrode is used to fabricate the gate electrode, the emitter electrode and the collector electrode.

3 is a schematic diagram showing the comparison of the output characteristic curves of the silicon carbide device according to the embodiment of the present invention and the conventional silicon carbide IGBT device, ^both of which have the same epitaxial layer structure. On-resistance is reduced by 45% compared to conventional SiC IGBT devices. It can be seen that, compared with the common silicon carbide IGBT device, the silicon carbide semiconductor device of the present invention has the characteristics of significantly reduced on-resistance.

4A is the electron distribution diagram of the top of the device in the forward conduction state of the silicon carbide device according to the embodiment of the present invention, and FIG. 4B is the electron distribution diagram of the top of the device of the conventional silicon carbide IGBT device in the forward conduction state, as shown in FIGS. 4A and 4B As shown in 4B, due to the existence of the built-in potential between the n-barrier region and the n-drift region, in the on-state, the hole current is hindered by the built-in potential, so that the emitter electron current of the device of the present invention and the hole Compared with the conventional IGBT device, the current ratio is increased, resulting in the enhancement effect of emitter injection, resulting in the carrier concentration in the drift region of the device of the present invention is higher than that of the conventional silicon carbide IGBT device, that is, the conductance modulation phenomenon in the device drift region is more obvious.

FIG. 5 is a schematic diagram of the blocking voltage of a silicon carbide device according to an embodiment of the present invention changing with the doping of the n-barrier region and the barrier spacing. As shown in FIG. 5 , with the increase of the doping of the n-barrier region, the inner The increase of the maximum field strength reduces the blocking characteristics of the device; as the barrier spacing decreases, the maximum field strength in the gate oxide layer increases, which also reduces the blocking characteristics of the device. In addition, the appropriate doping concentration and barrier spacing of implanted ions in the n-barrier region can be obtained through simulation optimization.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principle of the present invention, any modifications, equivalent replacements, improvements, etc. made should be included within the protection scope of the present invention.

Claims (8)

1. a kind of sic semiconductor device, which is characterized in that formed by multiple cellular parallel connections, each structure cell includes:

One p+ substrate；

One epitaxial layer is located at the p+ substrate；

The barrier region n of two ion implantings, is stacked and placed on two sides on the epitaxial layer respectively；

The blind zone p+ of two ion implantings is located at the both ends of each barrier region n, and between the blind zone p+ away from From greater than the distance between described barrier region n；

Two n+ source regions are stacked in respectively on each blind zone p+；

Two base areas p+ are located at the two sides of the blind zone p+, adjacent with each blind zone p+；

One collector layer is located under the p+ substrate；

Two emitters are located on each base area p+ and each n+ source region；

One gate oxide is located on described two n+ source regions；

One gate electrode is located on the gate oxide.

2. semiconductor devices according to claim 1, which is characterized in that the injection ion of the barrier region n be nitrogen or Phosphorus, the doping concentration for injecting ion is 5 × 10¹⁶cm^-3~3 × 10¹⁷cm^-3。

3. semiconductor devices according to claim 1, which is characterized in that the spacing of two barrier regions n is 1 μm~8 μ m。

4. semiconductor devices according to claim 1, which is characterized in that the injection ion of the blind zone p+ be aluminium or Boron, the doping concentration for injecting ion is 5 × 10¹⁷cm^-3~1 × 10¹⁹cm^-3。

5. semiconductor devices according to claim 1, which is characterized in that the spacing of two blind zones p+ be 8 μm~ 16μm。

6. semiconductor devices according to claim 1, which is characterized in that the epitaxial layer includes: n buffer layer and n- drift Area, the n buffer layer are located above the p+ substrate, and the drift region n- is located above n buffer layer；The n buffer layer thickness is 1 μm ~5 μm, injection ion includes nitrogen or phosphorus, and the doping concentration for injecting ion is 5 × 10¹⁶cm^-3~1 × 10¹⁸cm^-3；The drift region n- Thickness is greater than 100 μm, and injection ion includes nitrogen or phosphorus, injects the doping concentration of ion less than 5 × 10¹⁴cm^-3。

7. a kind of preparation method of sic semiconductor device, which is characterized in that comprising steps of

S1, in p+ substrate growing epitaxial layers；

S2, pass through ion implanting on said epitaxial layer there in the epitaxial layer two sides formation barrier region n；

S3, the blind zone p+ is formed by ion implanting in the two sides of each barrier region n, the distance between described blind zone p+ is big In the distance between described barrier region n；

S4, pass through ion implanting formation n+ source region on each blind zone p+；

S5, the base area p+ is formed by ion implanting in the two sides of each n+ source region, the base area p+ is adjacent with each n+ source region；

After step S5 further include:

S61, pass through growth gate oxide in the n+ source region；

S62, emitter is grown in the gate oxide two sides；

S63, gate electrode is grown on the gate oxide；

S64, collector layer is grown below the p+ substrate.

8. the method according to the description of claim 7 is characterized in that annealing swashs after step S2~S5 intermediate ion injection It is living, and the temperature for activation of annealing is 1500 DEG C or more.