CN106847762B - 半导体装置和半导体封装件 - Google Patents

半导体装置和半导体封装件 Download PDF

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Publication number
CN106847762B
CN106847762B CN201611025660.0A CN201611025660A CN106847762B CN 106847762 B CN106847762 B CN 106847762B CN 201611025660 A CN201611025660 A CN 201611025660A CN 106847762 B CN106847762 B CN 106847762B
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solder bump
semiconductor device
connection pad
opening
decoupling capacitor
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CN106847762A (zh
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李灿浩
郑显秀
朴明洵
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

公开了一种半导体装置和一种半导体封装件。所述半导体装置包括：基底；去耦电容器，设置在基底上；第一连接焊盘，与去耦电容器竖直地叠置；钝化层，暴露第一连接焊盘的一部分；以及第一焊料凸块，设置在第一连接焊盘上并覆盖钝化层的顶表面的一部分。

Description

半导体装置和半导体封装件
本专利申请要求于2015年12月3日提交到韩国知识产权局的第10-2015-0171647号韩国专利申请的优先权，该专利申请的公开内容通过引用全部包含于此。
技术领域
实施例涉及一种半导体装置，更具体地，涉及一种包括与集成电路竖直地叠置的焊料凸块的半导体装置。
背景技术
由于半导体装置的集成度增加，所以正需要高容量且高速的半导体装置。
半导体装置的操作电路的数目可以与半导体装置的集成度成比例地增加。在这种情况下，在半导体装置的读操作和写操作期间，在电源电压和接地电压中会出现起伏噪声。要解决这个问题，半导体装置可以包括用于过滤在诸如电源电压和接地电压的工作电压中存在的噪声的电源去耦电容器。
发明内容
实施例包括半导体装置，所述半导体装置包括：基底；去耦电容器，设置在基底上；第一连接焊盘，与去耦电容器竖直地叠置；钝化层，暴露第一连接焊盘的一部分；以及第一焊料凸块，设置在第一连接焊盘上并覆盖钝化层的顶表面的一部分。
实施例包括半导体装置，所述半导体装置包括：基底；去耦电容器，设置在基底上；第一焊料凸块，与去耦电容器竖直地叠置；以及第二焊料凸块，从去耦电容器偏移，其中，第一焊料凸块的宽度大于第二焊料凸块的宽度。
实施例包括半导体封装件，所述半导体封装件包括：封装基底；半导体芯片，包括去耦电容器和钝化层；多个焊料凸块，将半导体芯片电连接到封装基底，其中：焊料凸块中的第一焊料凸块与去耦电容器竖直地对齐并延伸到钝化层上方；焊料凸块中的第二焊料凸块与钝化层分隔开。
附图说明
基于附图和随附的具体实施方式，实施例将变得更加明显。
图1是示出根据一些实施例的半导体装置的平面图。
图2是沿图1的线A-A’和B-B’截取的剖视图。
图3是沿图1的线A-A’和B-B’截取的剖视图。
图4是示出根据一些实施例的半导体装置的平面图。
图5是沿图4的线C-C’和D-D’截取的剖视图。
图6是沿图4的线C-C’和E-E’截取的剖视图。
图7是示出根据一些实施例的半导体封装件的剖视图。
具体实施方式
现在将参照其中示出具体实施例的附图在下文中更加充分地描述实施例。
图1是示出根据一些实施例的半导体装置的平面图。参照图1，半导体装置1可以包括单元区CR和外围电路区PR。存储单元可以设置在单元区CR中。字线驱动器、感测放大器、行解码器、列解码器和控制电路可以设置在外围电路区PR中。在一些实施例中，单元区CR可以包括动态随机存取存储(DRAM)单元、静态随机存取存储(SRAM)单元、闪存单元、相变随机存取存储(PRAM)单元、电阻式随机存取存储(ReRAM)单元、铁电随机存取存储(FeRAM)单元或磁性随机存取存储(MRAM)单元。在某些实施例中，单元区CR可以包括嵌入在诸如专用集成电路(ASIC)、图形处理单元(GPU)或中央处理单元(CPU)的逻辑电路中的存储单元。
焊料凸块110和130可以设置在外围电路区PR中。焊料凸块110和130可以包括第一焊料凸块110和第二焊料凸块130。第一焊料凸块110和第二焊料凸块130可以设置在外围电路区PR的中心区中。第一焊料凸块110和第二焊料凸块130可以在第一方向x上彼此分隔开。可以设置多个第一焊料凸块110，可以设置多个第二焊料凸块130。第一焊料凸块110和第二焊料凸块130可以沿与第一方向x垂直的第二方向y布置，以构成与第二方向y平行的多个列。然而，实施例不限于第一焊料凸块110和第二焊料凸块130的这种布置。
图2是沿图1的线A-A’和B-B’截取的剖视图。参照图1和图2，半导体装置1可以包括基底10、层间绝缘层20a和20b、金属互连30a和30b、过孔40、去耦电容器DC、连接焊盘70a和70b、钝化层80以及焊料凸块110和130。将一起描述外围电路区PR和单元区CR，来详细描述半导体装置1。
基底10可以包括由第一器件隔离层18限定的第一有源区ACT1和由第二器件隔离层19限定的第二有源区ACT2。第一器件隔离层18和第一有源区ACT1可以设置在外围电路区PR中，第二器件隔离层19和第二有源区ACT2可以设置在单元区CR中。源区/漏区(未示出)可以设置在第一有源区ACT1中和第二有源区ACT2中。基底10可以是体硅基底、绝缘体上硅(SOI)基底、锗基底、绝缘体上锗(GOI)基底、硅锗基底或具有通过执行选择性外延生长(SEG)工艺获得的外延薄层的基底等。
至少一个第一晶体管TR1和至少一个第二晶体管TR2可以设置在基底10上。第一晶体管TR1可以设置在外围电路区PR中，第二晶体管TR2可以设置在单元区CR中。第一晶体管TR1可以是包括在设置在外围电路区PR中的控制电路中的开关元件，第二晶体管TR2可以是包括在设置在单元区CR中的存储单元中的开关元件。
第一层间绝缘层20a和第二层间绝缘层20b可以设置在基底10上。第一层间绝缘层20a可以设置在外围电路区PR中。第一层间绝缘层20a可以包括在基底10上顺序堆叠的第一下部层间绝缘层21a和第一上部层间绝缘层22a。第二层间绝缘层20b可以设置在单元区CR中。第二层间绝缘层20b可以包括在基底10上顺序堆叠的第二下部层间绝缘层21b和第二上部层间绝缘层22b。第一层间绝缘层20a和第二层间绝缘层20b中的每个可以包括氧化硅层、氮化硅层或氮氧化硅层等。另外，第一下部层间绝缘层21a、第一上部层间绝缘层22a、第二下部层间绝缘层21b和第二上部层间绝缘层22b可以由相同或不同的材料形成。
第一金属互连30a可以设置在第一上部层间绝缘层22a上，第二金属互连30b可以设置在第二上部层间绝缘层22b上。第一金属互连30a可以包括至少一个第一下部金属互连31和至少一个第一上部金属互连32。第一下部金属互连31和第一上部金属互连32可以被构造为将可以从外部系统提供的电源电压和/或数据传输到单元区CR。第一金属互连30a和第二金属互连30b可以包括金(Au)、铝(Al)、铬(Cr)、镍(Ni)、钨(W)、钛(Ti)、钽(Ta)、钨化钛(TiW)、铬化镍(NiCr)、氮化铝(AlNx)、氮化钛(TiNx)、氮化钛铝(TiAlxNy)、氮化钽(TaNx)、硅化钨(WSix)、硅化钛(TiSix)、硅化钴(CoSix)以及它们的任何合金等中的至少一种。
过孔40可以被构造为使第一金属互连30a、去耦电容器DC以及连接焊盘70a和70b彼此电连接。过孔40可以包括将去耦电容器DC连接到第一下部金属互连31中的一个的第一过孔41、将第一下部金属互连31连接到第一上部金属互连32的第二过孔42以及将第一上部金属互连32中的一个连接到连接焊盘70a和70b中的每个的第三过孔43。第一过孔41、第二过孔42和第三过孔43可以电连接到第一金属互连30a以及连接焊盘70a和70b，因此从外部系统提供的电源电压和/或数据可以通过连接焊盘70a和70b、第一金属互连30a以及过孔41、42和43传输到单元区CR。第一过孔41、第二过孔42和第三过孔43可以包括诸如铝(Al)、铜(Cu)和/或钨(W)的导电金属。虽然过孔和金属互连的具体数目已经被用作示例，但是在其它实施例中，每个的数目可以不同。
去耦电容器DC可以设置在外围电路区PR的第一下部层间绝缘层21a中。去耦电容器DC可以通过第一过孔41电连接到第一下部金属互连31。去耦电容器DC可以通过第一接触插塞55电连接到第一有源区ACT1的源区/漏区(未示出)。去耦电容器DC可以包括上电极51、介电层52和下电极53。介电层52可以设置在上电极51和下电极53之间。上电极51和下电极53中的每个可以包括掺杂的半导体材料(例如，掺杂的硅)、导电金属氮化物(例如，氮化钛、氮化钽或氮化钨)、金属(例如，钌、铱、钛或钽)和导电金属氧化物(例如，氧化铱)中的至少一种。上电极51可以包括与下电极53的导电材料相同的导电材料，或者可以包括与下电极53的导电材料不同的导电材料。介电层52可以包括氧化物(例如，氧化硅)、氮化物(例如，氮化硅)、氮氧化物(例如，氮氧化硅)、高k介电材料以及铁电材料等中的至少一种。
在一些实施例中，可以在半导体装置1的外围电路区PR中设置多个去耦电容器DC。当半导体装置1运转时，去耦电容器DC可以过滤存在于诸如电源电压和接地电压的工作电压中或所述工作电压之间的噪声。因此，即使半导体装置1以高速运转，去耦电容器DC也可以提高施加到半导体装置1的工作电压的稳定性。
至少一个存储元件60可以设置在单元区CR的第二下部层间绝缘层21b中。存储元件60可以通过第二接触插塞65电连接到第二有源区ACT2的源区/漏区(未示出)。位线BL可以设置在存储元件60和第二晶体管TR2之间。存储元件60可以包括用于DRAM单元的电容器、用于PRAM单元的相变元件、用于ReRAM单元的可变电阻元件、用于FeRAM单元的电容器、用于MRAM单元的磁性元件(例如，磁性隧道结(MTJ)元件)或其他类型的存储单元。可选择地，闪存单元或逻辑元件可以设置在单元区CR中。
连接焊盘70a和70b可以设置在外围电路区PR的第一上部层间绝缘层22a上。连接焊盘70a和70b可以包括第一连接焊盘70a和第二连接焊盘70b。第一连接焊盘70a可以与去耦电容器竖直地叠置。第二连接焊盘70b可以不与去耦电容器DC竖直地叠置，而是可以从去耦电容器DC横向偏移。第一连接焊盘70a和第二连接焊盘70b可以连接到第三过孔43。连接焊盘70a和70b可以包括诸如铜(Cu)、铝(Al)、镍(Ni)和它们的任何合金等的各种金属材料中的至少一种。
钝化层80可以设置在外围电路区PR的第一上部层间绝缘层22a上。钝化层80可以具有暴露在半导体装置1外面的顶表面80a、暴露第一连接焊盘70a的第一开口81和暴露第二连接焊盘70b的第二开口82。第一开口81可以具有第一宽度d1，第二开口82可以具有第二宽度d2。第一开口81可以暴露第一连接焊盘70a的顶表面的一部分，第二开口82可以暴露第二连接焊盘70b的顶表面的一部分。例如，钝化层80可以包括聚酰亚胺。钝化层80可以保护第一连接焊盘70a和第二连接焊盘70b免受外部污染，并且可以防止在第一连接焊盘70a和第二连接焊盘70b之间电短路。
焊料凸块110和130可以设置在连接焊盘70a和70b上。焊料凸块110和130可以包括设置在第一连接焊盘70a上的第一焊料凸块110和设置在第二连接焊盘70b上的第二焊料凸块130。第一焊料凸块110可以与去耦电容器DC竖直地叠置。第二焊料凸块130可以不与去耦电容器DC竖直地叠置，而是可以从去耦电容器DC横向偏移。第一焊料凸块110可以从第一连接焊盘70a的顶表面向钝化层80的顶表面80a延伸，以覆盖钝化层80的顶表面80a的一部分。第一焊料凸块110可以设置在钝化层80的第一开口81中并且可以填充第一开口81。第二焊料凸块130可以与钝化层80分隔开并且可以设置在第二连接焊盘70b上。第二焊料凸块130可以设置在钝化层80的第二开口82中。可以向第一焊料凸块110施加电源电压或接地电压，可以向第二焊料凸块130施加数据信号。因此，形成在基底10上电路(无论在单元区CR中还是在外围电路区PR中)可以电连接到第一焊料凸块110并被构造为通过包括第一焊料凸块110的路径接收电力。另外，所述电路可以电连接到第二焊料凸块130并被构造为通过包括第二焊料凸块130的路径接收数据信号。
第一焊料凸块110可以包括第一支柱112和第一焊料114，第二焊料凸块130可以包括第二支柱132和第二焊料134。第一支柱112和第二支柱132中的每个可以具有圆柱形形状或其它形状。第一支柱112可以从第一连接焊盘70a的顶表面向钝化层80的顶表面80a延伸，以覆盖钝化层80的顶表面80a的一部分。例如，第一支柱112和第二支柱132可以包括铜(Cu)，第一焊料114和第二焊料134可以包括包含锡(Sn)、银(Ag)、铜(Cu)、镍(Ni)、铋(Bi)、铟(In)、锑(Sb)和铈(Ce)等中的至少一种的合金。第一支柱112可以具有第三宽度d3，第二支柱132可以具有第四宽度d4。第三宽度d3可以大于第四宽度d4。第三宽度d3可以大于第一开口81的第一宽度d1，第四宽度d4可以小于第二开口82的第二宽度d2。
当安装半导体装置1时，可以向第一焊料凸块110和第二焊料凸块130施加压力。通过施加到第一焊料凸块110和第二焊料凸块130的压力，会向设置在半导体装置1内的去耦电容器DC施加应力。根据一些实施例，第一焊料凸块110可以大于第二焊料凸块130，因此，能够减小或最小化施加到与第一焊料凸块110竖直叠置的去耦电容器DC的应力。另外，由于第一焊料凸块110覆盖钝化层80的顶表面80a的一部分，所以施加到第一焊料凸块110的压力可以分散到钝化层80中。因此，能够保护与第一焊料凸块110竖直叠置的去耦电容器DC。
图3是沿图1的线A-A’和B-B’截取的剖视图。在下文中，为了容易和方便解释的目的，将省略或简要提及对与图2的实施例中相同的元件的描述。
参照图1和图3，第一焊料凸块110’可以设置在第一连接焊盘70a上，第二焊料凸块135可以设置在第二连接焊盘70b上。第一焊料凸块110’和第二焊料凸块135中的每个可以是可控塌陷芯片连接(C4)凸块。第一焊料凸块110’可以从第一连接焊盘70a的顶表面向钝化层80的顶表面80a延伸，以覆盖钝化层80的顶表面80a的一部分。例如，第一焊料凸块110’和第二焊料凸块135可以包括包含锡(Sn)、银(Ag)、铜(Cu)、镍(Ni)、铋(Bi)、铟(In)、锑(Sb)和铈(Ce)等中的至少一种的合金。
第一焊料凸块110’的最大宽度可以是第五宽度d5，第二焊料凸块135的最大宽度可以是第六宽度d6。第五宽度d5可以大于第六宽度d6。另外，第五宽度d5可以大于第一开口81的第一宽度d1，第六宽度d6可以小于第二开口82的第二宽度d2。其宽度大于第二焊料凸块135的宽度的第一焊料凸块110’可以设置为与去耦电容器DC竖直地叠置，从而减小或最小化施加到去耦电容器DC的应力。
图4是示出根据一些实施例的半导体装置的平面图。图5是沿图4的线C-C’和D-D’截取的剖视图，图6是沿图4的线C-C’和E-E’截取的剖视图。在下文中，为了容易和方便解释的目的，将省略或简要提及对与图1和图2的实施例中相同的元件的描述。
参照图4至图6，半导体装置2可以包括其中设置有第一焊料凸块110的第一横截面(即，沿线D-D’截取的横截面)和其中设置有第二焊料凸块130的第二横截面(即，沿线E-E’截取的横截面)。第一焊料凸块110和第二焊料凸块130可以布置为在外围电路区PR中构成一列。可以包括多个第一焊料凸块110和多个第二焊料凸块130。第一焊料凸块110和第二焊料凸块130可以彼此分隔开并可以沿第二方向y交替地布置。可以向第一焊料凸块110施加电源电压或接地电压，可以向第二焊料凸块130施加数据信号。
在示出(沿线D-D’截取的)第一横截面的图5中，半导体装置2可以包括与第一焊料凸块110竖直地叠置的第一去耦电容器DC1和不与第一焊料凸块110竖直地叠置的第二去耦电容器DC2。第二去耦电容器DC2可以从第一焊料凸块110横向偏移。在示出(沿线E-E’截取的)第二横截面的图6中，半导体装置2可以包括不与第二焊料凸块130竖直地叠置而是从第二焊料凸块130横向偏移的第三去耦电容器DC3。
根据一些实施例，半导体装置2可以包括从第一焊料凸块110横向偏移的第二去耦电容器DC2和设置在第一焊料凸块110下方的第一去耦电容器DC1。换句话说，可以在具有有限区域的外围电路区PR中设置多个去耦电容器，因此能够有效地过滤当施加工作电压(例如，电源电压和接地电压)时产生的噪声。因此，即使半导体装置2以高速运转，也可以通过去耦电容器DC1、DC2和DC3来提高施加到半导体装置2的工作电压的稳定性。
虽然具有关于图2描述的结构的焊料凸块110已经被描述为包括在半导体装置2中，但是在其它实施例中，可以使用具有关于图3描述的结构的焊料凸块110’。同样地，在一些实施例中，半导体装置2中可以包括具有关于图3描述的结构的焊料凸块135。
图7是示出根据一些实施例的半导体封装件的剖视图。图7示出根据一些实施例的包括半导体装置的半导体封装件。参照图7，半导体封装件P可以包括封装基底100、半导体芯片200和模层300。
封装基底100可以是印刷电路板(PCB)或其上可以安装半导体芯片200的其它基底，封装基底100具有顶表面100a和与顶表面100a相对的底表面100b。可以在封装基底100的顶表面100a上设置至少一个基底焊盘102，可以在封装基底100的底表面100b上设置至少一个外部端子104。例如，外部端子104可以是焊球。例如，外部端子104可以包括包含锡(Sn)、银(Ag)、铜(Cu)、镍(Ni)、铋(Bi)、铟(In)、锑(Sb)和铈(Ce)等中的至少一种的合金。
半导体芯片200可以通过第一焊料凸块110和第二焊料凸块130安装在封装基底100的顶表面100a上。例如，半导体芯片200可以是根据各种实施例的图1至图6的半导体装置1和半导体装置2中的一个。半导体芯片200可以是逻辑芯片、存储芯片或它们的组合。第一焊料凸块110的尺寸可以大于第二焊料凸块130的尺寸。可以向第一焊料凸块110施加电源电压，可以向第二焊料凸块130施加数据信号。
模层300可以覆盖封装基底100的顶表面100a和半导体芯片200。模层300可以包括诸如环氧树脂塑封料(EMC)的绝缘聚合物材料。
由于第一焊料凸块110的尺寸大于第二焊料凸块130的尺寸，所以能够减小或最小化当半导体芯片200安装在封装基底100上时施加到包括在半导体芯片200中的去耦电容器的应力。因此，可以保护包括在半导体芯片200中的元件。
然而，实施例不限于在以上实施例中描述的第一焊料凸块110和第二焊料凸块130的布置和数目。另外，可以对单元区CR的结构进行各种修改。
根据一些实施例，可以在与去耦电容器竖直地叠置的连接焊盘上设置大于另一焊料凸块的焊料凸块，从而减小或最小化施加到去耦电容器的应力。
根据一些实施例，可以在与去耦电容器竖直地叠置的连接焊盘上设置钝化层，焊料凸块可以覆盖钝化层的一部分和连接焊盘。因此，施加到焊料凸块的应力可以在钝化层中被分散。
尽管已经参照具体的实施例描述了实施例，但是对于本领域技术人员将明显的是，可以在不脱离所述精神和范围的情况下做出各种改变和修改。因此，应当理解的是，以上描述的具体实施例不是限制性的而是说明性的。因此，所述范围将由权利要求书和其等同物的最宽可允许解释来确定，不应被前面的描述约束或限制。

Claims (18)

1.一种半导体装置，所述半导体装置包括：
基底；
去耦电容器，设置在基底上；
第一连接焊盘，与去耦电容器竖直地叠置；
第二连接焊盘，从去耦电容器横向偏移；
钝化层，具有第一开口和第二开口，通过第一开口暴露第一连接焊盘的一部分并通过第二开口暴露第二连接焊盘的一部分；以及
第一焊料凸块，设置在第一连接焊盘上并覆盖钝化层的顶表面的一部分；以及
第二焊料凸块，设置在第二连接焊盘上，
其中，第一焊料凸块填充第一开口并且与钝化层接触，
其中，第一开口具有沿一个方向的第一宽度，且第二开口具有沿所述方向的第二宽度，
其中，第一焊料凸块沿所述方向的宽度大于第一宽度，第二焊料凸块沿所述方向的宽度小于第二宽度。
2.根据权利要求1所述的半导体装置，所述半导体装置还包括：
电路，形成在基底上；
其中，第一焊料凸块和第一连接焊盘是电连接到电路的接地路径或电源路径的部分。
3.根据权利要求1所述的半导体装置，其中：
第一连接焊盘的所述部分是第一连接焊盘的顶表面的一部分；
第一焊料凸块完全覆盖第一连接焊盘的暴露部分。
4.根据权利要求3所述的半导体装置，其中，
第一焊料凸块填充第一开口并且从第一连接焊盘延伸到钝化层的顶表面上方。
5.根据权利要求1所述的半导体装置，其中，第一焊料凸块的宽度大于第二焊料凸块的宽度。
6.根据权利要求5所述的半导体装置，其中，第二焊料凸块从形成在基底上的任何去耦电容器横向偏移。
7.根据权利要求1所述的半导体装置，其中，第一连接焊盘电连接到去耦电容器。
8.根据权利要求1所述的半导体装置，其中：
第一焊料凸块包括支柱和焊料；
支柱接触钝化层的顶表面。
9.一种半导体装置，所述半导体装置包括：
基底；
去耦电容器，设置在基底上；
钝化层，具有暴露第一连接焊盘的第一开口；
第一焊料凸块，与去耦电容器竖直地叠置，第一焊料凸块填充第一开口并且与钝化层接触；以及
第二焊料凸块，从去耦电容器横向偏移，
其中，第一焊料凸块的宽度大于第二焊料凸块的宽度。
10.根据权利要求9所述的半导体装置，所述半导体装置还包括：
电路，设置在基底上；
其中：第一焊料凸块是电连接到电路的接地路径或电源路径的部分；并且第二焊料凸块是电连接到电路的信号路径的部分。
11.根据权利要求9所述的半导体装置，其中：
基底包括单元区和外围电路区；
去耦电容器形成在外围电路区中；
半导体装置还包括在单元区中设置在基底上的存储元件。
12.根据权利要求9所述的半导体装置，其中：
第一焊料凸块完全覆盖第一连接焊盘的顶表面的暴露部分。
13.根据权利要求9所述的半导体装置，其中：
第一开口具有沿一个方向的第一宽度；
第一焊料凸块从第一连接焊盘延伸到钝化层的顶表面上方；
第一焊料凸块沿所述方向的宽度大于第一宽度。
14.根据权利要求9所述的半导体装置，其中：
钝化层包括暴露第二连接焊盘的第二开口；
第二焊料凸块设置在第二连接焊盘上的第二开口中并与钝化层分隔开。
15.根据权利要求9所述的半导体装置，其中，第一焊料凸块和去耦电容器通过金属互连彼此电连接。
16.一种半导体封装件，所述半导体封装件包括：
封装基底；
半导体芯片，包括去耦电容器和钝化层，钝化层具有第一开口和第二开口；多个焊料凸块，将半导体芯片电连接到封装基底，
其中：焊料凸块中的第一焊料凸块设置在第一开口中，与去耦电容器竖直地对齐并延伸到钝化层的顶表面上方；焊料凸块中的第二焊料凸块设置在第二开口中并且不与钝化层的第二开口的侧壁和去耦电容器竖直地叠置。
17.根据权利要求16所述的半导体封装件，其中，第二焊料凸块从半导体芯片的任何去耦电容器横向偏移。
18.根据权利要求16所述的半导体封装件，其中，第一焊料凸块的宽度大于第二焊料凸块的宽度。
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