CN1068458C - 半导体器件的体接触结构 - Google Patents
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Abstract
一种改进的半导体器件的体接触结构,能利用较小表面积形成接触部分,甚至在接触未对准时,也能获得源区和体接触扩散层间的恒定接触表面积比,并能防止寄生器件的激活,从而能使器件稳定地工作。该半导体器件接触结构包括:导电衬底;第一和第二并列的导电源区;形成于延展的源区上且被延展的源区分裂成多个部分的条形导电体接触扩散层;使每个体接触扩散层部分与邻近的体接触扩散层部分及形成于邻近体接触扩散层部分之间的延展源区连接而形成的立方形接触布线金属层。
Description
本发明涉及一种半导体器件体接触结构,特别涉及一种改进的半导体器件体接触结构,能利用较小表面积形成接触部分,既使在接触没对准时,也能得到源区与体接触扩散层间的恒定接触表面比,并能防止寄生器件激活,因此能使半导体器件稳定地工作。
通常,制造半导体器件时,不可避免地要形成寄生器件。
这种寄生器件在特定条件下被激活,并使器件的特性退化。所以重要的是消除这种寄生器件的工作条件。
下面将参照各附图说明消除寄生器件的上述工作条件的常规方法。
图1A是展示NMOSFET的常规体接触结构的剖面图,图1B是展示NMOSFET常规结构的等效电路图。
如图所示,常规NMOSFET包括有沟道区12的P型衬底11、形成于沟道区12上的栅氧化膜和栅极18、N+型漏区13、形成在N+型漏区13上的漏电极19、N+型源区14、与N+型源区14接触的P+型体接触扩散层15、及形成于N+型源区14和P+型体接触扩散层15上的源极17,源极17既与N+型源区14连接,又与P+型体接触扩散层15连接。在图中,参考数字16表示P型衬底11的P型衬底区,该P型衬底区16与N+型源区14和P+型体接触扩散层15接触。
另外,在上述常规NMOSFET中,寄生NPN双极结晶体管(BJT)形成于器件的表面上。
在该BJT器件中,NMOSFET的漏区13、衬底11的沟道区12、和源区分别作为集电极C、基极B、和发射极E。如果沟道区12的基极B和源区14(或体接触扩散层15)的发射极E间有预定的电位差,则BJT器件被激活,无论NMOSFET的栅18的电压如何,电流会通过基极B流到发射极E。
另外,少量电流通过与由源区14和体接触扩散层15接触构成的发射极E接触的P型衬底区16,从由沟道区12构成的基极B流到体接触扩散层15。衬底区16的电阻越高,则通过P型衬底区16从由沟道区构成的基极B流到体接触扩散层15的电流的流动通道上压降越大。此时,如果压降达到能激活寄生BJT器件的由沟道区12构成的基极B和由源区14构成的发射极E的程度,那么寄生BJT器件会被激活,因而,不管加到栅18上的电压如何,电流开始流动。
因此,为了防止BJT器件被激活,需防止电压加到寄生BJT器件的由沟道区12构成的基极B和由源区14构成的发射极E上。体接触扩散层15做得较深,能使衬底区16的电阻最小,并能防止寄生BJT器件被激活,由此可以增大安全工作区。
上述体接触扩散层15的作用是有效地防止寄生器件被激活,但由于体接触扩散层15面积增大,会使欲形成另一器件的区域增大,这样,便会减小面积利用率,不利于增大器件单位面积的导通电阻。
因此,为了防止寄生BJT器件被激活及半导体器件的特性退化,必须制造窄且深的体接触扩散层。
为了实现上述技术,如下所述,又公开了一种方法。
图2A是展示NMOSFET的常规体接触结构的示意图,图2B是展示NMOSFET的常规体接触结构的布局图。
如图所示,常规体接触结构包括:衬底21,其中形成有并列的源扩散层23和24;沿纵向形成于源扩散层23和24间的条形体接触扩散层22;形成于体接触扩散层22及部分源扩散层23和24上的长立方形接触布线金属层25,这样,接触部分能形成在体接触扩散层22及源扩散层23和24上,使体接触扩散层22、源扩散层23和24共接。
然而,在上述结构中,形成于体接触层22及源区23和24上的接触布线金属层25必须与源区23和24的接触部分接触预定宽度。另外,接触布线层25必须与源区23和24局部接触预定宽度。
例如,在确定了最小尺寸λ后,接触布线层25的最小尺寸由λ×λ决定,接触布线层25形成于其中的区27和接触布线层25没形成于其中的区28的最小宽度分别为1/4λ,所以沿沟道纵向形成的包括体接触扩散层22的源区23和24的宽度必须为3/2λ,即其宽度为最小宽度的1.5倍。
另外,如果由于在源区23和24之一的衬底上对准接触掩模时产生误差而使接触孔图形未对准,由于其中未形成接触布线层25的区28的宽度小于最小宽度(1/4λ),MOSFET源区23和24不能形成所要求的体接触。
结果,由于必须基于上述条件确定宽度,那么包括体接触扩散层22的源区23和24的整个面积(或宽度)会增加,这是有害的。
图3A是展示旨在克服上述缺点的NMOSFET的另一常规体接触结构的示意图,图3B是展示该NMOSFET的常规体接触结构的布局图。
如图所示,体接触结构包括沿沟道区并列地形成于P型衬底31上的N+型源区33和34、和形成于N+型源区33和34间的P+型体接触扩散层32。这里,P+型体接触扩散层32被在N+型源区33和34间延展的N+源区36分裂成多个部分。
即,由于N+型源区36和P+型体接触扩散层32交替地形成在P型衬底31中,接触孔35未与P+型体接触扩散层32和N+型源区36准确地接触。甚至在接触孔35未对准时,其中心部分的面积也恒定,这样便克服了体接触的缺点。
因此,获得了宽度为“λ”的包括体接触扩散层32的源区33和34,所以能获得基于设计规则的最小宽度。
然而,如图2A至3B所示,如果形成直条形接触孔,则其余器件的接触孔形成为方形。由于在形成接触孔时腐蚀率不同,所以应先腐蚀小尺寸接触孔区,之后再腐蚀大尺寸接触孔区。这样,在形成接触孔时,如果主要对体接触区进行腐蚀,则会过腐蚀其它接触区。相反,如果主要对其它接触区进行腐蚀,则基本上没腐蚀体接触区。
因此,本发明的目的是提供一种半导体器件体接触结构,克服常规技术中存在的上述缺点。
本发明的另一目的是提供一种改进的半导体器件体接触结构,能利用较小的表面积形成接触部分,甚至在接触没对准时,也能获得恒定的源区与体接触扩散层的接触表面比,因而能使器件稳定地工作。
为了实现上述目的,提供一种半导体器件体接触结构,包括:第一导电类型的衬底;第一和第二并列的导电源区;形成于源区上且被延展的源区分裂成多个部分的条形导电体接触扩散层;使每个体接触扩散层部分与邻近的体接触扩散层部分及形成于邻近体接触扩散层部分之间的延展源区连接而形成的立方形接触布线金属层。
下面的说明将会使本发明的其它优点、目的和特点更清楚。
通过下面的说明和只是示意性的各附图,会更充分地理解本发明,但这些并不是对本发明的限制,其中:
图1A是展示NMOSFET的常规体接触结构的剖面图;
图1B是展示NMOSFET的常规体接触结构的等效电路图;
图2A是展示NMOSFET的常规体接触结构的透视图;
图2B是展示NMOSFET的常规体接触结构的布局图;
图3A是展示NMOSFET的另一常规体接触结构的透视图;
图3B是展示NMOSFET的另一常规体接触结构的布局图;
图4A是展示根据本发明第一实施例的NMOSFET的体接触结构的透视图;
图4B是展示根据本发明第一实施例的NMOSFET的体接触结构的布局图;
图5A是展示根据本发明第二实施例的NMOSFET的体接触结构的透视图;
图5B是展示根据本发明第二实施例的NMOSFET的体接触结构的布局图。
图4A是展示根据本发明第一实施例的NMOSFET的体接触结构的透视图,图4B是展示根据本发明第一实施例的NMOSFET的体接触结构的布局图。
如图所示,在P型衬底101的上部,P型体接触扩散层102被N+型延展源区106相间地分裂成多个部分。并列的N+型源区103和104形成于P型体接触扩散层部分102的两侧。接触布线金属层105形成于每个N+型源区106及P型体接触扩散层部分102的各邻近部分上,P+型体接触扩散层102和形成于其间的N+型源区106共接。
上述体接触结构能利用较小的面积形成接触。另外,甚至在接触区未对准时,源区和体接触扩散层的PN结的接触比,即源接触区和体接触区的比变为1∶1。
另外,由于接触布线区按方形形成,接触布线区和体接触扩散层之间的接触面积小,使得腐蚀率与其它区体接触结构的腐蚀率相同。
图5A是展示根据本发明第二实施例的NMOSFET的体接触结构的透视图,图5B是展示根据本发明第二实施例的NMOSFET的体接触结构的布局图。
如图所示,根据本发明第二实施例的体接触结构包括:形成于P型衬底201中的N+型源区203和204;相间地被分裂成多个部分的P+型体接触扩散层202,它形成于N+型源区203和204中;接触布线金属层205,它被相间地分裂成多个部分,形成该层以便使P+型体接触扩散层部分202与邻近的P+型体接触扩散层部分202和形成于各P+型体接触扩散层202之间的N+型延展的源区206共接。
这里,体接触扩散层202的端部相对于源区203和204被垂直且纵向切掉,所以体接触扩散层202没有锐边缘部分。
与本发明的第一实施例相同,只利用小面积形成上述体接触结构,甚至在接触未对准时,源区和体接触扩散层的PN结的接触面积比,即源接触区和体接触区的比变为1∶1。
另外,由于形成条形接触布线金属层,且接触布线金属层和体接触扩散层间的接触面积变小,所以腐蚀率变得与其它区体接触结构的腐蚀率相同。
如上所述,根据本发明的半导体器件体接触结构包括形成于延展的源区中的体接触扩散层和形成于体接触扩散层上的体接触层,因而体接触扩散层和形成于其间的源区可以共接,因而甚至在对准接触掩模时产生误差,也能获得关于源区与体接触扩散层的1∶1面积比的金属接触。另外,能形成小尺寸接触,这样便可获得与其它区接触结构相同的预定的腐蚀率。
因此,衬底和源间的电位差减小,因而可以防止寄生器件的激活,使器件更稳定地工作。
尽管为了说明的目的公开了本发明的优选实施例,但本领域的普通技术人员明白,在不脱离本发明所附权利要求所限定的发明范围和精神实质的情况下,可能有各种改型、附加和替换。
Claims (3)
1.一种半导体器件的体接触结构,包括:
导电衬底;
第一和第二并列的导电源区;
形成于延展的源区上且被延展的源区分裂成多个部分的条形导电体接触扩散层;
使每个体接触扩散层部分与邻近的体接触扩散层部分及形成于邻近体接触扩散层部分之间的延展源区连接而形成的立方形接触布线金属层。
2.根据权利要求1的半导体器件的体接触结构,其特征在于,所述体接触扩散层部分形成于延展的源区中,所述体接触扩散层部分交替地形成于其中。
3.根据权利要求1的半导体器件的体接触结构,其特征在于,所述体接触扩散层通过垂直于源区的纵向轴切掉其边缘部分形成,从而形成一斜切的部分。
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KR5010/1996 | 1996-02-28 | ||
KR1019960005010A KR0179898B1 (ko) | 1996-02-28 | 1996-02-28 | 반도체소자의 바디-콘택 구조 |
KR5010/96 | 1996-02-28 |
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CN1160935A CN1160935A (zh) | 1997-10-01 |
CN1068458C true CN1068458C (zh) | 2001-07-11 |
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Application Number | Title | Priority Date | Filing Date |
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CN97100726A Expired - Fee Related CN1068458C (zh) | 1996-02-28 | 1997-02-26 | 半导体器件的体接触结构 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5844285A (zh) |
JP (1) | JP3008182B2 (zh) |
KR (1) | KR0179898B1 (zh) |
CN (1) | CN1068458C (zh) |
DE (1) | DE19707695B4 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050055295A1 (en) * | 2003-09-05 | 2005-03-10 | Bateson Douglas F. | Method and system for providing stable value |
US7670896B2 (en) * | 2006-11-16 | 2010-03-02 | International Business Machines Corporation | Method and structure for reducing floating body effects in MOSFET devices |
JP2009200165A (ja) * | 2008-02-20 | 2009-09-03 | Elpida Memory Inc | 半導体装置 |
US8420460B2 (en) * | 2008-03-26 | 2013-04-16 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
US8410554B2 (en) | 2008-03-26 | 2013-04-02 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
US7964467B2 (en) * | 2008-03-26 | 2011-06-21 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of soi circuits |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5185275A (en) * | 1992-03-30 | 1993-02-09 | Micron Technology, Inc. | Snap-back preventing method for high voltage MOSFET |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US5563438A (en) * | 1994-10-26 | 1996-10-08 | Alliedsignal Inc. | Rugged CMOS output stage design |
-
1996
- 1996-02-28 KR KR1019960005010A patent/KR0179898B1/ko not_active IP Right Cessation
-
1997
- 1997-02-25 US US08/810,135 patent/US5844285A/en not_active Expired - Lifetime
- 1997-02-26 DE DE19707695A patent/DE19707695B4/de not_active Expired - Fee Related
- 1997-02-26 CN CN97100726A patent/CN1068458C/zh not_active Expired - Fee Related
- 1997-02-28 JP JP9046188A patent/JP3008182B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5185275A (en) * | 1992-03-30 | 1993-02-09 | Micron Technology, Inc. | Snap-back preventing method for high voltage MOSFET |
Also Published As
Publication number | Publication date |
---|---|
DE19707695A1 (de) | 1997-09-04 |
KR0179898B1 (ko) | 1999-04-15 |
JP3008182B2 (ja) | 2000-02-14 |
DE19707695B4 (de) | 2005-04-28 |
JPH104192A (ja) | 1998-01-06 |
KR970063502A (ko) | 1997-09-12 |
CN1160935A (zh) | 1997-10-01 |
US5844285A (en) | 1998-12-01 |
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