CN106817840A - A kind of FPC and its manufacture method without orifice ring - Google Patents
A kind of FPC and its manufacture method without orifice ring Download PDFInfo
- Publication number
- CN106817840A CN106817840A CN201710069518.4A CN201710069518A CN106817840A CN 106817840 A CN106817840 A CN 106817840A CN 201710069518 A CN201710069518 A CN 201710069518A CN 106817840 A CN106817840 A CN 106817840A
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- China
- Prior art keywords
- layer
- metal
- fpc
- metal level
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention discloses a kind of FPC without orifice ring and its manufacture method, the manufacture method includes：Substrate layer is provided, and via is formed on substrate layer；Substrate layer is metallized, and one layer of conductive layer is deposited in the hole wall of the surface of substrate layer and via；Layer of metal layer is deposited on the electrically conductive；It is the pressing of etching dry film, exposed and developed, the local metal level position that etch removal is exposed；Etching, the metal level of logicalnot circuit layer and nonclient area is removed；Etching is peeled off with dry film, all dry films on stripping metal level, forms the FPC without orifice ring.The present invention can realize that FPC turns on the non-porous ring region of bore edges using drilling treatment and circuit etching flow before metallization, improve the wiring density and plate face utilization rate of FPC.
Description
Technical field
The present invention relates to FPC technical field, more particularly to a kind of FPC and its manufacture without orifice ring
Method.
Background technology
With the miniaturization of electronic product, to the high-density wiring requirement more and more higher of FPC.FPC
The conducting of levels Copper Foil is realized in meeting (such as Double-layer flexible circuit board) by graphic plating, it is contemplated that when graphic plating dry film exposes
Bit errors can typically reserve the orifice ring region of unilateral 75 microns in conducting bore edges.
Whole copper thickness rate base material Copper Foil is thick many after orifice ring regional graphics electro-coppering, it is impossible to lost simultaneously with base material Copper Foil region
Groove road, so all orifice ring regions can not be connected up, is unfavorable for high-density wiring.
Therefore, for above-mentioned technical problem, it is necessary to provide a kind of FPC without orifice ring and its manufacture method.
The content of the invention
In view of this, it is an object of the invention to provide a kind of FPC without orifice ring and its manufacture method.
To achieve these goals, technical scheme provided in an embodiment of the present invention is as follows：
A kind of FPC without orifice ring, the non-porous ring region of FPC, FPC includes：
Substrate layer, is formed with some vias on the substrate layer；
Conductive layer, the conductive layer is covered in the surface of substrate layer and the hole wall of via；
Metal level, the metal level is including the first metal layer positioned at via hole wall, on conductive layer and in first
If the second metal layer that metal level is electrically connected with and separating on conductive layer and in the first metal layer and second metal layer
Dry 3rd metal level, the first metal layer and second metal layer as FPC workspace, the 3rd metal level conduct
The line layer of FPC.
As a further improvement on the present invention, the substrate layer material is polyimides.
As a further improvement on the present invention, the conductive layer is electroless nickel layer, and metal level is copper electroplating layer.
As a further improvement on the present invention, the thickness of the conductive layer is 0.01~1 micron, and the thickness of metal level is 5
~20 microns.
Correspondingly, a kind of manufacture method of the FPC without orifice ring, the manufacture method includes：
Substrate layer is provided, and via is formed on substrate layer；
Substrate layer is metallized, and one layer of conductive layer is deposited in the hole wall of the surface of substrate layer and via；
Layer of metal layer is deposited on the electrically conductive；
It is the pressing of etching dry film, exposed and developed, the local metal level position that etch removal is exposed；
Etching, the metal level of logicalnot circuit layer and nonclient area is removed；
Etching is peeled off with dry film, all dry films on stripping metal level, forms the FPC without orifice ring.
As a further improvement on the present invention, in described " etching " step, the metal level after etching includes being located at via
The first metal layer of hole wall, on conductive layer and in the first metal layer be electrically connected with second metal layer and positioned at conduction
Some 3rd metal levels on layer and in the first metal layer and second metal layer separate, the first metal layer and second metal layer
As the workspace of FPC, the 3rd metal level as FPC line layer.
As a further improvement on the present invention, the substrate layer material is polyimides.
As a further improvement on the present invention, the conductive layer is electroless nickel layer, and metal level is copper electroplating layer.
As a further improvement on the present invention, the deposit thickness of the conductive layer is 0.01~1 micron, deposition of metal
Thickness is 5~20 microns.
The beneficial effects of the invention are as follows：
Can realize that FPC turns on the non-porous ring region of bore edges using drilling treatment and circuit etching flow before metallization
Domain, improves the wiring density and plate face utilization rate of FPC；
The operations such as the pressing of figure dry film, the dry film stripping of exposed and developed and graphic plating are reduced, manufacture stream is optimized
Journey, and the materials such as figure dry film are saved, greatly reduce manufacturing cost.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in invention, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 a~Fig. 1 h are the manufacturing approach craft flow chart of the FPC with orifice ring in the prior art；
Fig. 2 is the top view of the FPC originally in the prior art with orifice ring；
Fig. 3 a~3f is the manufacturing approach craft flow of the FPC without orifice ring in the embodiment of the invention
Figure；
Fig. 4 is the top view of the FPC without orifice ring in the embodiment of the invention.
Specific embodiment
In order that those skilled in the art more fully understand the technical scheme in the present invention, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described implementation
Example is only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, should all belong to protection of the present invention
Scope.
Ginseng Fig. 1 a~Fig. 1 h show the manufacturing approach craft flow chart of the FPC with orifice ring in the prior art,
Drilled including substrate and metallization (shadow), the pressing of figure dry film, exposed and developed, pattern plating copper, graphic plating dry film
Peel off, the pressing of etching dry film, exposed and developed, copper etching are etched and use dry film strip step, are carried out specifically below in conjunction with accompanying drawing
It is bright.
Shown in ginseng Fig. 1 a, there is provided substrate 10 ', substrate 10 ' includes substrate layer 11 ' and the metal level positioned at substrate layer both sides
12 ', wherein, substrate layer 11 ' is polyimides, and metal level 12 ' is base material Copper Foil, both sides table of the base material Copper Foil located at polyimides
Face, the thickness of base material Copper Foil is 12 microns；
Shown in ginseng Fig. 1 b, substrate drilling is one via 20 ' of brill on substrate, and via is realized by follow-up process
The metal conduction of 20 ' upper and lower layer metal copper foil；The shadow flow of metallization is deposited on the hole wall polyimides of via 20 '
Conductive layer (not shown) when very thin graphitic carbon particles are as electro-coppering；
Shown in ginseng Fig. 1 c, the pressing of figure dry film, exposed and developed flow are by via by graphic plating dry film 30 '
20 ' are exposed to follow-up graphic plating with the orifice ring region at the edge of via 20 '；
Shown in ginseng Fig. 1 d, graphic plating is thick left in one layer 12 microns of the hole wall of via 20 ' and orifice ring region local deposits
Right electrodeposited coating 40 ', realizes the metal conduction of upper and lower layer base material Copper Foil, it is preferable that electrodeposited coating is copper electroplating layer；
Shown in ginseng Fig. 1 e, it is to strip the dry film on substrate 10 ' that graphic plating dry film 30 ' is peeled off；
Shown in ginseng Fig. 1 f, the pressing of etching dry film, it is exposed and developed be that removal local will will be etched by etching dry film 50 '
The position of metal level 12 ' be exposed；
Shown in ginseng Fig. 1 g, etch copper is that the metal level 12 ' of logicalnot circuit and nonclient area is etched into removal；
Shown in ginseng Fig. 1 h, it is to strip all dry films in base material Copper Foil and electro-coppering that etching dry film 50 ' is peeled off.
Shown in ginseng Fig. 2, a hole for having electro-coppering can be formed at the edge of via 20 ' by the final products of above flow
Ring region 21 ', its orifice ring One-sided Widths is at 75 microns or more, and 12 microns thicker than base material Copper Foil of the copper in orifice ring region is thick very
It is many, it is impossible to which that, with base material Copper Foil region circuit etching simultaneously, orifice ring region can not be connected up, and be unfavorable for high-density wiring.
Shown in ginseng Fig. 3 a~3f, a kind of system of the FPC without orifice ring is disclosed in the embodiment of the invention
Make method, including polyimides drilling and metallization (chemical nickel plating), electro-coppering, the pressing of etching dry film, exposed and developed, copper erosion
Carve, dry film strip step is used in etching, is described in detail below in conjunction with accompanying drawing.
Shown in ginseng Fig. 3 a, 3b, there is provided substrate layer 10, and via 20 is formed on substrate layer 10.In present embodiment, base
Material 10 material of layer are polyimides, and a via 20 is bored on polyimide, and the gold of the upper and lower layer in hole is realized by follow-up process
Category conducting；
Substrate layer is metallized, and one layer of conductive layer (not shown) is deposited in the hole wall of the surface of substrate layer 10 and via 20,
It is that one layer of 0.01~1 conductive electroless nickel layer of micron thickness energy is deposited on polyimide surface and Kong Bi in present embodiment,
Preferably, the thickness of electroless nickel layer is 0.1 micron；
Shown in ginseng Fig. 3 c, layer of metal layer 30 is deposited on the electrically conductive, electroplated in electroless nickel layer in present embodiment
One layer of 5~20 metal copper layer of micron thickness of deposition, it is preferable that the thickness of metal copper layer is 12 microns；
It is the pressing of etching dry film, exposed and developed shown in ginseng Fig. 3 d, removal local will will be etched by etching dry film 40
The position of metal level 30 is exposed；
Shown in ginseng Fig. 3 e, etching removes the metal level of logicalnot circuit layer and nonclient area, and the metal level after etching includes position
The first metal layer 31 in via hole wall, the second metal layer 32 being electrically connected with conductive layer and in the first metal layer,
And some 3rd metal levels 33 on conductive layer and in the first metal layer and second metal layer separate, the first metal layer and
Second metal layer as FPC workspace, the 3rd metal level as FPC line layer；
Shown in ginseng Fig. 3 f, etching is peeled off with dry film, all etchings dry film 40 on stripping metal level, is formed without orifice ring
FPC.
Ginseng Fig. 3 f and Fig. 4, the non-porous ring region of FPC in present embodiment, including：
Substrate layer 10, is formed with some vias 20 on substrate layer；
Conductive layer (not shown), conductive layer is covered in the surface of substrate layer 10 and the hole wall of via 20；
Metal level, including the first metal layer 31 positioned at via hole wall, on conductive layer and in the first metal layer electricity
Property connection second metal layer 32 and on conductive layer and in the first metal layer and second metal layer separate some three
Metal level 33, the first metal layer and second metal layer as FPC workspace, the 3rd metal level is used as flexible circuitry
The line layer of plate.
Comparison diagram 2, Fig. 4 is visible, and present embodiment is realized final using drilling treatment and circuit etching flow before metallization
Product turns on the non-porous ring region of bore edges, and can also respectively be arranged single line on via both sides.
It should be appreciated that illustrated so that substrate layer both sides are equipped with line layer as an example in above-mentioned implementation method, at it
In his implementation method, it is also possible to line layer only is set in the side of substrate layer.
As can be seen from the above technical solutions, the invention has the advantages that：
Can realize that FPC turns on the non-porous ring region of bore edges using drilling treatment and circuit etching flow before metallization
Domain, improves the wiring density and plate face utilization rate of FPC；
The operations such as the pressing of figure dry film, the dry film stripping of exposed and developed and graphic plating are reduced, manufacture stream is optimized
Journey, and the materials such as figure dry film are saved, greatly reduce manufacturing cost.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be in other specific forms realized.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires to be limited rather than described above, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as the claim involved by limitation.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each implementation method is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art should
Specification an as entirety, the technical scheme in each embodiment can also be formed into those skilled in the art through appropriately combined
May be appreciated other embodiment.
Claims (9)
1. a kind of FPC without orifice ring, it is characterised in that the non-porous ring region of FPC, FPC bag
Include：
Substrate layer, is formed with some vias on the substrate layer；
Conductive layer, the conductive layer is covered in the surface of substrate layer and the hole wall of via；
Metal level, the metal level is including the first metal layer positioned at via hole wall, on conductive layer and in the first metal
Second metal layer that layer is electrically connected with and on conductive layer and in the first metal layer and second metal layer separate some the
Three metal levels, the first metal layer and second metal layer as FPC workspace, the 3rd metal level is used as flexibility
The line layer of wiring board.
2. FPC according to claim 1, it is characterised in that the substrate layer material is polyimides.
3. FPC according to claim 1, it is characterised in that the conductive layer is electroless nickel layer, metal level is
Copper electroplating layer.
4. FPC according to claim 1, it is characterised in that the thickness of the conductive layer is 0.01~1 micron,
The thickness of metal level is 5~20 microns.
5. a kind of manufacture method of the FPC without orifice ring, it is characterised in that the manufacture method includes：
Substrate layer is provided, and via is formed on substrate layer；
Substrate layer is metallized, and one layer of conductive layer is deposited in the hole wall of the surface of substrate layer and via；
Layer of metal layer is deposited on the electrically conductive；
It is the pressing of etching dry film, exposed and developed, the local metal level position that etch removal is exposed；
Etching, the metal level of logicalnot circuit layer and nonclient area is removed；
Etching is peeled off with dry film, all dry films on stripping metal level, forms the FPC without orifice ring.
6. manufacture method according to claim 5, it is characterised in that in " etching " step, the metal level after etching
The second metal being electrically connected with including the first metal layer positioned at via hole wall, on conductive layer and in the first metal layer
Layer and some 3rd metal levels on conductive layer and in the first metal layer and second metal layer separate, first gold medal
Category layer and second metal layer as FPC workspace, the 3rd metal level as FPC line layer.
7. manufacture method according to claim 5, it is characterised in that the substrate layer material is polyimides.
8. manufacture method according to claim 5, it is characterised in that the conductive layer is electroless nickel layer, metal level is electricity
Copper plate.
9. manufacture method according to claim 5, it is characterised in that the deposit thickness of the conductive layer is 0.01~1 micro-
Rice, the thickness of deposition of metal is 5~20 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710069518.4A CN106817840A (en) | 2017-02-08 | 2017-02-08 | A kind of FPC and its manufacture method without orifice ring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710069518.4A CN106817840A (en) | 2017-02-08 | 2017-02-08 | A kind of FPC and its manufacture method without orifice ring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106817840A true CN106817840A (en) | 2017-06-09 |
Family
ID=59112893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710069518.4A Pending CN106817840A (en) | 2017-02-08 | 2017-02-08 | A kind of FPC and its manufacture method without orifice ring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106817840A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714890A (en) * | 2019-01-22 | 2019-05-03 | 广州安费诺诚信软性电路有限公司 | A method of preparing the acyclic electric hole of flexible circuit thin plate |
| CN113543501A (en) * | 2021-07-14 | 2021-10-22 | 加宏科技（无锡）股份有限公司 | Method for producing carbon ink circuit board positive and negative films with electroplated through holes |
| CN114245598A (en) * | 2021-11-30 | 2022-03-25 | 苏州群策科技有限公司 | Circuit board etching method |
| CN114615811A (en) * | 2020-12-07 | 2022-06-10 | 深南电路股份有限公司 | High-precision circuit processing method and high-precision circuit board |
| CN114760771A (en) * | 2022-05-18 | 2022-07-15 | 福莱盈电子股份有限公司 | Protection method for conducting hole on circuit board |
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| CN103491726A (en) * | 2013-07-25 | 2014-01-01 | 博罗县精汇电子科技有限公司 | Flexible circuit board manufacturing method |
| CN105723817A (en) * | 2013-11-14 | 2016-06-29 | 阿莫绿色技术有限公司 | Flexible printed circuit board and method for manufacturing same |
| CN105899003A (en) * | 2015-11-06 | 2016-08-24 | 武汉光谷创元电子有限公司 | Single layer circuit board, multilayer circuit board and manufacture method for single layer circuit board and multilayer circuit board |
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2017
- 2017-02-08 CN CN201710069518.4A patent/CN106817840A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103491726A (en) * | 2013-07-25 | 2014-01-01 | 博罗县精汇电子科技有限公司 | Flexible circuit board manufacturing method |
| CN105723817A (en) * | 2013-11-14 | 2016-06-29 | 阿莫绿色技术有限公司 | Flexible printed circuit board and method for manufacturing same |
| CN105899003A (en) * | 2015-11-06 | 2016-08-24 | 武汉光谷创元电子有限公司 | Single layer circuit board, multilayer circuit board and manufacture method for single layer circuit board and multilayer circuit board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714890A (en) * | 2019-01-22 | 2019-05-03 | 广州安费诺诚信软性电路有限公司 | A method of preparing the acyclic electric hole of flexible circuit thin plate |
| CN114615811A (en) * | 2020-12-07 | 2022-06-10 | 深南电路股份有限公司 | High-precision circuit processing method and high-precision circuit board |
| CN113543501A (en) * | 2021-07-14 | 2021-10-22 | 加宏科技（无锡）股份有限公司 | Method for producing carbon ink circuit board positive and negative films with electroplated through holes |
| CN114245598A (en) * | 2021-11-30 | 2022-03-25 | 苏州群策科技有限公司 | Circuit board etching method |
| CN114760771A (en) * | 2022-05-18 | 2022-07-15 | 福莱盈电子股份有限公司 | Protection method for conducting hole on circuit board |
| CN114760771B (en) * | 2022-05-18 | 2023-11-07 | 福莱盈电子股份有限公司 | Method for protecting through hole on circuit board |
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Application publication date: 20170609 |