CN106783793A - A kind of leads of semiconductor device framework of use TO types encapsulation - Google Patents
A kind of leads of semiconductor device framework of use TO types encapsulation Download PDFInfo
- Publication number
- CN106783793A CN106783793A CN201710184825.7A CN201710184825A CN106783793A CN 106783793 A CN106783793 A CN 106783793A CN 201710184825 A CN201710184825 A CN 201710184825A CN 106783793 A CN106783793 A CN 106783793A
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- CN
- China
- Prior art keywords
- pin
- chip
- leads
- semiconductor device
- frame
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A kind of leads of semiconductor device framework of use TO types encapsulation of the invention, including independent base drawing strickle guide frame and nead frame, base drawing strickle guide frame is led encapsulation unit continuous transverse and is formed by connecting by multiple bases, nead frame is formed by connecting by multiple pin package unit continuous transverses, pin package unit includes three pins side by side for extending outward, the pin end of both sides is upturned and is connected with the chip island of chip placement, middle pin is tilted obliquely and front end is provided with weld part, base is led encapsulation unit and chip solder side above chip island is may be superimposed on including center, chip solder side bottom surface is provided with welding groove, the weld part insertion welding groove of middle pin is interior and welds together.The beneficial effects of the invention are as follows:A part of automated job equipment is eliminated, so as to reduce investment, while also save manpower, it is also relatively too high to reduce cost of labor, simplifies operation, improves operating efficiency.
Description
Technical field
The present invention relates to a kind of leads of semiconductor device framework of use TO types encapsulation.
Background technology
At present, for different semiconductor products, the form of semiconductor packages is varied, and most commonly seen is thin external form
Encapsulation(Thin Outline Package, abbreviation TO type are encapsulated).Existing TO series of products lead frame welding procedure is adopted
With copper wire jumper or WIRE BOND technique productions, equipment investment volume is too high when using automated job, and uses manual work
When cost of labor it is also relatively too high and cumbersome.
The content of the invention
It is technical deficiency more than solving, the invention provides a kind of leads of semiconductor device frame of use TO types encapsulation
Frame, production equipment less investment, cost of labor is low.
The present invention is achieved by the following measures:
A kind of leads of semiconductor device framework of use TO types encapsulation of the invention, including independent base drawing strickle guide frame and leadframe
Frame, the base drawing strickle guide frame is led encapsulation unit continuous transverse and is formed by connecting by multiple bases, and the nead frame is by multiple pin packages
Unit continuous transverse is formed by connecting, the pin package unit includes three pins side by side extending outward, and both sides are drawn
Foot portion is upturned and is connected with the chip island of chip placement, and middle pin is tilted obliquely and front end is provided with welding
Portion, the base is led encapsulation unit and may be superimposed on chip solder side above chip island, the chip solder side bottom including center
Face is provided with welding groove, and the weld part insertion welding groove of middle pin is interior and welds together.
The pin end of above-mentioned pin package unit both sides is connected with a chip island, or pin package unit two jointly
The leads ends portion of side is connected to a chip island.
The dowel for extending laterally is respectively connected between the pin middle part of above-mentioned pin package unit and end.
The beneficial effects of the invention are as follows:A part of automated job equipment is eliminated, so as to reduce investment, while
Manpower is saved, it is also relatively too high to reduce cost of labor, simplifies operation, improves operating efficiency.
Brief description of the drawings
Fig. 1 leads circuit theory schematic diagram for base of the invention.
Fig. 2 is leadframe structure schematic diagram of the invention.
Fig. 3 is the structural representation after present invention welding.
Fig. 4 is the side structure schematic diagram of Fig. 3.
Fig. 5 is the leadframe structure schematic diagram of twin-core sheet form of the present invention.
Fig. 6 is the array type single nead frame combining structure schematic diagram after present invention welding.
Fig. 7 is the double leadframe structure schematic diagrames of array of the present invention.
Wherein:1 base drawing strickle guide frame, 2 nead frames, 3 pins, 4 chip islands, 5 chip solders side, 6 weld parts, 7 welding grooves.
Specific embodiment
Further detailed description is done to the present invention below in conjunction with the accompanying drawings:
As shown in Figure 1, 2, a kind of leads of semiconductor device framework of use TO types encapsulation of the invention, including independent base drawing strickle guide
Frame 1 and nead frame 2, base drawing strickle guide frame 1 are led encapsulation unit continuous transverse and are formed by connecting by multiple bases, and nead frame 2 is drawn by multiple
Pin encapsulation unit continuous transverse is formed by connecting, and pin package unit includes three pins 3 side by side for extending outward, both sides
The end of pin 3 is upturned and is connected with the chip island 4 of chip placement, and middle pin 3 is tilted obliquely and front end is set
There is weld part 6, base leads the chip solder side 5 that encapsulation unit may be superimposed on the top of chip island 4 including center, under chip solder side 5
Bottom surface is provided with welding groove 7, and the insertion welding groove 7 of weld part 6 of middle pin 3 is interior and welds together.
As Fig. 3, the end of pin 3 of 4 pin package unit both sides are connected with a chip island 4, or pin package jointly
The end of pin 3 of unit both sides is connected to a chip island 4.Between the middle part of pin 3 of pin package unit and end
It is connected with the dowel for extending laterally.As shown in figure 5, nead frame 2 can use twin-core sheet form, have a wide range of application.As schemed
6th, shown in 7, nead frame can be by the way of both sides all set pin, and array arrangement improves efficiency.
Using independent two panels frame structure, replace aluminum steel, and former wire jumper be integrated on nead frame 2,
Lead base(PAD)Separated with pin 3, lift operating efficiency, reduce equipment investment cost, replace original WIRE BOND(Beat
Wiring technology)Or CLIP BOND(Wire jumper technique), can largely save equipment investment, improving production efficiency.
The above is only the preferred embodiment of this patent, it is noted that for the ordinary skill people of the art
For member, on the premise of the art of this patent principle is not departed from, some improvement and replacement can also be made, these improve and replace
Also should be regarded as the protection domain of this patent.
Claims (3)
1. the leads of semiconductor device framework that a kind of use TO types are encapsulated, it is characterised in that:Including independent base drawing strickle guide frame and drawing
Foot frame, the base drawing strickle guide frame is led encapsulation unit continuous transverse and is formed by connecting by multiple bases, and the nead frame is by multiple pins
Encapsulation unit continuous transverse is formed by connecting, and the pin package unit includes three pins side by side for extending outward, both sides
Pin end be upturned and be connected with the chip island of chip placement, middle pin is tilted obliquely and front end is provided with
Weld part, the base is led encapsulation unit and may be superimposed on chip solder side above chip island, the chip solder side including center
Bottom surface is provided with welding groove, and the weld part insertion welding groove of middle pin is interior and welds together.
2. according to claim 1 using the leads of semiconductor device framework of TO types encapsulation, it is characterised in that:The pin envelope
The pin end of dress unit both sides is connected with a chip island jointly, or the leads ends portion of pin package unit both sides connects respectively
It is connected to a chip island.
3. according to claim 1 using the leads of semiconductor device framework of TO types encapsulation, it is characterised in that:The pin envelope
Fill and be respectively connected with the dowel for extending laterally between the pin middle part of unit and end.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710184825.7A CN106783793A (en) | 2017-03-24 | 2017-03-24 | A kind of leads of semiconductor device framework of use TO types encapsulation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710184825.7A CN106783793A (en) | 2017-03-24 | 2017-03-24 | A kind of leads of semiconductor device framework of use TO types encapsulation |
Publications (1)
Publication Number | Publication Date |
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CN106783793A true CN106783793A (en) | 2017-05-31 |
Family
ID=58967387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201710184825.7A Pending CN106783793A (en) | 2017-03-24 | 2017-03-24 | A kind of leads of semiconductor device framework of use TO types encapsulation |
Country Status (1)
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CN (1) | CN106783793A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109119397A (en) * | 2018-10-24 | 2019-01-01 | 扬州扬杰电子科技股份有限公司 | A kind of ultrathin type stamp-mounting-paper diode frame |
CN112289752A (en) * | 2020-12-01 | 2021-01-29 | 江苏捷捷微电子股份有限公司 | Flip GaN power device packaging structure and preparation method thereof |
CN116721950A (en) * | 2023-08-09 | 2023-09-08 | 天津安联信科技有限公司 | Semiconductor device encapsulation processingequipment |
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CN201215803Y (en) * | 2008-10-07 | 2009-04-01 | 宁波华龙电子股份有限公司 | Double-row double-column transistor lead frame plate piece |
CN201549494U (en) * | 2009-12-22 | 2010-08-11 | 宁波华龙电子股份有限公司 | High-frequency triode lead frame component |
CN201584407U (en) * | 2009-12-22 | 2010-09-15 | 宁波华龙电子股份有限公司 | Dual-diode lead frame piece |
US20110073999A1 (en) * | 2009-09-30 | 2011-03-31 | Zhi Qiang Niu | Mixed alloy lead frame for packaging power semiconductor devices and its fabrication method |
CN206558497U (en) * | 2017-03-24 | 2017-10-13 | 王刚 | A kind of leads of semiconductor device framework of use TO types encapsulation |
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2017
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN201215803Y (en) * | 2008-10-07 | 2009-04-01 | 宁波华龙电子股份有限公司 | Double-row double-column transistor lead frame plate piece |
US20110073999A1 (en) * | 2009-09-30 | 2011-03-31 | Zhi Qiang Niu | Mixed alloy lead frame for packaging power semiconductor devices and its fabrication method |
CN102034782A (en) * | 2009-09-30 | 2011-04-27 | 万国半导体有限公司 | Mixed alloy lead frame used for power semiconductors |
CN201549494U (en) * | 2009-12-22 | 2010-08-11 | 宁波华龙电子股份有限公司 | High-frequency triode lead frame component |
CN201584407U (en) * | 2009-12-22 | 2010-09-15 | 宁波华龙电子股份有限公司 | Dual-diode lead frame piece |
CN206558497U (en) * | 2017-03-24 | 2017-10-13 | 王刚 | A kind of leads of semiconductor device framework of use TO types encapsulation |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109119397A (en) * | 2018-10-24 | 2019-01-01 | 扬州扬杰电子科技股份有限公司 | A kind of ultrathin type stamp-mounting-paper diode frame |
CN112289752A (en) * | 2020-12-01 | 2021-01-29 | 江苏捷捷微电子股份有限公司 | Flip GaN power device packaging structure and preparation method thereof |
CN112289752B (en) * | 2020-12-01 | 2023-04-11 | 江苏捷捷微电子股份有限公司 | Flip GaN power device packaging structure and preparation method thereof |
CN116721950A (en) * | 2023-08-09 | 2023-09-08 | 天津安联信科技有限公司 | Semiconductor device encapsulation processingequipment |
CN116721950B (en) * | 2023-08-09 | 2023-10-13 | 天津安联信科技有限公司 | Semiconductor device encapsulation processingequipment |
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