CN106783654A - The preparation method of bare chip test protection structure - Google Patents
The preparation method of bare chip test protection structure Download PDFInfo
- Publication number
- CN106783654A CN106783654A CN201611064901.2A CN201611064901A CN106783654A CN 106783654 A CN106783654 A CN 106783654A CN 201611064901 A CN201611064901 A CN 201611064901A CN 106783654 A CN106783654 A CN 106783654A
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- Prior art keywords
- protective cover
- bare chip
- pcb board
- insulating oil
- electric insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Micromachines (AREA)
Abstract
The present invention discloses a kind of preparation method of bare chip test protection structure.The method includes：Choose pcb board 101 and make pad 104 on the surface of pcb board 101；Specified location on the surface of pcb board 101 bonds bare chip 103；The two ends of bonding wire 105 are bonded on the metal PAD of bare chip 103 and pad 104 using bonding technology；Choose protective cover 102 and make perforate 106 on the surface of protective cover 102；Protective cover 102 is bonded on pcb board 101；Electric insulating oil 107 is injected into the inside of protective cover 102 so as to form bare chip test protection structure 100 by the perforate 113 on the surface of protective cover 102.The embodiment of the present invention, bare chip test protection structure interior sealing has certain electric insulating oil, enough within the time of chip package window phase, for test bare chip provides protection, it is to avoid bare chip and the aerial oxidation of bonding wire.
Description
Technical field
The present invention relates to test of semiconductor integrated circuit technical field, it is related to a kind of system of bare chip test protection structure
Make method.
Background technology
As the competition of electronics market is more and more fierce, each chip manufacturer needs to release chip product at faster speed
Product capture early stage market, strive for obtaining more profits.After the completion of chip flow, typically by nude film be packaged in plastic material or
In ceramic material, environmental protection is provided to it.Then various functions test can just be carried out.The encapsulation cycle occupies the test of preciousness
Time, slowing down the market-oriented paces of product, therefore test is carried out to bare chip turns into the focus studied in the world.
Wafer-level test can be tested bare chip by wafer probe and special test platform, but is merely able to complete more
Simple test assignment, there is more limitation in terms of the test of chip actual functional capability；External some companies release KGD
(Known Good Die) naked core flake products, are tested bare chip using special fixture, the specific customization of fixture and are opened
The hair cycle can not still meet the ageing requirement of chip testing；At present, what is more commonly used is that bare chip is fixed on pcb board,
Chip pin and pcb board pad are attached using bonder, then covering protection is carried out to total with glue special, i.e.,
Comprehensive functional test can be carried out to chip in laboratory environment.But glue is difficult to be removed from naked core once solidifying and becoming, can
Maintainability is not good, and the contact connection between bonding wire is likely to result in during glue covering bare chip, and reliability is poor.
The content of the invention
In order to solve above-mentioned technical problem, the invention provides a kind of making side of bare chip test protection structure
Method.
The preparation method that one embodiment of the invention provides a kind of bare chip test protection structure 100, including：
Choose pcb board 101 and make pad 104 on the surface of the pcb board 101；
Specified location on the surface of the pcb board 101 bonds bare chip 103；
The two ends of bonding wire 105 are bonded to the metal PAD and the pad of the bare chip 103 using bonding technology
On 104；
Choose protective cover 102 and make perforate 106 on the surface of the protective cover 102；
The protective cover 102 is bonded on the pcb board 101 so that the bare chip 103, the pad 104 and institute
Bonding wire 105 is stated to be packaged in the lump in the protective cover 102；
Electric insulating oil 107 is injected into the protective cover 102 by the perforate 113 on the surface of the protective cover 102
Inside is so as to form the bare chip test protection structure 100.
In one embodiment of the invention, pad 104 is made on the surface of the pcb board 101, including：
The pad 104 uses electroplating mild alloy technique, and interlaced is arranged in described in the bonding of the surface of the pcb board 101
The area periphery of bare chip 103.
In one embodiment of the invention, the specified location on the surface of the pcb board 101 bonds bare chip 103, bag
Include：
Specified location on the surface of the pcb board 101 makes the first boundary line 201 for bonding the bare chip 103；
Smear conducting resinl in first boundary line 201, and the bare chip 103 is bonded in described states the first border
In line 201.
In one embodiment of the invention, perforate 106 is made on the surface of the protective cover 102, including：
Using boring bar tool in two perforates 106 of diagonally opposed making of the upper surface of the protective cover 102, one of them
Used as the injection orifice of the electric insulating oil 107, another is used as steam vent.
In one embodiment of the invention, the perforate for electric insulating oil 107 being passed through into the surface of the protective cover 102
113 are injected into inside the protective cover 102, including：
The electric insulating oil 107 is injected to the injection orifice using syringe 401, whether is had in the observation steam vent
Whether the electric insulating oil 107 overflows to determine be filled with the electric insulating oil 107 in the protective cover 102.
In one embodiment of the invention, the protective cover 102 is bonded on the pcb board 101, including：
Specified location on the surface of the pcb board 101 makes the second boundary line 202 for bonding the protective cover 102；
Adhesive glue is smeared along the border of the second boundary line 202, and the protective cover 102 is bonded in described states second
On boundary line 202.
In one embodiment of the invention, electric insulating oil 107 is being passed through to be opened described in the surface of the protective cover 102
Hole 106 is injected into after the inside of the protective cover 102, is also included：
One layer of fluid sealant is smeared in the upper surface of the protective cover 102 to be sealed with to the perforate 106.
Compared with prior art, beneficial effects of the present invention are：
1. simple structure of the present invention, low cost, it is easy to process, engineer applied exploitativeness is good；
2. the protective cover interior sealing after the completion of has certain electric insulating oil, can avoid bare chip and bonding wire in atmosphere
Oxidation；
3. electric insulation oil mobility is preferable, the bonding wire being likely to result in during can avoiding general glue covering nude film
Between contact connection；
4. staggered binding pad to be reduced and touch connection between adjacent bonding wire；
If 5. bare chip is damaged in test process, directly removal protective cover and clean by electric insulating oil to bare chip
Changed, it is ensured that the recycling of test pcb board.
Brief description of the drawings
For clear the explanation embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing skill
The accompanying drawing to be used needed for art description is briefly described.Drawings in the following description are some embodiments of the present invention, right
In those of ordinary skill in the art, on the premise of not paying creative work, can also obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation of bare chip test protection structure provided in an embodiment of the present invention；
Fig. 2 is a kind of layout-design schematic diagram of pcb board provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation of protective cover provided in an embodiment of the present invention；
Fig. 4 is a kind of schematic diagram of syringe provided in an embodiment of the present invention；
Fig. 5 is a kind of preparation method schematic flow sheet of bare chip test protection structure provided in an embodiment of the present invention；
Fig. 6 a- Fig. 6 e are that a kind of technological process of bare chip test protection structure provided in an embodiment of the present invention is illustrated
Figure.
Specific embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Case is described in further detail to a kind of bare chip test protection structure of the invention and preparation method.Example only represents possible
Change, unless explicitly requested, otherwise single components and functionality is optional, and the order for operating can change.Some realities
The part and feature of applying scheme can be included in or replace part and the feature of other embodiments.Embodiment of the present invention
Scope including claims gamut, and claims all obtainable equivalent.
The present invention is described in further details below in conjunction with the accompanying drawings.
Embodiment one
Please also refer to Fig. 1, Fig. 2, Fig. 3 and Fig. 4, Fig. 1 is protected for a kind of bare chip test provided in an embodiment of the present invention
The structural representation of protection structure；Fig. 2 is a kind of layout-design schematic diagram of pcb board provided in an embodiment of the present invention；Fig. 3 is this hair
A kind of structural representation of protective cover that bright embodiment is provided；Fig. 4 is a kind of signal of syringe provided in an embodiment of the present invention
Figure.Wherein, the structure 100 includes：Pcb board 101, protective cover 102, bare chip 103, pad 104, bonding wire 105, perforate 106
With electric insulating oil 107.
Wherein, pcb board 101 is used to carry bare chip 103 and protective cover 102, and protective cover 102 is bonded in using fluid sealant
On pcb board 101, isolation contact of the bare chip 103 with air of electric insulating oil 107.
Wherein, being made on pcb board 101 has staggered pad 104, for providing bonding point for the bonding of bare chip 103, its
Made using electroplating mild alloy technique, and electronickelling is used as underlying metal, to improve the bond strength of bonding wire 105.Bonding wire 105
Preferably spun gold.
Wherein, first pad 104 is staggered on the main PCB plate 101, the staggered row of the second pad 106
It is listed on the secondary pcb board 102.
Wherein, adhesive glue is used for the bonding between protective cover 102 and pcb board 101, using the teaching of the invention it is possible to provide the cohesive force of sufficient intensity,
Such as single-component room-temperature vulcanized silicone rubber or glass cement.
Fig. 5 is referred to, Fig. 5 is a kind of preparation method stream of bare chip test protection structure provided in an embodiment of the present invention
Journey schematic diagram.The preparation method comprises the following steps：
Choose pcb board 101 and make pad 104 on the surface of the pcb board 101；
Specified location on the surface of the pcb board 101 bonds bare chip 103；
The two ends of bonding wire 105 are bonded to the metal PAD and the pad of the bare chip 103 using bonding technology
On 104；
Choose protective cover 102 and make perforate 106 on the surface of the protective cover 102；
The protective cover 102 is bonded on the pcb board 101 so that the bare chip 103, the pad 104 and institute
Bonding wire 105 is stated to be packaged in the lump in the protective cover 102；
Electric insulating oil 107 is injected into the protective cover 102 by the perforate 113 on the surface of the protective cover 102
Inside is so as to form the bare chip test protection structure 100.
Specifically, pad 104 is made on the surface of the pcb board 101, including：
The pad 104 uses electroplating mild alloy technique, and interlaced is arranged in described in the bonding of the surface of the pcb board 101
The area periphery of bare chip 103.
In addition, the specified location on the surface of the pcb board 101 bonds bare chip 103, including：
Specified location on the surface of the pcb board 101 makes the first boundary line 201 for bonding the bare chip 103；
Smear conducting resinl in first boundary line 201, and the bare chip 103 is bonded in described states the first border
In line 201.
Alternatively, perforate 106 is made on the surface of the protective cover 102, including：
Using boring bar tool in two perforates 106 of diagonally opposed making of the upper surface of the protective cover 102, one of them
Used as the injection orifice of the electric insulating oil 107, another is used as steam vent.
Preferably, electric insulating oil 107 is injected into the guarantor by the perforate 113 on the surface of the protective cover 102
Inside shield 102, including：
The electric insulating oil 107 is injected to the injection orifice using syringe 401, whether is had in the observation steam vent
Whether the electric insulating oil 107 overflows to determine be filled with the electric insulating oil 107 in the protective cover 102.
Alternatively, the protective cover 102 is bonded on the pcb board 101, including：
Specified location on the surface of the pcb board 101 makes the second boundary line 202 for bonding the protective cover 102；
Adhesive glue is smeared along the border of the second boundary line 202, and the protective cover 102 is bonded in described states second
On boundary line 202.
In addition, electric insulating oil 107 is being injected into the guarantor by the perforate 106 on the surface of the protective cover 102
After the inside of shield 102, also include：
One layer of fluid sealant is smeared in the upper surface of the protective cover 102 to be sealed with to the perforate 106.
The present embodiment, protective cover interior sealing has certain electric insulating oil, can avoid bare chip and bonding wire in atmosphere
Oxidation；Staggered binding pad to be reduced and touch connection between adjacent bonding wire；If bare chip is damaged in test process,
Directly remove protective cover and bare chip is changed by cleaning electric insulating oil, it is ensured that the recycling of test pcb board；
Its simple structure, low cost, it is easy to process, there is practical value higher.
Embodiment two
Fig. 6 a- Fig. 6 e, Fig. 6 a- Fig. 6 e are referred to for a kind of bare chip test protection structure provided in an embodiment of the present invention
Process flow diagram.The present embodiment is described in detail on the basis of above-described embodiment to preparation method of the invention
It is as follows：
Step one：Circuit board prepare, as depicted in figs. 1 and 2, circuit board include pcb board 101, staggered pad 104,
Chip bonds boundary line 201, protective cover and bonds boundary line 202.Pcb board 101 is used using traditional hardboard PCB, binding pad 104
The mode of electroplating mild alloy is produced on pcb board 101, and thickness is, for example, 3um, and electronickelling is used as underlying metal, to facilitate spun gold
Bonding；Protective cover bonds boundary line 202 and chip is bonded boundary line 201 and is produced on pcb board 101 by the way of silk-screen,
Respectively bonded areas of protective cover 102 and bare chip 103.
Step 2：Protective cover perforate, using boring bar tool in the diagonally opposed making perforate 106 of protective cover 102, one of them
Used as electric insulating oil injection orifice, another is used as steam vent.As shown in Figure 3.
Step 3：Pcb board and protective cover are cleaned, and using absolute alcohol or acetone as cleaning fluid, are cleaned using ultrasonic wave
Mode remove impurity on pcb board 101 and protective cover 102.Pcb board 101 after cleaning is as shown in Figure 6 a.
Step 4：Chip is bonded, and the chip using Manual dispenser on pcb board 101 is bonded to be smeared in boundary line 201 and fitted
Work as conducting resinl, bare chip 103 is bonded in into chip bonds in boundary line 201, is then toasted 2 hours in sintering baking oven, temperature
It it is 150 DEG C, so that conductive adhesive curing.Bond the pcb board 101 after bare chip 103 as shown in Figure 6 b.
Step 5：Chip bonding, bare chip bonding selects ultrasonic thermocompression Welding, using manual bonder, bonding wire 105
From spun gold, diameter is, for example, 25um, the good pcb board 101 of bonding die is placed on pressure welding base and is fixed, and is preheated 2~3 minutes,
The manual bonder operation handle of movement completes bare chip 103 and is bonded, and the pcb board 101 after bonding is as fig. 6 c.
Step 6：Protective cover is bonded, and bonding boundary line 202 along the protective cover on pcb board 101 smears adhesive glue, such as silicon rubber
Glue or glass cement, protective cover 102 is bonded on pcb board 101, pcb board 101 is stood at room temperature, until adhesive glue is completely solid
Change, bond the pcb board 101 after protective cover 102 as shown in fig 6d.
Step 7：Electric insulating oil is injected, using syringe 401 using wherein in the perforate 106 on protective cover 102
It is individual to electric insulating oil is injected in protective cover, another perforate, until steam vent has electric insulating oil to overflow, stops as steam vent
Only electric insulating oil injection.
Step 8：Perforate is sealed, and one layer of fluid sealant 601, such as silicon rubber or glass cement are smeared on protective cover 102, right
Perforate 106 on protective cover 102 is sealed.
Step 9：Pcb board 101 is stood at room temperature, until fluid sealant is fully cured.Ultimately form bare chip test guarantor
Protection structure.Pcb board 101 after sealing glue solidifying is as shown in fig 6e.
It is emphasized that the step in above-described embodiment has no specific ordinal relation, in operation can be according to reality
Border situation is implemented.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to assert
Specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should be all considered as belonging to of the invention
Protection domain.
Claims (7)
1. a kind of bare chip test preparation method of protection structure (100), it is characterised in that including：
Choose pcb board (101) and make pad (104) on the pcb board (101) surface；
Specified location on the pcb board (101) surface bonds bare chip (103)；
The two ends of bonding wire (105) are bonded to the metal PAD and the pad of the bare chip (103) using bonding technology
(104) on；
Choose protective cover (102) and make perforate (106) on the protective cover (102) surface；
The protective cover (102) is bonded on the pcb board (101) so that the bare chip (103), the pad (104)
And the bonding wire (105) is packaged in the protective cover (102) in the lump；
Electric insulating oil (107) is injected into the protective cover by the perforate (113) on the protective cover (102) surface
(102) it is internal so as to form the bare chip test protection structure (100).
2. preparation method according to claim 1, it is characterised in that make pad on the pcb board (101) surface
(104), including：
The pad (104) uses electroplating mild alloy technique, and interlaced is arranged in described in the bonding of the pcb board (101) surface
The area periphery of bare chip (103).
3. preparation method according to claim 1, it is characterised in that the specified location on the pcb board (101) surface is glued
Knot bare chip (103), including：
Specified location on the pcb board (101) surface makes the first boundary line (201) for bonding the bare chip (103)；
Smear conducting resinl in first boundary line (201), and the bare chip (103) is bonded in described states the first border
In line (201).
4. preparation method according to claim 1, it is characterised in that make perforate on the protective cover (102) surface
(106), including：
Using boring bar tool in two perforates (106) of the diagonally opposed making in the protective cover (102) upper surface, one of them
Used as the injection orifice of the electric insulating oil (107), another is used as steam vent.
5. preparation method according to claim 4, it is characterised in that by electric insulating oil (107) by the protective cover
(102) perforate (113) on surface is injected into the protective cover (102) inside, including：
The electric insulating oil (107) is injected to the injection orifice using syringe (401), whether is had in the observation steam vent
Whether the electric insulating oil (107) overflows to determine be filled with the electric insulating oil (107) in the protective cover (102).
6. preparation method according to claim 1, it is characterised in that the protective cover (102) is bonded in the pcb board
(101) on, including：
Specified location on the pcb board (101) surface makes the second boundary line (202) for bonding the protective cover (102)；
Adhesive glue is smeared along the border of the second boundary line (202), and the protective cover (102) is bonded in described states second
On boundary line (202).
7. preparation method according to claim 1, it is characterised in that by electric insulating oil (107) by the protection
The perforate (106) for covering (102) surface is injected into after the protective cover (102) inside, is also included：
One layer of fluid sealant is smeared in the upper surface of the protective cover (102) to be sealed with to the perforate (106).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611064901.2A CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611064901.2A CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106783654A true CN106783654A (en) | 2017-05-31 |
| CN106783654B CN106783654B (en) | 2019-12-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611064901.2A Active CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109884504A (en) * | 2019-03-14 | 2019-06-14 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip capacity detection method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124834A1 (en) * | 2001-12-31 | 2003-07-03 | Siliconware Precision Industries Co., Ltd., | Method and system of wire bonding for use in fabrication of semiconductor package |
| CN201234402Y (en) * | 2008-07-14 | 2009-05-06 | 比亚迪股份有限公司 | PCB board |
| CN101814443A (en) * | 2010-03-31 | 2010-08-25 | 中国人民解放军国防科学技术大学 | Chip design method for multi-chip module of high-performance processor with optical interface |
| CN203827682U (en) * | 2014-04-24 | 2014-09-10 | 中兴通讯股份有限公司 | Mobile communication terminal |
-
2016
- 2016-11-28 CN CN201611064901.2A patent/CN106783654B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124834A1 (en) * | 2001-12-31 | 2003-07-03 | Siliconware Precision Industries Co., Ltd., | Method and system of wire bonding for use in fabrication of semiconductor package |
| CN201234402Y (en) * | 2008-07-14 | 2009-05-06 | 比亚迪股份有限公司 | PCB board |
| CN101814443A (en) * | 2010-03-31 | 2010-08-25 | 中国人民解放军国防科学技术大学 | Chip design method for multi-chip module of high-performance processor with optical interface |
| CN203827682U (en) * | 2014-04-24 | 2014-09-10 | 中兴通讯股份有限公司 | Mobile communication terminal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109884504A (en) * | 2019-03-14 | 2019-06-14 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip capacity detection method |
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| CN106783654B (en) | 2019-12-13 |
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