CN106783654B - Method for manufacturing protection structure for testing bare chip - Google Patents
Method for manufacturing protection structure for testing bare chip Download PDFInfo
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- CN106783654B CN106783654B CN201611064901.2A CN201611064901A CN106783654B CN 106783654 B CN106783654 B CN 106783654B CN 201611064901 A CN201611064901 A CN 201611064901A CN 106783654 B CN106783654 B CN 106783654B
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- protective cover
- bonding
- bare chip
- pcb
- insulating oil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a manufacturing method of a protection structure for testing a bare chip. The method comprises the following steps: selecting a PCB (printed Circuit Board) 101 and manufacturing a bonding pad 104 on the surface of the PCB 101; bonding a bare chip 103 at a designated position on the surface of the PCB 101; bonding two ends of a bonding wire 105 on the metal PAD and the bonding PAD 104 of the bare chip 103 by adopting a bonding process; selecting a protective cover 102 and manufacturing an opening 106 on the surface of the protective cover 102; bonding the protective cover 102 to the PCB 101; an electrically insulating oil 107 is injected into the protective cover 102 through the opening 106 on the surface of the protective cover 102 to form the protective structure 100 for a bare chip test. In the embodiment of the invention, certain electrical insulating oil is sealed in the bare chip test protection structure, which is enough to protect the test bare chip within the time of a chip packaging window period and avoid the oxidation of the bare chip and the bonding wire in the air.
Description
Technical Field
the invention relates to the technical field of semiconductor integrated circuit testing, in particular to a manufacturing method of a protection structure for bare chip testing.
Background
With the increasingly competitive market of electronic products, chip manufacturers need to push out chip products at a faster rate to occupy the early market and strive for more profits. After the chip flow is completed, the die is typically encapsulated in a plastic or ceramic material to provide environmental protection. Then various functional tests can be performed. The packaging period occupies valuable testing time, and the marketization pace of the product is slowed down, so that the testing of the bare chip becomes a hot point of international research.
Wafer level testing can test bare chips through a wafer probe and a special test table, but can only complete simpler testing tasks, and has more limitations in the aspect of testing actual functions of the chips; some foreign companies launch KGD (dark Good Die) bare chip products, test the bare chip by adopting a special fixture, and the special customization and development period of the fixture still cannot meet the timeliness requirement of chip testing; at present, it is relatively common to fix a bare chip on a PCB, connect chip pins and a pad of the PCB using a bonding machine, and then cover and protect the whole structure with special glue, so as to perform a comprehensive functional test on the chip in a laboratory environment. However, once the glue is cured, it is difficult to remove the glue from the bare chip, the maintainability is poor, and the contact connection between bonding wires may be caused in the process of covering the bare chip by the glue, and the reliability is poor.
disclosure of Invention
in order to solve the above technical problems, the present invention provides a method for manufacturing a protection structure for a bare chip test.
An embodiment of the present invention provides a method for manufacturing a protection structure 100 for a die test, including:
selecting a PCB (printed Circuit Board) 101 and manufacturing a bonding pad 104 on the surface of the PCB 101;
Bonding a bare chip 103 at a designated position on the surface of the PCB 101;
Bonding two ends of a bonding wire 105 on the metal PAD of the bare chip 103 and the bonding PAD 104 by adopting a bonding process;
Selecting a protective cover 102 and manufacturing an opening 106 on the surface of the protective cover 102;
adhering the protective cover 102 to the PCB 101 such that the bare chip 103, the bonding pad 104 and the bonding wire 105 are packaged together in the protective cover 102;
An electrically insulating oil 107 is injected into the protective cover 102 through the opening 106 on the surface of the protective cover 102 to form the protective structure 100 for die testing.
In an embodiment of the present invention, the fabricating the pad 104 on the surface of the PCB 101 includes:
The bonding pads 104 are arranged on the periphery of the area, bonded with the bare chip 103, on the surface of the PCB 101 in a staggered manner by adopting a soft gold electroplating process.
In one embodiment of the present invention, the bonding of the bare chip 103 at a designated position on the surface of the PCB board 101 includes:
Manufacturing a first boundary line 201 for bonding the bare chip 103 at a designated position on the surface of the PCB 101;
A conductive paste is applied inside the first boundary line 201, and the bare chip 103 is bonded inside the first boundary line 201.
In one embodiment of the present invention, the forming of the opening 106 on the surface of the protection cover 102 includes:
Two of the openings 106 are formed in the upper surface of the protective cover 102 in the angular direction using a drilling tool, one of which serves as an injection hole for the electrically insulating oil 107 and the other serves as a discharge hole.
In one embodiment of the present invention, injecting an electrical insulating oil 107 into the interior of the protective cover 102 through the opening 106 on the surface of the protective cover 102 includes:
the electrical insulating oil 107 is injected into the injection hole using a syringe 401, and whether the electrical insulating oil 107 overflows from the exhaust hole is observed to determine whether the electrical insulating oil 107 is filled in the protective cover 102.
in one embodiment of the present invention, the bonding of the protection cover 102 to the PCB board 101 includes:
manufacturing a second boundary line 202 for bonding the protective cover 102 at a designated position on the surface of the PCB 101;
adhesive glue is applied along the border of the second border line 202 and the protective cover 102 is adhered to the second border line 202.
In an embodiment of the present invention, after injecting the electrical insulating oil 107 into the interior of the protective cover 102 through the opening 106 on the surface of the protective cover 102, the method further includes:
A layer of sealant is applied to the upper surface of the protective cover 102 to seal the opening 106.
compared with the prior art, the invention has the beneficial effects that:
1. The invention has simple structure, low cost, easy processing and good engineering application feasibility;
2. Certain electric insulating oil is sealed in the finished protective cover, so that the bare chip and the bonding wire can be prevented from being oxidized in the air;
3. the electrical insulating oil has good fluidity, and can avoid the contact connection between bonding wires possibly caused in the process of covering the bare chip by common glue;
4. the staggered binding pads reduce the touch connection between adjacent bonding wires;
5. If the bare chip is damaged in the testing process, the bare chip can be replaced by directly removing the protective cover and cleaning the electrical insulating oil, so that the reutilization of the testing PCB is ensured.
Drawings
For the purpose of clearly illustrating the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. The drawings in the following description are examples of the present invention, and other drawings may be derived from those drawings by those skilled in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a protection structure for a bare chip test according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a layout design of a PCB board according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a protective cover according to an embodiment of the present invention;
FIG. 4 is a schematic view of a syringe provided in accordance with an embodiment of the present invention;
FIG. 5 is a schematic flow chart illustrating a method for fabricating a protection structure for a bare chip test according to an embodiment of the present invention;
fig. 6 a-6 e are schematic process flow diagrams of a protection structure for a die test according to an embodiment of the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the following describes a protection structure for a bare chip test and a manufacturing method thereof in detail with reference to the accompanying drawings and specific embodiments. Examples merely typify possible variations, individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims.
the present invention will be described in further detail with reference to the accompanying drawings.
example one
referring to fig. 1, fig. 2, fig. 3 and fig. 4 together, fig. 1 is a schematic structural diagram of a protection structure for a bare chip test according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a layout design of a PCB board according to an embodiment of the present invention; fig. 3 is a schematic structural diagram of a protective cover according to an embodiment of the present invention; fig. 4 is a schematic view of a syringe according to an embodiment of the present invention. Wherein the structure 100 comprises: PCB board 101, protective cover 102, bare chip 103, bonding pad 104, bonding wire 105, opening 106 and electrically insulating oil 107.
The PCB 101 is used to carry the bare chip 103 and the protection cover 102, the protection cover 102 is bonded to the PCB 101 by using a sealant, and the electrical insulating oil 107 isolates the bare chip 103 from air.
The PCB 101 is provided with staggered bonding pads 104 for providing bonding points for bonding the bare chip 103, and is manufactured by adopting a soft gold electroplating process, and nickel is electroplated as bottom metal to improve the bonding strength of the bonding wire 105. The bonding wire 105 is preferably a gold wire.
the first pads 104 are staggered on the main PCB 101, and the second pads 106 are staggered on the sub PCB 102.
in which an adhesive paste is used for bonding between the protective cover 102 and the PCB board 101, which can provide a sufficient strength of adhesion, such as a one-component room temperature vulcanized silicone rubber or a glass paste.
referring to fig. 5, fig. 5 is a flowchart illustrating a method for manufacturing a protection structure for a die test according to an embodiment of the present invention. The manufacturing method comprises the following steps:
selecting a PCB (printed Circuit Board) 101 and manufacturing a bonding pad 104 on the surface of the PCB 101;
bonding a bare chip 103 at a designated position on the surface of the PCB 101;
bonding two ends of a bonding wire 105 on the metal PAD of the bare chip 103 and the bonding PAD 104 by adopting a bonding process;
selecting a protective cover 102 and manufacturing an opening 106 on the surface of the protective cover 102;
adhering the protective cover 102 to the PCB 101 such that the bare chip 103, the bonding pad 104 and the bonding wire 105 are packaged together in the protective cover 102;
An electrically insulating oil 107 is injected into the protective cover 102 through the opening 106 on the surface of the protective cover 102 to form the protective structure 100 for die testing.
Specifically, the manufacturing of the pad 104 on the surface of the PCB 101 includes:
the bonding pads 104 are arranged on the periphery of the area, bonded with the bare chip 103, on the surface of the PCB 101 in a staggered manner by adopting a soft gold electroplating process.
in addition, the bare chip 103 is bonded at a designated position on the surface of the PCB board 101, including:
Manufacturing a first boundary line 201 for bonding the bare chip 103 at a designated position on the surface of the PCB 101;
A conductive paste is applied inside the first boundary line 201, and the bare chip 103 is bonded inside the first boundary line 201.
optionally, making an opening 106 on the surface of the protective cover 102 includes:
Two of the openings 106 are formed in the upper surface of the protective cover 102 in the angular direction using a drilling tool, one of which serves as an injection hole for the electrically insulating oil 107 and the other serves as a discharge hole.
Preferably, injecting an electrical insulating oil 107 into the interior of the protective cover 102 through the opening 106 on the surface of the protective cover 102 includes:
The electrical insulating oil 107 is injected into the injection hole using a syringe 401, and whether the electrical insulating oil 107 overflows from the exhaust hole is observed to determine whether the electrical insulating oil 107 is filled in the protective cover 102.
optionally, bonding the protective cover 102 to the PCB board 101 includes:
manufacturing a second boundary line 202 for bonding the protective cover 102 at a designated position on the surface of the PCB 101;
adhesive glue is applied along the border of the second border line 202 and the protective cover 102 is adhered to the second border line 202.
In addition, after injecting the electrical insulating oil 107 into the interior of the protective cover 102 through the opening 106 on the surface of the protective cover 102, the method further includes:
a layer of sealant is applied to the upper surface of the protective cover 102 to seal the opening 106.
In the embodiment, a certain amount of electrical insulating oil is sealed in the protective cover, so that the bare chip and the bonding wire can be prevented from being oxidized in the air; the staggered binding pads reduce the touch connection between adjacent bonding wires; if the bare chip is damaged in the testing process, the bare chip can be replaced by directly removing the protective cover and cleaning the electrical insulating oil, so that the reutilization of the testing PCB is ensured; the structure is simple, the cost is low, the processing is easy, and the practical value is high.
Example two
Referring to fig. 6a to 6e, fig. 6a to 6e are schematic process flow diagrams of a protection structure for a die test according to an embodiment of the present invention. In this embodiment, the manufacturing method of the present invention is explained in detail below based on the above embodiments:
the method comprises the following steps: a circuit board is prepared, as shown in fig. 1 and 2, including a PCB board 101, staggered pads 104, a chip bonding boundary line 201, and a shield case bonding boundary line 202. The PCB 101 is a traditional hard PCB, the binding pad 104 is made on the PCB 101 by electroplating soft gold, the thickness is 3um for example, and nickel is electroplated as bottom metal to facilitate gold wire bonding; the protective cover bonding boundary line 202 and the chip bonding boundary line 201 are both manufactured on the PCB 101 by silk-screen printing, and are bonding areas of the protective cover 102 and the bare chip 103, respectively.
Step two: the protective cover is perforated, and perforations 106 are made diagonally in the protective cover 102 using a perforating tool, one of which serves as an electrical insulating oil injection hole and the other serves as a vent hole. As shown in fig. 3.
Step three: and cleaning the PCB and the protective cover, wherein absolute ethyl alcohol or acetone is used as a cleaning solution, and impurities on the PCB 101 and the protective cover 102 are removed in an ultrasonic cleaning mode. The cleaned PCB board 101 is shown in fig. 6 a.
Step four: chip bonding, in which a manual dispenser is used to coat a proper conductive adhesive in the chip bonding boundary line 201 on the PCB board 101, the bare chip 103 is bonded in the chip bonding boundary line 201, and then baked in a sintering oven at 150 ℃ for 2 hours to cure the conductive adhesive. The PCB board 101 after bonding the bare chip 103 is shown in fig. 6 b.
step five: chip bonding, bare chip bonding selects ultrasonic hot-press bonding process, a manual bonding machine is adopted, a bonding wire 105 selects gold wire with the diameter of 25um for example, the bonded PCB 101 is placed on a press-welding base to be fixed, preheating is carried out for 2-3 minutes, the operation handle of the manual bonding machine is moved to complete bare chip 103 bonding, and the bonded PCB 101 is as shown in fig. 6 c.
Step six: and (3) bonding the protective cover, namely coating bonding glue, such as silicon rubber or glass glue, along a protective cover bonding boundary line 202 on the PCB 101, bonding the protective cover 102 on the PCB 101, standing the PCB 101 at room temperature until the bonding glue is completely cured, and bonding the PCB 101 with the protective cover 102 as shown in FIG. 6 d.
step seven: injecting the electric insulating oil, injecting the electric insulating oil into the protective cover by using the injector 401 through one of the openings 106 on the protective cover 102, and using the other opening as a vent hole until the electric insulating oil overflows from the vent hole, and stopping injecting the electric insulating oil.
Step eight: the opening is sealed by applying a layer of sealant 601, such as silicone rubber or glass cement, over the protective cover 102 to seal the opening 106 in the protective cover 102.
step nine: the PCB board 101 is left at room temperature until the sealant is fully cured. And finally forming the protection structure for testing the bare chip. The PCB board 101 after curing the sealant is shown in fig. 6 e.
it should be emphasized that the steps in the above embodiments have no specific order relationship, and the operation can be implemented according to actual situations.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. a method for fabricating a protection structure (100) for die testing, comprising:
selecting a PCB (101) and manufacturing a bonding pad (104) on the surface of the PCB (101);
bonding a bare chip (103) at a designated position on the surface of the PCB (101);
bonding two ends of a bonding wire (105) on the metal PAD of the bare chip (103) and the bonding PAD (104) by adopting a bonding process;
selecting a protective cover (102) and manufacturing an opening (106) on the surface of the protective cover (102);
Bonding the protective cover (102) on the PCB (101) so that the bare chip (103), the bonding pad (104) and the bonding wire (105) are packaged in the protective cover (102) together;
And injecting an electrical insulating oil (107) into the protective cover (102) through the opening (106) on the surface of the protective cover (102) to form the protective structure (100) for testing the bare chip.
2. the method of claim 1, wherein forming the bonding pads (104) on the surface of the PCB (101) comprises:
the bonding pads (104) are arranged on the periphery of the area, bonded with the bare chip (103), of the surface of the PCB (101) in a staggered mode by adopting a soft gold electroplating process.
3. The method of manufacturing according to claim 1, wherein bonding a bare chip (103) at a designated position on the surface of the PCB board (101) comprises:
Manufacturing a first boundary line (201) for bonding the bare chip (103) at a designated position on the surface of the PCB (101);
And coating conductive adhesive in the first boundary line (201) and bonding the bare chip (103) in the first boundary line (201).
4. The method of claim 1, wherein forming an opening (106) in a surface of the protective cover (102) comprises:
Two of the openings (106) are formed in the upper surface of the protective cover (102) in the angular direction by using a drilling tool, one of which serves as an injection hole for the electrically insulating oil (107) and the other serves as a vent hole.
5. The method of manufacturing according to claim 4, wherein injecting an electrically insulating oil (107) into the interior of the protective cover (102) through the opening (106) in the surface of the protective cover (102) comprises:
injecting the electrical insulating oil (107) into the injection hole by using a syringe (401), and observing whether the electrical insulating oil (107) overflows from the exhaust hole to determine whether the electrical insulating oil (107) is fully stored in the protective cover (102).
6. The method of manufacturing according to claim 1, wherein bonding the protective cover (102) to the PCB board (101) comprises:
manufacturing a second boundary line (202) for bonding the protective cover (102) at a designated position on the surface of the PCB (101);
and (3) coating adhesive glue along the boundary of the second boundary line (202), and adhering the protective cover (102) to the second boundary line (202).
7. The method of manufacturing according to claim 1, further comprising, after injecting an electrical insulating oil (107) into the interior of the protective cover (102) through the opening (106) in the surface of the protective cover (102):
and coating a layer of sealant on the upper surface of the protective cover (102) to seal the opening (106).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201611064901.2A CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611064901.2A CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
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| CN106783654A CN106783654A (en) | 2017-05-31 |
| CN106783654B true CN106783654B (en) | 2019-12-13 |
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| CN201611064901.2A Active CN106783654B (en) | 2016-11-28 | 2016-11-28 | Method for manufacturing protection structure for testing bare chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109884504A (en) * | 2019-03-14 | 2019-06-14 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip capacity detection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201234402Y (en) * | 2008-07-14 | 2009-05-06 | 比亚迪股份有限公司 | PCB board |
| CN101814443A (en) * | 2010-03-31 | 2010-08-25 | 中国人民解放军国防科学技术大学 | Chip design method for multi-chip module of high-performance processor with optical interface |
| CN203827682U (en) * | 2014-04-24 | 2014-09-10 | 中兴通讯股份有限公司 | Mobile communication terminal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW513795B (en) * | 2001-12-31 | 2002-12-11 | Siliconware Precision Industries Co Ltd | Wire bonding method and system for fabricating semiconductor package |
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- 2016-11-28 CN CN201611064901.2A patent/CN106783654B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201234402Y (en) * | 2008-07-14 | 2009-05-06 | 比亚迪股份有限公司 | PCB board |
| CN101814443A (en) * | 2010-03-31 | 2010-08-25 | 中国人民解放军国防科学技术大学 | Chip design method for multi-chip module of high-performance processor with optical interface |
| CN203827682U (en) * | 2014-04-24 | 2014-09-10 | 中兴通讯股份有限公司 | Mobile communication terminal |
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