CN106847719B - Naked core chip architecture and its manufacturing method applied to test - Google Patents
Naked core chip architecture and its manufacturing method applied to test Download PDFInfo
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- CN106847719B CN106847719B CN201611064905.0A CN201611064905A CN106847719B CN 106847719 B CN106847719 B CN 106847719B CN 201611064905 A CN201611064905 A CN 201611064905A CN 106847719 B CN106847719 B CN 106847719B
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Microelectronics & Electronic Packaging (AREA)
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- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Tests Of Electronic Circuits (AREA)
- Micromachines (AREA)
Abstract
The present invention discloses a kind of naked core chip architecture and its manufacturing method applied to test.The structure 100 includes: main PCB plate 101, secondary pcb board 102, bare chip 103, pad 104/106, bonding wire 105/107, gasket 110, metal row needle 111, protective cover 112 and electric insulating oil 114；Gasket 110 bonds on main PCB plate 101 and bare chip 103 bonds on gasket 110；Pad 104 is surrounded on 103 surrounding of bare chip and is set on main PCB plate 101 and is connect by bonding wire 105 with the metal PAD of bare chip 103；Secondary pcb board 102, which is located at 104 periphery of pad and bonds on main PCB plate 101 and realized by metal ferrule 111 and main PCB plate 101, to be electrically connected；Pad 106 is set on secondary pcb board 102 and is connect by bonding wire 107 with the metal PAD of bare chip 103；Protective cover 112 is bonded on main PCB plate 101 and injects electric insulating oil 114 inside it.In the present invention, structure is high ladder-like in height, improves the density of bonding wire on unit area, can guarantee that metal PAD avoids bare chip and bonding wire from aoxidizing in air from pollution when bare chip bonding.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit testing, in particular to a connecting and protecting structure of a bare chip and a printed circuit board and a manufacturing method thereof.
Background
After the chip is taped out, the die is typically encapsulated in a plastic or ceramic material to provide environmental protection before various functional tests can be performed. The packaging period occupies valuable testing time, and the marketization pace of the product is slowed down, so that the testing of the bare chip becomes a hot point of international research.
Wafer level testing can test bare chips through a wafer probe and a special test table, but can only complete simpler testing tasks, and has more limitations in the aspect of testing actual functions of the chips; some foreign companies put out KGD (dark Good die) bare chip products, and test the bare chips by adopting special fixtures, and the special customization and development period of the fixtures cannot meet the timeliness requirement of chip testing; at present, it is relatively common to fix a bare chip on a PCB, connect chip pins and a pad of the PCB using a bonding machine, and then cover and protect the whole structure with special glue, so as to perform a comprehensive functional test on the chip in a laboratory environment. However, once cured, the glue is difficult to remove from the die, the maintainability is poor, and the process of covering the die with the glue may cause contact connection between bonding wires, resulting in poor reliability. With the increasing complexity of chips and the hundreds of functional pins, a circle of bonding pads with the same number are required to be processed on a PCB as bonding points, the length requirement of bonding wires and the limitation of the area and the distance of metal bonding pads are caused, the contact connection between the bonding wires is easily caused during bonding, the requirements on the processing precision of the PCB and the technical level of bonding operators are higher, and the effective connection difficulty between a multi-pin bare chip and the PCB is higher under the condition of a common laboratory; the larger the area of the bare chip is, the more conductive adhesive is needed when the bare chip is bonded on the PCB, and when the bare chip is pressed on the PCB, the conductive adhesive can overflow from the side of the bare chip, and the conductive adhesive is easily adhered to a metal PAD of the bare chip, so that a short circuit is formed between the metal PADs, and the bare chip is scrapped.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a bare chip structure for testing and a method for manufacturing the same.
An embodiment of the present invention provides a bare chip structure 100 for testing, including: the PCB comprises a main PCB 101, a secondary PCB 102, a bare chip 103, a first bonding pad 104, a first bonding wire 105, a second bonding pad 106, a second bonding wire 107, a gasket 110, a metal pin 111, a protective cover 112 and electrical insulating oil 114; wherein,
the pad 110 is adhered on the main PCB board 101 and the bare chip 103 is adhered on the pad 110; the first bonding PAD 104 surrounds the bare chip 103, is disposed on the main PCB 101, and is connected to a metal PAD of the bare chip 103 through the first bonding wire 105; the secondary PCB 102 is located at the periphery of the first pad 104, is adhered to the main PCB 101, and is electrically connected to the main PCB 101 through the metal pins 111; the second PAD 106 is disposed on the secondary PCB 102 and connected to the metal PAD of the bare chip 103 through the second bonding wire 107; the protective cover 112 is adhered to the main PCB 101, encloses the sub PCB 102, the bare chip 103, the first pad 104, the first bonding wire 105, the second pad 106, the second bonding wire 107, and the pad 110, and is filled with the electrically insulating oil 114.
In an embodiment of the present invention, the main PCB 101 is provided with a first through hole 108, the sub PCB 102 is correspondingly provided with a second through hole 109, and the metal pin 111 is inserted into the first through hole 108 and the second through hole 109, which are correspondingly provided, to electrically connect the main PCB 101 and the sub PCB 102.
In an embodiment of the present invention, the first pads 104 are staggered on the main PCB 101, and the second pads 106 are staggered on the sub PCB 102.
In one embodiment of the present invention, the upper surface of the protective cover 112 is provided with two openings 113; one of the openings 113 is used for injecting the electrically insulating oil 114 and the other opening 113 is used for venting and observing whether the electrically insulating oil 114 overflows to determine whether the protective cover 112 is filled with the electrically insulating oil 114.
Another embodiment of the present invention provides a method of fabricating a bare chip structure 100 for testing, comprising:
manufacturing a main PCB (printed circuit board) 101, and manufacturing a first bonding pad 104 on the surface of the main PCB 101;
bonding a gasket 110 at a designated position on the surface of the main PCB 101 and bonding a bare chip 103 on the surface of the gasket 110;
bonding two ends of a first bonding wire 105 on the metal PAD of the bare chip 103 and the first bonding PAD 104 by adopting a bonding process;
manufacturing a secondary PCB (printed Circuit Board) 102, and manufacturing a second bonding pad 106 on the surface of the secondary PCB 102;
bonding the sub PCB 102 to the main PCB 101;
bonding two ends of a second bonding wire 107 to the metal PAD of the bare chip 103 and the second bonding PAD 106 by using a bonding process, and connecting the main PCB 101 and the auxiliary PCB 102 by using a metal pin 111 to realize electrical connection;
bonding the protective cover 112 to the main PCB 101 such that the sub-PCB 102, the bare chip 103, the first pad 104, the first bonding wire 105, the second pad 106, the second bonding wire 107 and the pad 110 are collectively encapsulated in the protective cover 112;
injecting an electrical insulating oil 114 into the protective cover 112 through one opening 113 on the surface of the protective cover 112, and observing whether the electrical insulating oil 114 overflows from the other opening 113 on the surface of the protective cover 112 to determine whether the electrical insulating oil 114 is full of the protective cover 112, thereby forming the bare chip structure 100 applied to the test.
In one embodiment of the present invention, the connecting the main PCB 101 and the sub PCB 102 by using the metal pins 111 to realize the electrical connection includes:
a first through hole 108 is formed in the main PCB 101, a second through hole 109 is correspondingly formed in the sub PCB 102, and the metal pin 111 is inserted into the first through hole 108 and the second through hole 109 which are correspondingly formed, so as to electrically connect the main PCB 101 and the sub PCB 102.
In an embodiment of the present invention, after the protective cover 112 is filled with the electrical insulating oil 114, the method further includes:
a layer of sealant is coated on the upper surface of the protective cover 112 to seal the opening 113 of the protective cover 112.
Yet another embodiment of the present invention provides a method of fabricating a bare chip structure 100 for testing, comprising:
selecting a main PCB (printed Circuit Board) 101, and manufacturing a first boundary line 201 for bonding an auxiliary PCB 102, a second boundary line 202 for bonding a gasket 110 and a third boundary line 203 for bonding a protective cover 112 on the surface of the main PCB 101; first bonding pads 104 are manufactured on the surface of the main PCB 101 along the periphery of the second boundary line 202 in a staggered mode;
bonding the PAD 110 on the surface of the main PCB 101 along the second boundary line 202 and bonding the bare chip 103 on the surface of the PAD 110, and connecting the metal PAD of the bare chip 103 and the first PAD 104 by using a first bonding wire 105;
selecting a hollow auxiliary PCB (printed circuit board) 102, manufacturing second PADs 106 which are arranged in a staggered mode on the surface of the auxiliary PCB 102, fixing the auxiliary PCB 102 on the surface of the main PCB 101 along the first boundary line 201, and connecting the metal PAD of the bare chip 103 and the second PADs 106 by adopting a second bonding wire 107;
two openings 113 are formed on the surface of the protection cover 112 and are adhered to the main PCB 101 along the third boundary 203, and an electrical insulating oil 114 is injected into one of the openings 113 and is observed whether the electrical insulating oil 114 overflows from the other opening 113 to determine whether the protection cover 112 is full of the electrical insulating oil 114, thereby forming the bare chip structure 100 applied to the test.
In one embodiment of the present invention, fixing the sub PCB 102 to the surface of the main PCB 101 along the first boundary line 201 includes:
the secondary PCB 102 is bonded to the primary PCB 101 and the secondary PCB 102 are connected by metal pins 111 to achieve electrical connection.
Compared with the prior art, the invention has the beneficial effects that:
1. the gasket is fixed on the main PCB in a bonding mode, so that the complex steps and cost of processing a boss by adopting a direct printed board are avoided;
2. the introduction of the gasket enables the conductive adhesive overflowing during the bonding of the bare chip to flow downwards under the action of gravity, so that the pollution to the metal PAD of the bare chip can be effectively avoided;
3. the staggered binding pads reduce the touch connection between adjacent bonding wires;
4. after the auxiliary PCB is used, the connecting structure is in a high-low high-order ladder shape, so that bonding wires are fully distributed in space, and the density of the bonding wires in unit area is improved;
5. certain electric insulating oil is sealed in the finished protective cover, so that the bare chip and the bonding wire can be prevented from being oxidized in the air;
6. the electrical insulating oil has good fluidity, and can avoid the contact connection between bonding wires possibly caused in the process of covering the bare chip by common glue;
7. if the bare chip is damaged in the testing process, the bare chip can be replaced by directly removing the protective cover and cleaning the electrical insulating oil, so that the reutilization of the testing PCB is ensured;
8. the invention has simple structure, low cost, easy processing and better feasibility of engineering application.
Drawings
For the purpose of clearly illustrating the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. The drawings in the following description are examples of the present invention, and other drawings may be derived from those drawings by those skilled in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a bare chip structure applied to testing according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a layout design of a main PCB board according to an embodiment of the present invention;
FIG. 3 is a schematic layout diagram of a secondary PCB according to an embodiment of the present invention;
FIG. 4 is a schematic layout diagram of a primary PCB and a secondary PCB stack according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a protective cover according to an embodiment of the present invention;
FIG. 6 is a schematic view of a syringe provided in accordance with an embodiment of the present invention;
FIG. 7 is a flow chart illustrating a method for fabricating a bare chip structure for testing according to an embodiment of the present invention;
FIG. 8 is a flow chart illustrating another method for fabricating a bare chip structure for testing according to an embodiment of the present invention;
fig. 9 a-9 i are schematic process flow diagrams of a bare chip structure for testing according to an embodiment of the invention.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, a structure for connecting a bare chip and a printed circuit board and a method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Examples merely typify possible variations, individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims.
The present invention will be described in further detail with reference to the accompanying drawings.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a bare chip structure applied to testing according to an embodiment of the present invention, wherein the structure 100 includes: the PCB comprises a main PCB 101, a secondary PCB 102, a bare chip 103, a first bonding pad 104, a first bonding wire 105, a second bonding pad 106, a second bonding wire 107, a gasket 110, a metal pin 111, a protective cover 112 and electrical insulating oil 114.
Wherein the pad 110 is adhered on the main PCB board 101 and the bare chip 103 is adhered on the pad 110; the first bonding PAD 104 surrounds the bare chip 103, is disposed on the main PCB 101, and is connected to a metal PAD of the bare chip 103 through the first bonding wire 105; the secondary PCB 102 is located at the periphery of the first pad 104, is adhered to the main PCB 101, and is electrically connected to the main PCB 101 through the metal pins 111; the second PAD 106 is disposed on the secondary PCB 102 and connected to the metal PAD of the bare chip 103 through the second bonding wire 107; the protective cover 112 is adhered to the main PCB 101, encloses the sub PCB 102, the bare chip 103, the first pad 104, the first bonding wire 105, the second pad 106, the second bonding wire 107, and the pad 110, and is filled with the electrically insulating oil 114.
The main PCB 101 is provided with a first through hole 108, the sub PCB 102 is correspondingly provided with a second through hole 109, and the metal pin 111 is inserted into the first through hole 108 and the second through hole 109 which are correspondingly arranged to realize the electrical connection between the main PCB 101 and the sub PCB 102.
The first pads 104 are staggered on the main PCB 101, and the second pads 106 are staggered on the sub PCB 102.
Wherein, two openings 113 are arranged on the upper surface of the protective cover 112; one of the openings 113 is used for injecting the electrically insulating oil 114 and the other opening 113 is used for venting and observing whether the electrically insulating oil 114 overflows to determine whether the protective cover 112 is filled with the electrically insulating oil 114.
Optionally, referring to fig. 2, fig. 3, fig. 4, fig. 5 and fig. 6 together, fig. 2 is a schematic layout diagram of a main PCB according to an embodiment of the present invention; FIG. 3 is a schematic layout diagram of a secondary PCB according to an embodiment of the present invention; FIG. 4 is a schematic layout diagram of a primary PCB and a secondary PCB stack according to an embodiment of the present invention; fig. 5 is a schematic structural diagram of a protective cover according to an embodiment of the present invention; FIG. 6 is a flow chart illustrating a method for fabricating a bare chip structure for testing according to an embodiment of the present invention; fig. 7 is a schematic view of a syringe according to an embodiment of the present invention.
Specifically, the main PCB 101 is provided with a staggered first pad 104, a first through hole 108 for connecting with the sub PCB 102, a first boundary line 201 for bonding the sub PCB 102, a second boundary line 202 for bonding the gasket 110, and a third boundary line 203 for bonding the protective cover 112, for carrying the sub PCB 102, the gasket 110, and the protective cover 112. The sub PCB 102 is provided with staggered second pads 106 and second through holes 109 for connection with the main PCB 101. The pads 110 are used to carry the bare chip 103. The metal pins 111 are used to realize reliable electrical and mechanical connection between the main PCB 101 and the sub PCB 102. The protective cover is bonded 112 to the main PCB 101 using an adhesive to provide oxygen-free enclosure protection for the bare chip 103. The injector 601 is used for injecting the electrically insulating oil 114 into the protective structure to isolate the bare chip 103, the first bonding wire 105, the second bonding wire 107 and air from contacting each other.
The main PCB 101 and the sub PCB 103 are preferably conventional hard PCB. The second boundary line 202 to which the pad 110 is bonded, the first boundary line 201 to which the sub PCB 101 is bonded, and the third boundary line 203 to which the protection cover 112 is bonded may be printed on the main PCB 101 in a screen printing manner to form a bonding region of the pad 110, a bonding region of the sub PCB 102, and a bonding region of the protection cover 112, respectively.
The spacer 110 is bonded to the main PCB 101 by a conductive adhesive to form a bump for supporting the bare chip 103, and has an area and a shape consistent with those of the bare chip and a height consistent with those of the sub PCB 102.
The bare chip 103 is bonded on the pad 110 on the main PCB board 101 using conductive paste.
The main PCB 101 and the sub PCB 102 are fabricated with staggered pads 104/106 for providing bonding points for bonding the bare chip 103, and are fabricated by a soft gold electroplating process, and nickel is electroplated as a bottom metal to improve the bonding strength of the bonding wire 105/107. Bonding wire 105/107 is preferably gold wire.
The main PCB 101 is provided with a first through hole 108 connected to the sub PCB 102.
The sub PCB 102 is provided with a second through hole 109 connected to the main PCB 101.
The first through holes 108 and the second through holes 109 correspond to each other in number and size and coincide in position.
The middle of the secondary PCB 102 is empty, and the area is slightly larger than the area surrounded by the first pad 104 of the primary PCB 101.
The metal pins 111 are made of brass and are gold-plated, and have a length slightly greater than the sum of the heights of the main PCB board 101 and the sub PCB board 102.
The protective cover 112 may be made of plastic material, hard rubber material, or metal material.
An adhesive paste is used for bonding between the protective cover 112 and the main PCB 101, and can provide a sufficient strength of adhesion, such as a one-component room temperature vulcanized silicone rubber or a glass paste.
The syringe 601 is used to inject the electrical insulating oil 114 into the protective cover 112 to isolate the bare chip 103, the first bonding wire 105, the second bonding wire 107 and air from contacting each other.
In this embodiment, the connection structure between the bare chip and the printed circuit board is in a high-low high-order ladder shape, and the spatial distribution of the bonding wires is used to obtain a larger bonding density per unit area. Certain electrical insulating oil is sealed in the bare chip test protection structure, and the bare chip test protection structure can provide protection for a test bare chip within the time of a chip packaging window period, so that the bare chip and the bonding wire are prevented from being oxidized in the air.
Example two
Referring to fig. 7, fig. 7 is a flowchart illustrating a method for manufacturing a bare chip structure for testing according to an embodiment of the invention. Wherein the manufacturing method comprises:
manufacturing a main PCB (printed circuit board) 101, and manufacturing a first bonding pad 104 on the surface of the main PCB 101;
bonding a gasket 110 at a designated position on the surface of the main PCB 101 and bonding a bare chip 103 on the surface of the gasket 110;
bonding two ends of a first bonding wire 105 on the metal PAD of the bare chip 103 and the first bonding PAD 104 by adopting a bonding process;
manufacturing a secondary PCB (printed Circuit Board) 102, and manufacturing a second bonding pad 106 on the surface of the secondary PCB 102;
bonding the sub PCB 102 to the main PCB 101;
bonding two ends of a second bonding wire 107 to the metal PAD of the bare chip 103 and the second bonding PAD 106 by using a bonding process, and connecting the main PCB 101 and the auxiliary PCB 102 by using a metal pin 111 to realize electrical connection;
bonding the protective cover 112 to the main PCB 101 such that the sub-PCB 102, the bare chip 103, the first pad 104, the first bonding wire 105, the second pad 106, the second bonding wire 107 and the pad 110 are collectively encapsulated in the protective cover 112;
injecting an electrical insulating oil 114 into the protective cover 112 through one opening 113 on the surface of the protective cover 112, and observing whether the electrical insulating oil 114 overflows from the other opening 113 on the surface of the protective cover 112 to determine whether the electrical insulating oil 114 is full of the protective cover 112, thereby forming the bare chip structure 100 applied to the test.
Wherein, before bonding the gasket 110 at the designated position on the surface of the main PCB 101, further comprising:
removing impurities on the main PCB 101, the sub PCB 102 and the protective cover 112 using a cleaning solution.
In addition, the main PCB 101 and the sub PCB 102 are connected by metal pins 111 to realize electrical connection, including:
a first through hole 108 is formed in the main PCB 101, a second through hole 109 is correspondingly formed in the sub PCB 102, and the metal pin 111 is inserted into the first through hole 108 and the second through hole 109 which are correspondingly formed, so as to electrically connect the main PCB 101 and the sub PCB 102.
Preferably, after the protective cover 112 is filled with the electrical insulating oil 114, the method further includes:
a layer of sealant is coated on the upper surface of the protective cover 112 to seal the opening 113 of the protective cover 112.
EXAMPLE III
Referring to fig. 8, fig. 8 is a flow chart illustrating a method for manufacturing a bare chip structure for testing according to another embodiment of the present invention. Wherein the manufacturing method comprises:
selecting a main PCB (printed Circuit Board) 101, and manufacturing a first boundary line 201 for bonding an auxiliary PCB 102, a second boundary line 202 for bonding a gasket 110 and a third boundary line 203 for bonding a protective cover 112 on the surface of the main PCB 101; first bonding pads 104 are manufactured on the surface of the main PCB 101 along the periphery of the second boundary line 202 in a staggered mode;
bonding the PAD 110 on the surface of the main PCB 101 along the second boundary line 202 and bonding the bare chip 103 on the surface of the PAD 110, and connecting the metal PAD of the bare chip 103 and the first PAD 104 by using a first bonding wire 105;
selecting a hollow auxiliary PCB (printed circuit board) 102, manufacturing second PADs 106 which are arranged in a staggered mode on the surface of the auxiliary PCB 102, fixing the auxiliary PCB 102 on the surface of the main PCB 101 along the first boundary line 201, and connecting the metal PAD of the bare chip 103 and the second PADs 106 by adopting a second bonding wire 107;
two openings 113 are formed on the surface of the protection cover 112 and are adhered to the main PCB 101 along the third boundary 203, and an electrical insulating oil 114 is injected into one of the openings 113 and is observed whether the electrical insulating oil 114 overflows from the other opening 113 to determine whether the protection cover 112 is full of the electrical insulating oil 114, thereby forming the bare chip structure 100 applied to the test.
Wherein the fixing of the sub PCB 102 to the surface of the main PCB 101 along the first boundary line 201 comprises:
the secondary PCB 102 is bonded to the primary PCB 101 and the secondary PCB 102 are connected by metal pins 111 to achieve electrical connection.
It should be emphasized that the steps in the above embodiments have no specific order relationship, and the operation can be implemented according to actual situations.
Example four
Referring to fig. 9a to 9i, fig. 9a to 9i are schematic process flow diagrams of a bare chip structure for testing according to an embodiment of the present invention, and the embodiment of the present invention provides a detailed description of a method for manufacturing the bare chip protection structure according to the present invention based on the above embodiments as follows:
the method comprises the following steps: as shown in fig. 2 and 3, the main PCB 101 includes a staggered first land 104, a first through hole 108, a first boundary line 201 to which the sub PCB 102 is bonded, a second boundary line 202 to which the pad 110 is bonded, and a third boundary line 203 to which the protective cover 112 is bonded. The sub PCB 102 includes a staggered second pad 106 and a second via 109. The main PCB 101 and the auxiliary PCB 102 are conventional hard PCBs, the bonding pads 104 and 106 are made by electroplating soft gold, the thickness is 3um for example, and nickel is electroplated as bottom metal to facilitate gold wire bonding; the first boundary line 201, the second boundary line 202, and the third boundary line 203 are formed on the main PCB 101 by screen printing, and are bonding regions of the sub PCB 102, the spacer 110, and the protective cover 112, respectively. The main PCB 101 and the sub PCB 102 without die 103 bonding are stacked as shown in fig. 4, and the first through holes 108 and the second through holes 109 are aligned in a one-to-one correspondence.
Step two: the protective cover is perforated, and perforations 113 are made diagonally in the protective cover 112 using a perforating tool, one of which serves as an electrically insulating oil injection hole and the other serves as an exhaust hole. As shown in fig. 5.
Step three: and cleaning the PCB and the protective cover, wherein anhydrous alcohol or acetone is used as a cleaning solution, and impurities on the main PCB 101, the auxiliary PCB 102 and the protective cover 112 are removed in an ultrasonic cleaning mode. The cleaned main PCB board 101 is shown in fig. 9 a.
Step four: and bonding the gasket, coating a proper conductive adhesive in the second boundary line 202 on the main PCB 101, bonding the gasket 110 in the second boundary line 202, and baking in a sintering oven at 150 ℃ for 2 hours to cure the conductive adhesive. The main PCB board 101 after bonding the pads 110 is shown in fig. 9 b.
And step five, chip bonding, namely coating proper conductive adhesive on the gasket 110 by using a manual dispenser, bonding the bare chip 103 on the gasket 110, and then baking for 2 hours in a sintering oven at the temperature of 150 ℃ so as to cure the conductive adhesive. The main PCB board 101 after bonding the bare chip 103 is shown in fig. 9 c.
And sixthly, bonding the bare chip and the main PCB, wherein the bonding of the bare chip adopts an ultrasonic hot-press welding process, a manual bonding machine is adopted, the first bonding wire 105 adopts a gold wire with the diameter of 25 mu m, the main PCB 101 with the bonded chip is placed on a pressure welding base and fixed, preheating is carried out for 2-3 minutes, an operating handle of the manual bonding machine is moved to complete the bonding of the metal PAD of the bare chip 103 and the first bonding PAD 104 on the main PCB 101, and the bonded main PCB 101 is shown in fig. 9 d.
And seventhly, bonding the auxiliary PCB, smearing bonding glue, such as silicon rubber or glass glue, along the first boundary line 201 on the main PCB 101, bonding the auxiliary PCB 102 on the main PCB 101, and ensuring that the first through holes 108 and the second through holes 109 are in one-to-one correspondence and overlapped in position. The main PCB 101 after bonding the sub PCB 102 is shown in fig. 9 e.
And step eight, bonding the bare chip and the auxiliary PCB, selecting an ultrasonic hot-press welding process, selecting a manual bonding machine, selecting a gold wire with the diameter of 25 microns as a second bonding wire 107, placing and fixing the main PCB 101 bonded with the auxiliary PCB 102 on a pressure welding base, preheating for 2-3 minutes, moving an operating handle of the manual bonding machine to complete bonding of the metal PAD of the bare chip 103 and the second bonding PAD 106 on the auxiliary PCB 102, wherein the bonded main PCB 101 is shown in fig. 9 f.
And ninthly, welding and fixing, namely using a metal pin 111 which is made of brass material and plated with gold, inserting the metal pin into the main PCB connecting through hole 108 and the auxiliary PCB connecting through hole 109, wherein the length of the metal pin 111 is slightly larger than the sum of the heights of the main PCB 101 and the auxiliary PCB 102, welding the metal pin 111 with the main PCB 101, the metal pin 111 with the auxiliary PCB 102 by using an electric welding tool to form a welding point 901, and ensuring that the main PCB 101 and the auxiliary PCB 102 are reliably electrically and mechanically connected, wherein the main PCB 101 after welding and fixing is shown in fig. 9 g.
Tentatively, adhering the protective cover, smearing adhesive glue, such as silicon rubber or glass glue, along the third boundary line 203 on the PCB 101, adhering the protective cover 112 on the PCB 101, standing the PCB 101 at room temperature until the adhesive glue is completely cured, and adhering the PCB 101 with the protective cover 112 as shown in fig. 9 h.
Step eleven, injecting the electrical insulating oil, namely injecting the electrical insulating oil into the protective cover by using the injector 601 through one of the openings 113 in the protective cover 112, and taking the other opening as an exhaust hole until the electrical insulating oil overflows from the exhaust hole, and stopping injecting the electrical insulating oil.
Step twelve, opening sealing, a layer of sealant 902, such as silicone rubber or glass cement, is applied on the protective cover 112 to seal the opening 113 on the protective cover 102.
And step thirteen, curing the sealant, and standing the PCB 101 at room temperature until the sealant is completely cured. And finally forming a connecting and protecting structure of the bare chip and the printed circuit board. The PCB board 101 after the curing of the sealant is shown in fig. 9 i.
According to the connection and protection structure of the bare chip and the printed circuit board, the secondary PCB is introduced, the completed connection structure is in a high-low high-order ladder shape, bonding wires are fully distributed in space, and the density of the bonding wires in unit area is improved; the introduction of the gasket enables the conductive adhesive overflowing during the bonding of the bare chip to flow downwards under the action of gravity, so that the pollution to the metal PAD of the bare chip can be effectively avoided; the staggered binding pads reduce the touch connection between adjacent bonding wires; the gasket is fixed on the main PCB in a bonding mode, so that the complex steps and cost of processing a boss by adopting a direct printed board are avoided; certain electrical insulating oil is sealed in the protective cover, so that the bare chip and the bonding wire can be prevented from being oxidized in the air; if the bare chip is damaged in the testing process, the bare chip can be replaced by directly removing the protective cover and cleaning the electrical insulating oil, so that the reutilization of the testing PCB is ensured; simple structure, low cost, easy processing and higher practical value.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (2)
1. A bare chip structure (100) for testing, comprising: the PCB comprises a main PCB (101), a secondary PCB (102), a bare chip (103), a first bonding pad (104), a first bonding wire (105), a second bonding pad (106), a second bonding wire (107), a gasket (110), a metal pin header (111), a protective cover (112) and electrical insulating oil (114); wherein,
the pad (110) is bonded to the main PCB (101) and the bare chip (103) is bonded to the pad (110); the first bonding PADs (104) are staggered and surrounded on the periphery of the bare chip (103), arranged on the main PCB (101) and connected with a metal PAD of the bare chip (103) through the first bonding wires (105); the main PCB (101) is provided with a first through hole (108), the auxiliary PCB (102) is correspondingly provided with a second through hole (109), and the metal pin (111) is inserted into the first through hole (108) and the second through hole (109) which are correspondingly arranged so as to realize the electrical connection between the main PCB (101) and the auxiliary PCB (102); the auxiliary PCB (102) is positioned at the periphery of the first bonding pad (104) and is bonded on the main PCB (101) and is electrically connected with the main PCB (101) through the metal pins (111); the second PADs (106) are arranged on the secondary PCB board (102) in a staggered mode and are connected with the metal PAD of the bare chip (103) through the second bonding wires (107); the protective cover (112) is adhered to the main PCB (101) and encapsulates the sub PCB (102), the bare chip (103), the first pad (104), the first bonding wire (105), the second pad (106), the second bonding wire (107) and the gasket (110) therein, and the electrically insulating oil (114) is injected therein; the upper surface of the protective cover (112) is provided with two open holes (113); one of the openings (113) is used for injecting the electrically insulating oil (114) and the other opening (113) is used for venting and observing whether the electrically insulating oil (114) overflows or not to determine whether the protective cover (112) is full of the electrically insulating oil (114).
2. A method of fabricating a bare chip structure (100) for testing, comprising:
manufacturing a main PCB (101), and manufacturing a first bonding pad (104) on the surface of the main PCB (101);
bonding a gasket (110) at a designated position on the surface of the main PCB (101) and bonding a bare chip (103) on the surface of the gasket (110);
bonding two ends of a first bonding wire (105) on the metal PAD of the bare chip (103) and the first bonding PAD (104) by adopting a bonding process;
manufacturing a secondary PCB (102), and manufacturing a second bonding pad (106) on the surface of the secondary PCB (102);
bonding the secondary PCB (102) to the primary PCB (101);
bonding two ends of a second bonding wire (107) on a metal PAD of the bare chip (103) and the second bonding PAD (106) by adopting a bonding process, connecting the main PCB (101) and the auxiliary PCB (102) by adopting a metal pin (111) to realize electrical connection, manufacturing a first through hole (108) on the main PCB (101), correspondingly arranging a second through hole (109) on the auxiliary PCB (102), and inserting the metal pin (111) into the correspondingly arranged first through hole (108) and the second through hole (109) to realize the electrical connection of the main PCB (101) and the auxiliary PCB (102);
bonding a protective cover (112) to the main PCB (101) such that the sub PCB (102), the bare chip (103), the first pad (104), the first bonding wire (105), the second pad (106), the second bonding wire (107), and the pad (110) are collectively encapsulated in the protective cover (112);
inject electrical insulation oil (114) through an trompil (113) on safety cover (112) surface to inside safety cover (112), and observe whether another trompil (113) on safety cover (112) surface has electrical insulation oil (114) overflows with the definite whether electrical insulation oil (114) has been filled safety cover (112) upper surface daub one deck sealant in order to be right trompil (113) on safety cover (112) seal, thereby form be applied to the bare chip structure (100) of test.
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| CN106856177B (en) * | 2016-11-28 | 2019-07-02 | 嘉兴鹏武电子科技有限公司 | Naked core chip architecture and its manufacturing method applied to test |
| US10593852B2 (en) * | 2018-06-20 | 2020-03-17 | Innolux Corporation | Display device having a plurality of main pads, a plurality of redundant pads, and a light-emitting device |
| CN108882523A (en) * | 2018-06-27 | 2018-11-23 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN109560026A (en) * | 2018-12-03 | 2019-04-02 | 北京遥感设备研究所 | A kind of vacuum electronic component mechanical environment adaptability device |
| CN110376506B (en) * | 2019-07-17 | 2022-01-14 | 上海华虹宏力半导体制造有限公司 | Testing method of fragment chip |
| CN112185926B (en) * | 2020-09-10 | 2023-04-28 | 上海华虹宏力半导体制造有限公司 | Chip bonding pad leading-out device and method |
| CN112798928A (en) * | 2020-12-29 | 2021-05-14 | 中国电子科技集团公司第十四研究所 | Chip testing method based on ceramic slide |
| CN114675162B (en) * | 2022-03-24 | 2022-11-15 | 北京涵鑫盛科技有限公司 | PCB for testing and packaging SSD main control chip |
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