CN106783636A - The preparation method of integrated circuit Plastic Package - Google Patents
The preparation method of integrated circuit Plastic Package Download PDFInfo
- Publication number
- CN106783636A CN106783636A CN201611133300.2A CN201611133300A CN106783636A CN 106783636 A CN106783636 A CN 106783636A CN 201611133300 A CN201611133300 A CN 201611133300A CN 106783636 A CN106783636 A CN 106783636A
- Authority
- CN
- China
- Prior art keywords
- chip
- preparation
- integrated circuit
- molding
- encapsulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004033 plastic Substances 0.000 title claims abstract description 15
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000000465 moulding Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 239000003822 epoxy resin Substances 0.000 claims abstract description 10
- 239000012778 molding material Substances 0.000 claims abstract description 10
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 10
- 230000011218 segmentation Effects 0.000 claims abstract description 4
- 239000011265 semifinished product Substances 0.000 claims abstract description 4
- 238000005516 engineering process Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 210000003205 muscle Anatomy 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 9
- 238000012856 packing Methods 0.000 abstract description 3
- 238000003754 machining Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to a kind of preparation method of integrated circuit Plastic Package, it is characterized in that, comprise the following steps：（1）Pre-molding substrate is made using pre-molding material in the lower surface of lead frame；（2）In pre-molding upper surface of base plate assembling chip；（3）Chip after assembling is encapsulated using epoxy resin, EMC encapsulated layers are obtained；（4）Method by being machined, removes the unnecessary epoxy resin in nead frame top；（5）Method by being machined, removes the unnecessary pre-molding material in nead frame lower section；（6）By step（5）The semi-finished product segmentation for obtaining is shaped to independent packaging body.Present invention improves over encapsulating mold and the present situation of different size packaging body " one-to-one ", the method for packing of machining is encapsulated and used by pre-molding substrate, the encapsulation of different apparent sizes can be completed by a set of encapsulating mold.
Description
Technical field
The present invention relates to a kind of preparation method of integrated circuit Plastic Package, belong to ic manufacturing technology field.
Background technology
In the prior art, QFP（Quad Flat Package, small-sized square planar package）、SOP（Small Out-Line
Package, small outline packages）Plastic Package is encapsulated by injection mould, and the encapsulation of different plastic-sealed body sizes is needed to use
Different encapsulating molds, for small lot batch manufacture or new size research and development of products, investing corresponding mould needs great amount of cost, makes
The about exploitation of new encapsulation.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of preparation of integrated circuit Plastic Package
Method, improves the present situation of encapsulating mold and different size packaging body " one-to-one ", and machine is encapsulated and used by pre-molding substrate
The method for packing of tool processing, can complete the encapsulation of different apparent sizes by a set of encapsulating mold.
According to the present invention provide technical scheme, a kind of preparation method of integrated circuit Plastic Package, it is characterized in that, including
Following steps：
（1）Pre-molding substrate is made using pre-molding material in the lower surface of lead frame；
（2）In pre-molding upper surface of base plate assembling chip；
（3）Chip after assembling is encapsulated using epoxy resin, EMC encapsulated layers are obtained；
（4）Method by being machined, removes the unnecessary epoxy resin in nead frame top；
（5）Method by being machined, removes the unnecessary pre-molding material in nead frame lower section；
（6）By step（5）The semi-finished product segmentation for obtaining is shaped to independent packaging body.
Further, the pre-molding upper surface of base plate passes through chip load, bonding technology assembling chip.
Further, the chip after the assembling is using compression mould or injection mold technique encapsulating EMC encapsulated layers.
Further, the step（5）The packaging body for obtaining is obtained solely through the muscle that hits, deflashing, plating, printing, shaping
Vertical packaging body.
Compared with the prior art the present invention has advantages below：The present invention is encapsulated by pre-molding substrate and uses machinery to add
The encapsulation preparation method of work, compared with the method for packing of existing QFP, SOP type, the present invention can be completed by a set of encapsulating mold
The encapsulation of different apparent sizes, has saved die sinking cost, improves the compatibility of mould.
Brief description of the drawings
Fig. 1~Fig. 6 is the flow chart of the preparation method of integrated circuit Plastic Package of the present invention.Wherein：
Fig. 1 is the schematic diagram of the pre-molding substrate.
Fig. 2 is the schematic diagram in pre-molding substrate over-assemble chip.
Fig. 3 is the schematic diagram that chip is encapsulated using epoxy resin.
Fig. 4 is the schematic diagram of EMC encapsulated layer redundances.
Fig. 5 is the schematic diagram of the unnecessary EMC encapsulated layers of removal.
Fig. 6 is the schematic diagram of the unnecessary pre-molding material of removal.
Label in figure：Lead frame 1, pre-molding material 2, EMC encapsulated layers 3, chip 4.
Specific embodiment
With reference to specific accompanying drawing, the invention will be further described.
The preparation method of integrated circuit Plastic Package of the present invention, comprises the following steps：
（1）As shown in figure 1, the lower surface in lead frame 1 is made pre-molding substrate using pre-molding material 2；
（2）As shown in Fig. 2 using the chip load of standard, bonding technology in pre-molding upper surface of base plate assembling chip 4；
（3）As shown in figure 3, using compression mould or injection mold technique, the chip 4 after assembling is encapsulated using epoxy resin,
Obtain EMC encapsulated layers 3；
（4）As shown in figure 4, shape, the size requirement according to product, to step（3）The packaging body of EMC encapsulatings is completed, is calculated
To the position of unnecessary EMC encapsulated layers 3；As in Figure 2-4, the part in EMC encapsulated layers 3 beyond dotted line is unnecessary part；
（5）As shown in figure 5, the method by being machined, removes the unnecessary epoxy resin in the top of nead frame 1；
（6）As shown in fig. 6, shape, the size requirement according to product, the method by being machined, remove the lower section of nead frame 1
Unnecessary pre-molding material 2；
（7）By the conventional muscle that hits, deflashing, plating, printing, forming method by step（6）The semi-finished product segmentation shaping for obtaining
It is single complete packaging body.
The preparation method of integrated circuit Plastic Package of the present invention, uses pre- mould using encapsulated plastic on the lead frames
The method of modeling, forms package substrate of the molding substrate as integrated circuit, after load, bonding are completed on the substrate, using EMC
（Epoxy resin）Chip and bonding wire are encapsulated by compressing mould or injection mold technique, then by the way of machining
The encapsulating material of pin upper and lower is removed, is then hited muscle, deflashing, plating, printing, molding procedure by standard, form one
Individual complete encapsulation.The preparation method can encapsulate various sizes of the type encapsulation in one set of die, save different chis
The die sinking cost respectively of very little the type encapsulation, improves the compatibility of mould.
Claims (4)
1. a kind of preparation method of integrated circuit Plastic Package, it is characterized in that, comprise the following steps：
（1）In lead frame（1）Lower surface use pre-molding material（2）It is made pre-molding substrate；
（2）In pre-molding upper surface of base plate assembling chip（4）；
（3）By the chip after assembling（4）Encapsulated using epoxy resin, obtained EMC encapsulated layers（3）；
（4）Method by being machined, removes nead frame（1）The unnecessary epoxy resin in top；
（5）Method by being machined, removes nead frame（1）The unnecessary pre-molding material in lower section（2）；
（6）By step（5）The semi-finished product segmentation for obtaining is shaped to independent packaging body.
2. the preparation method of integrated circuit Plastic Package as claimed in claim 1, it is characterized in that：The pre-molding substrate upper table
Face passes through chip load, bonding technology assembling chip（4）.
3. the preparation method of integrated circuit Plastic Package as claimed in claim 1, it is characterized in that：Chip after the assembling
（4）Using compression mould or injection mold technique encapsulating EMC encapsulated layers（3）.
4. the preparation method of integrated circuit Plastic Package as claimed in claim 1, it is characterized in that：The step（5）Obtain
Packaging body obtains independent packaging body through the muscle that hits, deflashing, plating, printing, shaping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611133300.2A CN106783636A (en) | 2016-12-10 | 2016-12-10 | The preparation method of integrated circuit Plastic Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611133300.2A CN106783636A (en) | 2016-12-10 | 2016-12-10 | The preparation method of integrated circuit Plastic Package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106783636A true CN106783636A (en) | 2017-05-31 |
Family
ID=58875098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611133300.2A Pending CN106783636A (en) | 2016-12-10 | 2016-12-10 | The preparation method of integrated circuit Plastic Package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106783636A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878299A (en) * | 2018-02-23 | 2018-11-23 | 无锡中微高科电子有限公司 | The preparation method of frame clsss integrated circuit Plastic Package is carried out by laser |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878561A (en) * | 1994-08-31 | 1996-03-22 | Sony Corp | Manufacturing method of semiconductor device |
| JPH08167685A (en) * | 1994-12-15 | 1996-06-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| TW411593B (en) * | 1999-06-22 | 2000-11-11 | Vanguard Int Semiconduct Corp | Plastic carrier mold with magnetic inserting article |
| US20070170554A1 (en) * | 2006-01-23 | 2007-07-26 | Stats Chippac Ltd. | Integrated circuit package system with multiple molding |
| CN104229727A (en) * | 2013-06-20 | 2014-12-24 | 英飞凌科技股份有限公司 | Pre-mold for a magnet semiconductor assembly group and method of producing the same |
-
2016
- 2016-12-10 CN CN201611133300.2A patent/CN106783636A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878561A (en) * | 1994-08-31 | 1996-03-22 | Sony Corp | Manufacturing method of semiconductor device |
| JPH08167685A (en) * | 1994-12-15 | 1996-06-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| TW411593B (en) * | 1999-06-22 | 2000-11-11 | Vanguard Int Semiconduct Corp | Plastic carrier mold with magnetic inserting article |
| US20070170554A1 (en) * | 2006-01-23 | 2007-07-26 | Stats Chippac Ltd. | Integrated circuit package system with multiple molding |
| CN104229727A (en) * | 2013-06-20 | 2014-12-24 | 英飞凌科技股份有限公司 | Pre-mold for a magnet semiconductor assembly group and method of producing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878299A (en) * | 2018-02-23 | 2018-11-23 | 无锡中微高科电子有限公司 | The preparation method of frame clsss integrated circuit Plastic Package is carried out by laser |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170531 |
|
| RJ01 | Rejection of invention patent application after publication |