CN106776414A - Data transmission device and method, ink-jet print system - Google Patents
Data transmission device and method, ink-jet print system Download PDFInfo
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- CN106776414A CN106776414A CN201710015292.XA CN201710015292A CN106776414A CN 106776414 A CN106776414 A CN 106776414A CN 201710015292 A CN201710015292 A CN 201710015292A CN 106776414 A CN106776414 A CN 106776414A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/005—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
- B41J2/01—Ink jet
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/12—Digital output to print unit, e.g. line printer, chain printer
- G06F3/1201—Dedicated interfaces to print systems
- G06F3/1202—Dedicated interfaces to print systems specifically adapted to achieve a particular effect
- G06F3/1203—Improving or facilitating administration, e.g. print management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/12—Digital output to print unit, e.g. line printer, chain printer
- G06F3/1201—Dedicated interfaces to print systems
- G06F3/1223—Dedicated interfaces to print systems specifically adapted to use a particular technique
- G06F3/1236—Connection management
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Abstract
The present invention relates to a kind of data transmission device and method, ink-jet print system, methods described includes：Being received by the first fpga chip is needed the data that are transmitted and exports corresponding Transistor-Transistor Logic level signal；Exported after difference signal generator receives the TTL signal of the first fpga chip output and is converted into high-speed differential signal；The high-speed differential signal of the difference signal generator output is received by differential signal demodulator and Transistor-Transistor Logic level signal is converted into；The Transistor-Transistor Logic level signal that the differential signal adjuster is changed is gathered by the second fpga chip.The present invention can realize the one-way data transfer speed of more than 10Mbps, and the different types of data of transmission can be distinguished in same data channel.
Description
【Technical field】
The present invention relates to field of data transmission, more particularly to data transmission device and method, ink-jet print system.
【Background technology】
With FPGA (Field-Programmable Gate Array：Field programmable gate array) chip functions and work(
That consumes continues to optimize so that it is more and more extensive in the application of field of electronic design.Numerous sensor data acquisitions and communication
Interface is required for using fpga chip come structure composed, realizes function.In the middle of star-network or mesh network topologies structure, have
When each node between fpga chip there is the demand of direct data communication.Such as, in some distributed apparatus or more piece
, it is necessary to use polylith circuit board to realize function in point device, in this case, between the fpga chip of each circuit board
There is the demand of direct communication；And the communication mode between FPGA and FPGA, typically all use existing communication protocol standard, example
Such as RS232 asynchronous serial ports, I2C interface protocols etc.；But the program is disadvantageous in that, its limitation for being limited to existing protocol,
Secondly underaction, cannot also distinguish the different types of data of transmission in same data channel.
【The content of the invention】
The present invention provides a kind of data transmission device and method, ink-jet print system, it is proposed that one kind is by FPGA to FPGA
High-speed synchronous data transmission means, the program can realize the one-way data transfer speed of more than 10Mbps, and can be same
Distinguished on one data passage and send different types of data.
A kind of first aspect according to embodiments of the present invention, there is provided data transmission device, including output circuit and reception electricity
Road；The output circuit includes：
First fpga chip, is arranged on the output circuit, and defeated after the data being transmitted for reception needs
Go out corresponding Transistor-Transistor Logic level signal；
Difference signal generator, is arranged on the output circuit, and is connected to first fpga chip, for receiving
The TTL signal of the first fpga chip output is simultaneously converted into output after high-speed differential signal；
The receiving circuit includes：
Differential signal demodulator, is arranged in the receiving circuit, and is connected to the difference signal generator, for connecing
Receive the high-speed differential signal of the difference signal generator output and be converted into Transistor-Transistor Logic level signal；
Second fpga chip, is arranged in the receiving circuit, and is connected to the differential signal demodulator, for gathering
The Transistor-Transistor Logic level signal of the differential signal adjuster conversion.
In certain embodiments, first fpga chip includes：
Data match module, for being matched with speed according to classification to the data that are transmitted of needs after output；
Data is activation matching module, is connected to the data match module, for defeated in the reception data match module
Its step-by-step is matched and exported after the data for going out；
Data outputting module, is connected to the data is activation matching module and the data match module, for receiving
After the data is activation matching module and the data of data match module output, Transistor-Transistor Logic level signal is exported；
Second fpga chip includes：
Data reception module, is connected to the data outputting module, the TTL for receiving the data outputting module output
Level signal；
Data resolution module, is connected to the data reception module, for the TTL electricity received to the data reception module
Ordinary mail number exports data corresponding with its state after being parsed.
In certain embodiments, first fpga chip also includes：
Rate selection module, is connected to the data match module, the data is activation matching module and the data defeated
Go out module, for carrying out speed selection.
In certain embodiments, the Transistor-Transistor Logic level signal includes DSYNC signals, DSCLK signals, cmd signal and DATA letter
Number；
The data outputting module is included for exporting the DSYNC output ends of DSYNC signals, for exporting DSCLK signals
DSCLK output ends, the CMD output ends for exporting cmd signal, the DATA output ends for exporting DATA signal；
The data reception module is included for receiving the DSYNC receiving terminals of DSYNC signals, for receiving DSCLK signals
DSCLK receiving terminals, the CMD receiving terminals for receiving cmd signal, the DATA receiving terminals for receiving DATA signal.
In certain embodiments, the data is activation matching module includes：
Order sends matching unit, is connected to the data match module and the data outputting module, for receiving
Its step-by-step is matched and exported after the cmd signal of the data match module output；
Data is activation matching unit, is connected to the data match module and the data outputting module, for receiving
Its step-by-step is matched and exported after the DATA signal of the data match module output；
The data reception module includes：
Order receiving unit, is connected to the data resolution module and the differential signal adjuster, described for receiving
The cmd signal of differential signal adjuster conversion simultaneously outputs this to the data resolution module；
Data receipt unit, is connected to the data resolution module and the differential signal adjuster, described for receiving
The DATA signal of differential signal adjuster conversion simultaneously outputs this to the data resolution module.
In certain embodiments, the order sends matching unit and/or the quantity of the data is activation matching unit is
It is multiple；
The quantity of the order receiving unit and/or the data receipt unit is multiple.
In certain embodiments, the data match module includes：
Data category switch unit, is connected to the data is activation matching module, for switching the number for needing to be transmitted
According to transmission classification after output it.
Second aspect according to embodiments of the present invention, also provides a kind of ink-jet print system, including described data transfer
Device.
The third aspect according to embodiments of the present invention, also provides a kind of data transmission method, including：
Being received by the first fpga chip is needed the data that are transmitted and exports corresponding Transistor-Transistor Logic level signal；
The TTL signal of the first fpga chip output is received by difference signal generator and speed difference high is converted into
Exported after sub-signal；
The high-speed differential signal of the difference signal generator output is received by differential signal demodulator and is converted
It is Transistor-Transistor Logic level signal；
The Transistor-Transistor Logic level signal that the differential signal adjuster is changed is gathered by the second fpga chip.
In certain embodiments, first fpga chip includes data match module, data is activation matching module sum
According to output module；Second fpga chip includes data reception module and data resolution module；
The data being transmitted by the first fpga chip reception needs simultaneously export corresponding Transistor-Transistor Logic level letter
Number, including：
It is defeated after being matched with speed according to classification to the data that needs are transmitted by the data match module
Go out；
Received its step-by-step after the data that the data match module is exported by the data is activation matching module
With and export；
Exported by the data outputting module reception data is activation matching module and the data match module
After data, Transistor-Transistor Logic level signal is exported；
It is described that the Transistor-Transistor Logic level signal that the differential signal adjuster is changed is gathered by the second fpga chip, including：
The Transistor-Transistor Logic level signal that the data outputting module is exported is received by the data reception module；
After being parsed to the Transistor-Transistor Logic level signal that the data reception module is received by the data resolution module,
Output data corresponding with the Transistor-Transistor Logic level signal.
Technical scheme provided in an embodiment of the present invention can produce following beneficial effect：Being received by the first fpga chip is needed
The data that are transmitted simultaneously export corresponding Transistor-Transistor Logic level signal；First FPGA is received by difference signal generator
The TTL signal of chip output is simultaneously converted into output after high-speed differential signal；The difference is received by differential signal demodulator
The high-speed differential signal of sub-signal generator output is simultaneously converted into Transistor-Transistor Logic level signal；Institute is gathered by the second fpga chip
State the Transistor-Transistor Logic level signal of differential signal adjuster conversion.The program can realize the one-way data transfer speed of more than 10Mbps,
And the different types of data of transmission can be distinguished in same data channel.
Other features and advantages of the present invention will be illustrated in the following description, also, the partly change from specification
Obtain it is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by the explanations write
Specifically noted structure is realized and obtained in book, claims and accompanying drawing.
Below by drawings and Examples, technical scheme is described in further detail.
【Brief description of the drawings】
Fig. 1 is a kind of block diagram of data transmission device of the present invention according to an exemplary embodiment.
Fig. 2 is data transfer timing diagram of the present invention according to an exemplary embodiment.
Fig. 3 is a kind of frame of the first fpga chip of data transmission device of the present invention according to an exemplary embodiment
Figure.
Fig. 4 is the first fpga chip of another data transmission device of the present invention according to an exemplary embodiment
Block diagram.
Fig. 5 is a kind of frame of the second fpga chip of data transmission device of the present invention according to an exemplary embodiment
Figure.
Fig. 6 is the second fpga chip of another data transmission device of the present invention according to an exemplary embodiment
Block diagram.
Fig. 7 is the first fpga chip of another data transmission device of the present invention according to an exemplary embodiment
Block diagram.
Fig. 8 is a kind of data is activation matching module of data transmission device of the present invention according to an exemplary embodiment
Block diagram.
Fig. 9 is a kind of frame of the data reception module of data transmission device of the present invention according to an exemplary embodiment
Figure.
Figure 10 is a kind of data match module of data transmission device of the present invention according to an exemplary embodiment
Block diagram.
Figure 11 is a kind of flow chart of data transmission method of the present invention according to an exemplary embodiment.
【Specific embodiment】
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the present invention, not
For limiting the present invention.
The embodiment of the present disclosure provides a kind of data transmission device and method, ink-jet print system, is used to realize 10Mbps
One-way data transfer speed above, and the different types of data of transmission can be distinguished in same data channel.
As shown in figure 1, Fig. 1 is a kind of block diagram of data transmission device of the present invention according to an exemplary embodiment.
The data transmission device includes output circuit A and receiving circuit B；The output circuit A includes：
First fpga chip 1, is arranged on the output circuit A, and after the data being transmitted for reception needs
The corresponding Transistor-Transistor Logic level signal of output.
Difference signal generator 2, is arranged on the output circuit A, and is connected to first fpga chip 1, is used for
Receive the TTL signal of the output of the first fpga chip 1 and exported after being converted into high-speed differential signal；That is, the difference
The effect of sub-signal generator 2 be the first fpga chip 1 is exported TTL signal conversion for ease of long-distance transmissions speed difference high
Sub-signal.
The receiving circuit B includes：
Differential signal demodulator 3, is arranged on the receiving circuit B, and is connected to the difference signal generator 2, uses
In the high-speed differential signal for receiving the difference signal generator 2 output and it is converted into Transistor-Transistor Logic level signal；That is, described
Differential signal demodulator 3 is converted into TTL signal as corresponding signal demodulating apparatus, the high-speed differential signal that will be received, with
Just the second fpga chip 4 is acquired.
Second fpga chip 4, is arranged on the receiving circuit B, and is connected to the differential signal demodulator 3, is used for
Gather the Transistor-Transistor Logic level signal of the differential signal adjuster conversion.
In certain embodiments, as shown in Figures 3 and 4, Fig. 3 is the one kind of the present invention according to an exemplary embodiment
The block diagram of the first fpga chip of data transmission device.Fig. 4 is another number of the present invention according to an exemplary embodiment
According to the block diagram of the first fpga chip of transmitting device.First fpga chip 1 includes：
Data match module 11, for being matched with speed according to classification to the data that are transmitted of needs after it is defeated
Go out；In the embodiment shown in fig. 4, the data match module 11 is FRAM_CTRL, and FRAM_CTRL is responsible to needing to pass
Transmission of data classification and speed etc. are matched.
Data is activation matching module 12, is connected to the data match module 11, for receiving the Data Matching mould
Its step-by-step is matched and exported after the data of the output of block 11；In the embodiment shown in fig. 4, the data is activation matching module
12 is CMD_FRAM and DATA_FRAM, and in the present embodiment, CMD_FRAM and DATA_FRAM are actually identical
Two data is activation matching modules, data are sent for step-by-step matching；In the life and death shown in Fig. 4 is returned, ADDR and STATE believes
Number for generating cmd signal.It is intelligible, the arbitrarily extensible port number for sending data of framework of first fpga chip 1
(data is activation matching module 12), such as in the case where other modules do not do big change integrally, can increase a DATA1_
FRAM, many DATA1 signals of output.It is noted that often increase data channel all the way increases by one group of multiple twin it is necessary to corresponding
Line.
Data outputting module 13, is connected to the data is activation matching module 12 and the data match module 11, is used for
After the data for receiving the data is activation matching module 12 and the output of the data match module 11, output Transistor-Transistor Logic level letter
Number；In the embodiment shown in fig. 4, the data outputting module 13 be DATA_OUT, for export cmd signal, DATA signal,
DSYNC signals and DCLK signal lamp Transistor-Transistor Logic level signal.
As shown in Figures 5 and 6, Fig. 5 is a kind of data transmission device of the present invention according to an exemplary embodiment
The block diagram of the second fpga chip.Fig. 6 is the of another data transmission device of the present invention according to an exemplary embodiment
The block diagram of two fpga chips.Second fpga chip 4 includes：
Data reception module 41, is connected to the data outputting module 13, defeated for receiving the data outputting module 13
The Transistor-Transistor Logic level signal for going out；In the embodiment shown in fig. 6, the data reception module 41 includes CMD_RECIVE, DATA_
RECIVE, and both are two data reception modules of identical, the Transistor-Transistor Logic level signal for simply receiving in logic is divided into cmd signal
With two classifications of DATA signal.It is intelligible, it is corresponding with first fpga chip 1 (transmitting terminal), if a FPGA
Chip 1 increases a passage (data is activation matching module 12) for transmission data, then the second fpga chip 4 needs to increase by a number
According to receiving channel (data reception module 41).
Data resolution module 42, is connected to the data reception module 41, for being received to the data reception module 41
Transistor-Transistor Logic level signal parsed after corresponding with its state data of output.In the embodiment shown in fig. 6, the data
Parsing module 42 is DATE_DEV, and DATE_DEV is responsible for cmd signal to be parsed into COMMAND and ADDR simultaneously corresponding states
DATA data outputs；Wherein, cmd signal is divided into three parts according to functional structure：Order (COMMAND), address (ADDR) and
The type (STATE) of this transmission data.
In certain embodiments, as shown in Fig. 4 and Fig. 7, Fig. 7 is that the present invention is another according to an exemplary embodiment
Plant the block diagram of the first fpga chip of data transmission device.First fpga chip 1 also includes：
Rate selection module 14, is connected to the data match module 11, the data is activation matching module 12 and described
Data outputting module 13, for carrying out speed selection, so as to realize the transmission characteristic of different pieces of information different rates.Shown in Fig. 4
Embodiment in, the rate selection module 14 is SPEED_SELECT, and it is responsible for the generation of transmission rate DCLK.
In certain embodiments, as shown in Figures 1 and 2, Fig. 2 is data of the present invention according to an exemplary embodiment
Transmission time sequence figure.In the present embodiment, this agreement regulation carried out data transmission using 4 signals (in this 4 divisions of signal and
The data transfer for defining any length under framework is within the scope of the present invention), namely the Transistor-Transistor Logic level signal includes
Following four signal：
DSYNC signals：The DSYNC marked in synchronizing signal, namely Fig. 1 and Fig. 2, DSYNC signals are in an idle state
Low level, is high level in the middle of data transmission procedure.
DSCLK signals：The DSCLK marked in clock signal, namely Fig. 1 and Fig. 2, DSCLK signals are in an idle state
Low level, starting of oscillation after DSYNC signals are uprised, dutycycle is 50%, it is ensured that contain 32 trailing edges in the middle of a transmitting procedure；
Intelligible, its clock rate can carry out self-defined according to the difference for sending data.
DATA signal：The DATA signal marked in data-signal, namely Fig. 1 and Fig. 2, DATA signal is on DSCLK signals
Rise along when switch data, keep data stabilization during DSCLK signal trailing edges.Load is useful data, and single transmission is 32bit.
Cmd signal：The CMD marked in order and status signal, namely Fig. 1 and Fig. 2, cmd signal rises in DSCLK signals
Along when switch data, keep data stabilization in DSCLK signal trailing edges.Wherein, as shown in table 1, cmd signal is according to function knot
Structure is divided into three parts：The type (STATE) of order (COMMAND), address (ADDR) and this transmission data.
The cmd signal structure of table 1
Wherein：
COMMAND：The mandatory signal that data sending terminal sends to data receiver, takes 2 bytes.
ADDR：The plate level address of data sending terminal, accounts for 1 byte.
STATE：The type of this frame data, accounts for 1 byte.
It is intelligible, as shown in figure 1, the data outputting module 13 includes the DSYNC outputs for exporting DSYNC signals
End (outgoing position of DSYNC signals in Fig. 1), DSCLK output ends (the DSCLK signals in Fig. 1 for exporting DSCLK signals
Outgoing position), the CMD output ends (outgoing position of cmd signal in Fig. 1) for exporting cmd signal, for exporting DATA signal
DATA output ends (outgoing position of DATA signal in Fig. 1)；
The data reception module 41 includes DSYNC receiving terminals (the DSYNC signals in Fig. 1 for receiving DSYNC signals
Receiving position), the DSCLK receiving terminals (receiving position of DSCLK signals in Fig. 1) for receiving DSCLK signals, for receiving
The CMD receiving terminals (receiving position of cmd signal in Fig. 1) of cmd signal, for receiving the DATA receiving terminals of DATA signal (in Fig. 1
The receiving position of DATA signal).Wherein, ADDR of the CMD receiving terminals of cmd signal in cmd signal is received to differentiate data
Source, data type is differentiated according to STATE.
In certain embodiments, as shown in Figures 4 and 8, Fig. 8 is the one kind of the present invention according to an exemplary embodiment
The block diagram of the data is activation matching module of data transmission device.The data is activation matching module 12 includes：
Order sends matching unit 121, is connected to the data match module 11 and the data outputting module 13, is used for
Its step-by-step is matched and exported after the cmd signal for receiving the output of data match module 11；In the embodiment shown in Fig. 4
In, the data is activation matching module 12 is CMD_FRAM.
Data is activation matching unit 122, is connected to the data match module 11 and the data outputting module 13, is used for
Its step-by-step is matched and exported after the DATA signal for receiving the output of data match module 11；In the implementation shown in Fig. 4
In example, the data is activation matching module 12 is DATA_FRAM.
As shown in figs. 6 and 9, Fig. 9 is a kind of data transmission device of the present invention according to an exemplary embodiment
The block diagram of data reception module.The data reception module 41 includes：
Order receiving unit 411, is connected to the data resolution module 42 and the differential signal adjuster, for receiving
The cmd signal of the differential signal adjuster conversion simultaneously outputs this to the data resolution module 42；In the implementation shown in Fig. 6
In example, the data reception module 41 is CMD_RECIVE.
Data receipt unit 412, is connected to the data resolution module 42 and the differential signal adjuster, for receiving
The DATA signal of the differential signal adjuster conversion simultaneously outputs this to the data resolution module 42.In the reality shown in Fig. 6
Apply in example, the data reception module 41 is DATA_RECIVE.
In certain embodiments, the order sends matching unit 121 and/or the data is activation matching unit 122
Quantity is multiple；That is, arbitrarily extensible port number (the order transmission for sending data of the framework of first fpga chip 1
With unit 121 and/or data is activation matching unit 122), can for example increase a DATA1_RECIVE, output is more one
DATA1 signals.It is noted that often increase data channel all the way increases by one group of twisted-pair feeder it is necessary to corresponding.
The quantity of the order receiving unit 411 and/or the data receipt unit 412 is multiple.That is, with described
One fpga chip 1 (transmitting terminal) correspondence, if first fpga chip 1 increases a passage for transmission data, and (order sends
Matching unit 121 and/or data is activation matching unit 122), then the second fpga chip 4 needs to increase a data receiving channel
(order receiving unit 411 and/or data receipt unit 412).
In certain embodiments, as shown in Fig. 4 and Figure 10, Figure 10 is one of the present invention according to an exemplary embodiment
Plant the block diagram of the data match module of data transmission device.The data match module 11 includes：
Data category switch unit 111, is connected to the data is activation matching module 12, is transmitted for switching needs
Data transmission classification after output it.In the embodiment shown in fig. 4, the RATE signals in Fig. 4 are used for data is activation
The switching of classification, it will be appreciated that, regularly control the RATE signals also to realize time-multiplexed data is activation.
Said apparatus provided in an embodiment of the present invention, it is possible to achieve the one-way data transfer speed of more than 10Mbps, and
The different types of data of transmission can be distinguished in same data channel.
The present invention also provides a kind of ink-jet print system, including described data transmission device.The ink-jet print system
The one-way data transfer speed of more than 10Mbps can be realized with the data transmission device, and can be in same data channel
Distinguish the beneficial effect for sending different types of data.
Correspondence data transmission device provided in an embodiment of the present invention, the present invention also provides data transmission method, such as Figure 11 institutes
Show, Figure 11 is a kind of flow chart of data transmission method of the present invention according to an exemplary embodiment.The method may include：
Step S10, the data being transmitted by the reception needs of the first fpga chip 1 simultaneously export corresponding TTL electricity
Ordinary mail number；
Step S20, TTL signal that first fpga chip 1 exports is received by difference signal generator 2 and by its turn
Exported after being changed to high-speed differential signal；That is, the TTL signal that the step exports the first fpga chip 1 is changed for ease of long distance
From the high-speed differential signal of transmission.
Step S30, the high-speed differential signal that the output of the difference signal generator 2 is received by differential signal demodulator 3
And it is converted into Transistor-Transistor Logic level signal；That is, the high-speed differential signal that the step will be received is converted into TTL signal, so as to
Two fpga chips 4 are acquired.
Step S40, the Transistor-Transistor Logic level signal that the differential signal adjuster conversion is gathered by the second fpga chip 4.
In certain embodiments, as shown in Figures 3 to 6, first fpga chip 1 includes data match module 11, number
According to transmission matching module 12 and data outputting module 13；Second fpga chip 4 includes data reception module 41 and data solution
Analysis module 42.
The step S10 includes：
After the data being transmitted by 11 pairs of needs of the data match module are matched according to classification with speed
Output；In the embodiment shown in fig. 4, the data match module 11 is FRAM_CTRL, and FRAM_CTRL is responsible to needing
Transmission data category and speed etc. are matched.
Pressed after receiving the data that the data match module 11 is exported by the data is activation matching module 12
Position matches and exports；In the embodiment shown in fig. 4, the data is activation matching module 12 is CMD_FRAM and DATA_
FRAM, in the present embodiment, CMD_FRAM and DATA_FRAM is actually identical two data is activation matching modules,
Data are sent for step-by-step matching；In the life and death shown in Fig. 4 is returned, ADDR and STATE signals are used to generate cmd signal.Can
Understand, the arbitrarily extensible port number (data is activation matching module 12) for sending data of framework of first fpga chip 1,
For example in the case where other modules do not do big change integrally, a DATA1_FRAM, many DATA1 letters of output can be increased
Number.It is noted that often increase data channel all the way increases by one group of twisted-pair feeder it is necessary to corresponding.
The data is activation matching module 12 and the data match module 11 are received by the data outputting module 13
After the data of output, Transistor-Transistor Logic level signal is exported；In the embodiment shown in fig. 4, the data outputting module 13 is DATA_
OUT, for exporting cmd signal, DATA signal, DSYNC signals and DCLK signal lamp Transistor-Transistor Logic level signal.
The step S40 includes：
The Transistor-Transistor Logic level signal that the data outputting module 13 is exported is received by the data reception module 41；In Fig. 6 institutes
In the embodiment shown, the data reception module 41 includes CMD_RECIVE, DATA_RECIVE, and both are identicals two
Data reception module, the Transistor-Transistor Logic level signal for simply receiving in logic is divided into two classifications of cmd signal and DATA signal.It is appreciated that
, it is corresponding with first fpga chip 1 (transmitting terminal), if first fpga chip 1 increases by one sends the logical of data
Road (data is activation matching module 12), then the second fpga chip 4 need increase a data receiving channel (data reception module
41)。
The Transistor-Transistor Logic level signal received by 42 pairs of data reception modules 41 of the data resolution module carries out parsing
Afterwards, data corresponding with the Transistor-Transistor Logic level signal are exported.In the embodiment shown in fig. 6, the data resolution module 42 is
DATE_DEV, DATE_DEV are responsible for cmd signal to be parsed into COMMAND and ADDR while the DATA data of corresponding states are defeated
Go out.The above method provided in an embodiment of the present invention, it is possible to achieve the one-way data transfer speed of more than 10Mbps, and can be same
Distinguished on one data passage and send different types of data.It is intelligible, due to the data transmission method pair that the present invention is provided
Data transmission device provided in an embodiment of the present invention is answered, therefore, the data transmission method illustrated in embodiment of above belongs to
Within the category of data transmission method of the invention, therefore no longer repeat one by one herein.
It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program
Product.Therefore, the present invention can be using the reality in terms of complete hardware embodiment, complete software embodiment or combination software and hardware
Apply the form of example.And, the present invention can be used and wherein include the computer of computer usable program code at one or more
The shape of the computer program product implemented in usable storage medium (including but not limited to magnetic disk storage and optical memory etc.)
Formula.
The present invention is the flow with reference to method according to embodiments of the present invention, equipment (system) and computer program product
Figure and/or block diagram are described.It should be understood that every first-class during flow chart and/or block diagram can be realized by computer program instructions
The combination of flow and/or square frame in journey and/or square frame and flow chart and/or block diagram.These computer programs can be provided
The processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce
A raw machine so that produced for reality by the instruction of computer or the computing device of other programmable data processing devices
The device of the function of being specified in present one flow of flow chart or multiple one square frame of flow and/or block diagram or multiple square frames.
These computer program instructions may be alternatively stored in can guide computer or other programmable data processing devices with spy
In determining the computer-readable memory that mode works so that instruction of the storage in the computer-readable memory is produced and include finger
Make the manufacture of device, the command device realize in one flow of flow chart or multiple one square frame of flow and/or block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented treatment, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of data transmission device, it is characterised in that including output circuit and receiving circuit；The output circuit includes：
First fpga chip, is arranged on the output circuit, and for receive need after the data that are transmitted output with
Its corresponding Transistor-Transistor Logic level signal；
Difference signal generator, is arranged on the output circuit, and is connected to first fpga chip, described for receiving
The TTL signal of the first fpga chip output is simultaneously converted into output after high-speed differential signal；
The receiving circuit includes：
Differential signal demodulator, is arranged in the receiving circuit, and is connected to the difference signal generator, for receiving
State the high-speed differential signal of difference signal generator output and be converted into Transistor-Transistor Logic level signal；
Second fpga chip, is arranged in the receiving circuit, and is connected to the differential signal demodulator, described for gathering
The Transistor-Transistor Logic level signal of differential signal adjuster conversion.
2. data transmission device as claimed in claim 1, it is characterised in that first fpga chip includes：
Data match module, for being matched with speed according to classification to the data that are transmitted of needs after output；
Data is activation matching module, is connected to the data match module, for receiving the data match module output
Its step-by-step is matched and exported after data；
Data outputting module, is connected to the data is activation matching module and the data match module, for receiving described
After data is activation matching module and the data of data match module output, Transistor-Transistor Logic level signal is exported；
Second fpga chip includes：
Data reception module, is connected to the data outputting module, the Transistor-Transistor Logic level for receiving the data outputting module output
Signal；
Data resolution module, is connected to the data reception module, for the Transistor-Transistor Logic level letter received to the data reception module
Output data corresponding with its state after number being parsed.
3. data transmission device as claimed in claim 2, it is characterised in that first fpga chip also includes：
Rate selection module, is connected to the data match module, the data is activation matching module and the data output mould
Block, for carrying out speed selection.
4. data transmission device as claimed in claim 2 or claim 3, it is characterised in that the Transistor-Transistor Logic level signal includes DSYNC letters
Number, DSCLK signals, cmd signal and DATA signal；
The data outputting module is included for exporting the DSYNC output ends of DSYNC signals, for exporting DSCLK signals
DSCLK output ends, the CMD output ends for exporting cmd signal, the DATA output ends for exporting DATA signal；
The data reception module is included for receiving the DSYNC receiving terminals of DSYNC signals, for receiving DSCLK signals
DSCLK receiving terminals, the CMD receiving terminals for receiving cmd signal, the DATA receiving terminals for receiving DATA signal.
5. data transmission device as claimed in claim 4, it is characterised in that the data is activation matching module includes：
Order sends matching unit, is connected to the data match module and the data outputting module, for receiving described
Its step-by-step is matched and exported after the cmd signal of data match module output；
Data is activation matching unit, is connected to the data match module and the data outputting module, for receiving described
Its step-by-step is matched and exported after the DATA signal of data match module output；
The data reception module includes：
Order receiving unit, is connected to the data resolution module and the differential signal adjuster, for receiving the difference
The cmd signal of signal conditioner conversion simultaneously outputs this to the data resolution module；
Data receipt unit, is connected to the data resolution module and the differential signal adjuster, for receiving the difference
The DATA signal of signal conditioner conversion simultaneously outputs this to the data resolution module.
6. data transmission device as claimed in claim 5, it is characterised in that the order sends matching unit and/or described
The quantity of data is activation matching unit is multiple；
The quantity of the order receiving unit and/or the data receipt unit is multiple.
7. data transmission device as claimed in claim 2, it is characterised in that the data match module includes：
Data category switch unit, is connected to the data is activation matching module, for switching the data for needing to be transmitted
Output it after transmission classification.
8. a kind of ink-jet print system, it is characterised in that including the data transmission device described in any one of claim 1 to 7.
9. a kind of data transmission method, it is characterised in that including：
Being received by the first fpga chip is needed the data that are transmitted and exports corresponding Transistor-Transistor Logic level signal；
Receive the TTL signal of the first fpga chip output and be converted into high-speed-differential by difference signal generator and believe
Exported after number；
The high-speed differential signal of the difference signal generator output is received by differential signal demodulator and TTL is converted into
Level signal；
The Transistor-Transistor Logic level signal that the differential signal adjuster is changed is gathered by the second fpga chip.
10. data transmission method as claimed in claim 9, it is characterised in that first fpga chip includes Data Matching
Module, data is activation matching module and data outputting module；Second fpga chip includes data reception module and data solution
Analysis module；
The data being transmitted by the first fpga chip reception needs simultaneously export corresponding Transistor-Transistor Logic level signal, wrap
Include：
Exported after being matched with speed according to classification to the data that needs are transmitted by the data match module；
Its step-by-step is matched simultaneously after receiving the data that the data match module is exported by the data is activation matching module
Output；
The data that the data is activation matching module and the data match module are exported are received by the data outputting module
Afterwards, Transistor-Transistor Logic level signal is exported；
It is described that the Transistor-Transistor Logic level signal that the differential signal adjuster is changed is gathered by the second fpga chip, including：
The Transistor-Transistor Logic level signal that the data outputting module is exported is received by the data reception module；
After being parsed to the Transistor-Transistor Logic level signal that the data reception module is received by the data resolution module, output
Data corresponding with the Transistor-Transistor Logic level signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710015292.XA CN106776414A (en) | 2017-01-10 | 2017-01-10 | Data transmission device and method, ink-jet print system |
| PCT/CN2017/116251 WO2018130045A1 (en) | 2017-01-10 | 2017-12-14 | Data transmission device, method, and inkjet printing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710015292.XA CN106776414A (en) | 2017-01-10 | 2017-01-10 | Data transmission device and method, ink-jet print system |
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| CN106776414A true CN106776414A (en) | 2017-05-31 |
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| CN201710015292.XA Pending CN106776414A (en) | 2017-01-10 | 2017-01-10 | Data transmission device and method, ink-jet print system |
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| CN (1) | CN106776414A (en) |
| WO (1) | WO2018130045A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018130045A1 (en) * | 2017-01-10 | 2018-07-19 | 深圳华云数码有限公司 | Data transmission device, method, and inkjet printing system |
| CN111421961A (en) * | 2020-04-13 | 2020-07-17 | 无锡翼盟电子科技有限公司 | Method and consumable box capable of realizing rapid power-on and rapid storage of consumable chip |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110287132A (en) * | 2019-05-17 | 2019-09-27 | 全球能源互联网研究院有限公司 | A kind of data communication processing board |
| CN114050838B (en) * | 2021-10-30 | 2023-12-29 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | 100Gbps bandwidth RapidIO signal source |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101722729A (en) * | 2008-10-13 | 2010-06-09 | 北京美科艺数码科技发展有限公司 | Method and device for transmitting data between main board and spray nozzle panel of ink-jet printer |
| JP2010131761A (en) * | 2008-12-02 | 2010-06-17 | Konica Minolta Ij Technologies Inc | Data transfer method, data transfer system, and inkjet recording apparatus |
| CN103885734A (en) * | 2014-04-02 | 2014-06-25 | 北京美科艺数码科技发展有限公司 | Ink-jet head control panel of ink-jet printer and method for transmission of printable data |
| CN104035904A (en) * | 2014-07-04 | 2014-09-10 | 山东超越数控电子有限公司 | FPGA-based interconnection device among chips |
| CN205620995U (en) * | 2016-04-18 | 2016-10-05 | 厦门立控科技有限公司 | Enhancement mode combination treater based on FPGA |
| CN206470748U (en) * | 2017-01-10 | 2017-09-05 | 深圳华云数码有限公司 | Data transmission device and ink-jet print system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218858B1 (en) * | 1999-01-27 | 2001-04-17 | Xilinx, Inc. | Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits |
| CN103036822A (en) * | 2012-12-14 | 2013-04-10 | 深圳先进技术研究院 | Data transmission device and method of ultrasonic imaging system |
| CN103166818B (en) * | 2013-02-26 | 2016-05-11 | 深圳市东微智能科技有限公司 | A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof |
| CN106776414A (en) * | 2017-01-10 | 2017-05-31 | 深圳华云数码有限公司 | Data transmission device and method, ink-jet print system |
-
2017
- 2017-01-10 CN CN201710015292.XA patent/CN106776414A/en active Pending
- 2017-12-14 WO PCT/CN2017/116251 patent/WO2018130045A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101722729A (en) * | 2008-10-13 | 2010-06-09 | 北京美科艺数码科技发展有限公司 | Method and device for transmitting data between main board and spray nozzle panel of ink-jet printer |
| JP2010131761A (en) * | 2008-12-02 | 2010-06-17 | Konica Minolta Ij Technologies Inc | Data transfer method, data transfer system, and inkjet recording apparatus |
| CN103885734A (en) * | 2014-04-02 | 2014-06-25 | 北京美科艺数码科技发展有限公司 | Ink-jet head control panel of ink-jet printer and method for transmission of printable data |
| CN104035904A (en) * | 2014-07-04 | 2014-09-10 | 山东超越数控电子有限公司 | FPGA-based interconnection device among chips |
| CN205620995U (en) * | 2016-04-18 | 2016-10-05 | 厦门立控科技有限公司 | Enhancement mode combination treater based on FPGA |
| CN206470748U (en) * | 2017-01-10 | 2017-09-05 | 深圳华云数码有限公司 | Data transmission device and ink-jet print system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018130045A1 (en) * | 2017-01-10 | 2018-07-19 | 深圳华云数码有限公司 | Data transmission device, method, and inkjet printing system |
| CN111421961A (en) * | 2020-04-13 | 2020-07-17 | 无锡翼盟电子科技有限公司 | Method and consumable box capable of realizing rapid power-on and rapid storage of consumable chip |
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| Publication number | Publication date |
|---|---|
| WO2018130045A1 (en) | 2018-07-19 |
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