CN113891537B - Method, device and medium for timing logic through computer analog digital dimming protocol - Google Patents
Method, device and medium for timing logic through computer analog digital dimming protocol Download PDFInfo
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- CN113891537B CN113891537B CN202111256310.6A CN202111256310A CN113891537B CN 113891537 B CN113891537 B CN 113891537B CN 202111256310 A CN202111256310 A CN 202111256310A CN 113891537 B CN113891537 B CN 113891537B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/165—Controlling the light source following a pre-assigned programmed sequence; Logic control [LC]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/155—Coordinated control of two or more light sources
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention relates to the field of digital signal control, and particularly discloses a method, a device and a medium for analog digital dimming protocol sequential logic through a computer, wherein the method comprises the steps of calculating analog sequential parameters according to configurable parameters of a first port of the computer and digital dimming protocol data packets required to be simulated; converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter; configuring parameters of the first port as the analog timing parameters; and controlling the first port to send a first level signal to a level conversion circuit according to the message data frame. The invention directly outputs the level signal of the analog-digital dimming protocol sequential logic through the port of the computer, does not need to carry out protocol conversion of the output signal through the singlechip circuit, saves the hardware cost, ensures lower signal output delay, increases the transmission speed of the control signal, and ensures that the equipment connection is more convenient.
Description
Technical Field
The present invention relates to the field of digital signal control, and in particular, to a method, an apparatus, and a medium for timing logic of a computer analog digital dimming protocol.
Background
Along with the development of modern technology, the electrification and digitalization degrees of stages and entertainment places are higher and higher, how to control various kinds of complicated lamplight and stage equipment more efficiently and conveniently becomes a difficult problem of industry development, and the digital multiplexing signal protocol for controlling a plurality of equipment by sharing one control bus is one of schemes for solving the problems.
The most commonly used digital multiplexing signal protocol is the international standard USITT DMX512-a protocol (DMX 512 for short), because the time sequence requirement of the DMX512 on signals is to reach microsecond level, the existing light control console generally adopts the IO pin of the MCU singlechip to simulate the time sequence level of the DMX512 protocol, and then outputs the time sequence level to the 458 bus through the level conversion circuit, so that the implementation is easy, and for the port of the computer, the computer end and the singlechip circuit are generally adopted to establish a conventional data communication protocol because the required time sequence level is difficult to directly control the IO port to generate the data signal like the singlechip, the computer end sends 512 channel data to the singlechip circuit, and the singlechip is then used to simulate the time sequence signal logic required by the DXM512 protocol after receiving the data, however, the singlechip conversion circuit has high implementation cost, is complicated to debug, a certain delay is generated, and the installation and recovery of the equipment are troublesome.
Disclosure of Invention
In order to solve the problems of high implementation cost, complex debugging, delayed signals and troublesome equipment installation and recovery of the existing digital dimming protocol conversion circuit, the invention provides a method, a device and a medium for sequential logic of a computer analog digital dimming protocol.
The technical scheme adopted by the invention is as follows: a method of timing logic via a computer analog to digital dimming protocol, comprising:
calculating a simulation time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet required to be simulated;
converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;
configuring parameters of the first port as the analog timing parameters;
and controlling the first port to send a first level signal to a level conversion circuit according to the message data frame so that the level conversion circuit converts the first level signal into a digital dimming signal and then sends the digital dimming signal to a digital dimming control bus.
Preferably, the calculating the analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be simulated specifically includes:
calculating the minimum unit data bit time according to the communication rate which can be simulated by the first port;
and obtaining the analog time sequence parameter of the first port according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.
Preferably, the converting the digital dimming protocol data packet into a message data frame according to the analog timing parameter specifically includes:
the digital dimming protocol data packet includes: control frames and data frames;
obtaining a first simulation time sequence parameter according to the time sequence logic of the control frame and the minimum unit data bit time;
and obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time.
Preferably, the converting the digital dimming protocol data packet into a message data frame according to the analog timing parameter specifically includes:
converting the control frame into a first message data frame according to the first simulation time sequence parameter;
and converting the data frame into a second message data frame according to the second simulation time sequence parameter.
Preferably, the configuring the parameter of the first port as the analog timing parameter controls the first port to send a first level signal to a level conversion circuit according to the packet data frame, specifically:
the first port is configured as a first analog time sequence parameter, and is controlled to send a control frame signal to a level conversion circuit according to the first message data frame;
and then, the first port is configured as a second analog time sequence parameter, and the first port is controlled to send a data frame signal to a level conversion circuit according to the second message data frame.
The technical scheme adopted by the invention also comprises the following steps: a device for timing logic through a computer analog digital dimming protocol comprises a parameter calculation module, a data conversion module, a parameter configuration module, a transmission control module and a level conversion circuit;
the parameter calculation module is used for calculating the analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be analog;
the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;
the parameter configuration module is used for configuring parameters of the first port into the simulation time sequence parameters;
the sending control module is used for controlling the first port to send a first level signal to the level conversion circuit according to the message data frame;
the level conversion circuit is used for converting the first level signal into a digital dimming signal and then sending the digital dimming signal to the digital dimming control bus.
Preferably, the parameter calculation module comprises a first calculation unit and a second calculation unit;
the digital dimming protocol data packet includes: control frames and data frames;
the first calculation unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;
the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.
Preferably, the data conversion module comprises a first conversion unit and a second conversion unit;
the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;
the second conversion unit is configured to convert the data frame into a second packet data frame according to the second analog timing parameter.
Preferably, the transmission control module comprises a first control unit and a second control unit;
the first control unit is used for controlling the parameter configuration module to configure the parameter of the first port into the first analog time sequence parameter and controlling the first port to send a control frame signal to the level conversion circuit according to the first message data frame;
the second control unit is configured to control the parameter configuration module to configure the parameter of the first port to the second analog timing parameter, and control the first port to send a data frame signal to the level conversion circuit according to the second message data frame.
The technical scheme adopted by the invention also comprises a computer readable storage medium, wherein the computer readable storage medium comprises a stored computer program, and the equipment where the computer readable storage medium is located is controlled to execute the method for timing logic through the computer analog digital dimming protocol when the computer program runs.
The beneficial effects of the invention are as follows:
the level signal of the analog digital dimming protocol sequential logic is directly output through the port of the computer, the protocol conversion of the output signal is not needed to be carried out through the singlechip circuit, the hardware cost is saved, the signal output delay is lower, the control signal transmission speed is increased, and the equipment connection is more convenient.
Preferably, the control frame and the data frame are respectively sent through different port configuration parameters, so that the optimal port parameters are configured for different signals, the universality of the scheme is higher, and the sending efficiency is faster.
Drawings
The invention will be further described with reference to the accompanying drawings, in which:
FIG. 1 is a schematic flow chart of one embodiment of the present invention;
FIG. 2 is a serial port output connection diagram according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of COM serial port configuration parameters according to one embodiment of the present invention;
FIG. 4 is a table of DMX512 signal analog parameters according to one embodiment of the present invention;
FIG. 5 is a table of parameters for the DMX512 signal;
FIG. 6 is a schematic diagram of the timing logic of the DMX512 signal.
In the figure: 1. a BREAK signal; 2. MAB signal; 3. a data frame time slot; 4. a data frame start bit; 5. a lowest data bit; 6. the highest data bit; 7. a first stop position; 8. a second stop position; 9. a data frame interval; 10. an MTBP signal; 11. message data frame time slots; 12. transmitting a reset sequence; 13. DMX512 packets; 14. an SC signal; 15. a first data frame; 16. and an nth data frame.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention relates to a method, a device and a medium for timing logic of a computer analog-digital dimming protocol, wherein the working principle of the scheme relates to TTL level, USB level, RS232 level and RS485 level, the TTL level is adopted for the bus (and a bus interface on a computer main board) communication of a computer, the RS-232 level is adopted for a serial communication interface (COM serial port), the USB level is adopted for the USB interface, the RS485 bus communication adopts the RS-485 level, and a level conversion circuit among the levels belongs to the prior art.
Referring to fig. 1 to fig. 4, as one embodiment of the present invention, the present embodiment is applied to a signal sequential logic using a com serial port of a computer to simulate an international standard USITT DMX512-a protocol (abbreviated as DMX 512), and outputs a TTL signal through the serial port, and directly converts the TTL signal into an RS485 bus transmission signal through an RS485 chip for transmission.
Referring to fig. 1 to 2, the method of the present embodiment includes the following implementation steps:
s1, calculating a simulation time sequence parameter according to a configurable parameter of a first port of a computer and a digital dimming protocol data packet required to be simulated;
s2, converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;
s3, configuring parameters of the first port as the simulation time sequence parameters;
and S4, controlling the first port to send a first level signal to a level conversion circuit according to the message data frame, converting the level of the first level signal into the level corresponding to the digital dimming control bus by the level conversion circuit, and sending the level to the digital dimming control bus.
Preferably, the method for calculating the analog time sequence parameter comprises the following steps:
a1, calculating minimum unit data bit time according to the communication rate which can be simulated by the first port;
a2, calculating a solution of the first port configuration parameter as an analog time sequence parameter according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.
Wherein the first port configuration parameters include communication rate, data bits, stop bits, and parity bits.
Preferably, the digital dimming protocol data packet is converted into a message data frame according to the analog timing parameter, and the digital dimming protocol data packet includes a control frame and a data frame, so that the implementation steps are as follows:
b1, obtaining a first simulation time sequence parameter according to the time sequence logic of the control frame and the minimum unit data bit time;
and B2, obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time.
Preferably, the converting the digital dimming protocol data packet into the message data frame according to the analog timing parameter includes the following steps:
c1, converting a control frame into a first message data frame according to the first simulation time sequence parameter;
and C2, converting the data frame into a second message data frame according to the second simulation time sequence parameter.
Preferably, the configuring the parameter of the first port as the analog timing parameter controls the first port to send a first level signal to a level conversion circuit according to the packet data frame, including the following steps:
d1, configuring the first port as a first analog timing parameter;
d2, controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;
d3, configuring the first port as a second analog timing parameter;
and D4, controlling the first port to send a data frame signal to the level conversion circuit according to the second message data frame.
According to the scheme, the level signal of the analog-digital dimming protocol sequential logic is directly output through the port of the computer, protocol conversion of output signals is not needed through the singlechip circuit, hardware cost is saved, signal output delay is lower, control signal transmission speed is increased, and equipment connection is more convenient.
As another embodiment of the present invention, a method for simulating DMX512 sequential logic through a COM serial port of a computer, wherein a first port corresponds to the COM serial port, and the digital dimming protocol data packet comprises: control frames and data frames; the first level signal includes a control frame signal and a data frame signal.
Referring to fig. 5 and 6, the signal transmission of DMX512, depending on the hardware circuit RS485 bus transmission signal, has strict time limitation requirements on signal timing, has a certain requirement on the transmission rate of data, and is typically 250kbps, with a duration of 4us for each bit, a duration of 44us for each data field, and the protocol also specifies that each DMX512 packet supports transmission of 512 frames of data at maximum.
In the DMX512 sequential logic simulated by the port of the computer, the MTBP signal, the BREAK signal and the MAB signal belong to control signals, and the data frame signal corresponds to a data field in the DMX512 protocol sequential logic required to be simulated, wherein the data field comprises an SC signal as a start code.
The implementation steps of the method for timing logic of the analog-digital dimming protocol of the computer are as follows:
s1, calculating minimum unit data bit time according to the communication rate which can be simulated by the first port;
s1.1, obtaining a first simulation time sequence parameter according to the time sequence logic of the control frame and the minimum unit data bit time;
s1.2, obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time;
s2, calculating a first simulation time sequence parameter according to the configurable parameter of a first port of the computer and the time sequence logic of the control frame, and converting the control frame into a first message data frame according to the first simulation time sequence parameter; calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame, and converting the data frame into a second message data frame according to the second simulation time sequence parameter;
s3, configuring the first port as a first analog time sequence parameter, and controlling the first port to send a control frame signal to a level conversion circuit according to the first message data frame;
s4, configuring the first port as a second analog time sequence parameter, and controlling the first port to send a data frame signal to a level conversion circuit according to the second message data frame.
Since DMX512 specifies that each timing unit must be performed according to the specified timing format and time, a complete DMX512 packet is composed of an MTBP signal, a BREAK signal, and a MAB signal, and the following data fields, and the duration of the DMX512 packet corresponds to the packet data frame time slot, which is respectively as follows:
(1) The MTBP signal (Mark Time Between Packages), also called MBB signal (Mark Before Between), marks that the transmission of a complete DMX512 data packet is completed, and is the indication bit of the next DMX512 data packet to be started, and is valid at high level, which indicates that the current transmission line is in an idle state and no data is transmitted;
(2) The BREAK signal is a start control signal for a DMX512 packet, and corresponds to a start phase of a new DMX512 packet; the DMX512 protocol provides that the BREAK signal is active low and the duration is not less than the length of the data field in two DMX512 data packets, namely not less than 88us;
(3) The MAB signal (Mark After BREAK) is an indication that the DMX512 packet starts to be sent, and is added to distinguish between the low level of BREAK and the low level of the start bit of the data field because the first bit of each data field is low; the protocol specifies that the typical duration of a MAB is 8us to 1s, i.e., two bits of time, active high;
(4) The SC signal (Start Code), namely the Start Code, frame 0 data, is the same as a common data field, but the 8-bit data bits of the SC signal are all zero, and the SC signal is the Start flag byte of the data field in the DMX512 data packet;
(5) A data field beginning with the SC signal and followed by a first data frame through an nth data frame, wherein n is 512 max, i.e., the DMX512 data packet contains 512 data frames at most; carry the active content of DMX512 packets.
The BREAK signal, the MAB signal and the SC signal form a transmission reset sequence together, namely after each DMX512 data packet is transmitted, the next DMX512 data packet is confirmed to start to be transmitted through the transmission reset sequence.
The time length of a single data frame corresponds to a data frame time slot, and each data frame consists of a data frame start bit, a lowest data bit to a highest data bit, a first stop bit and a second stop bit; a data frame interval is arranged between two adjacent data frames.
Referring to fig. 3 to 4, the specific calculation steps in this embodiment are as follows:
s1, calculating time sequence parameters of an analog MTBP signal, a BREAK signal and a MAB signal according to configurable parameters of a COM serial port of a computer and DMX512 protocol time sequence logic;
s1.1, according to the DMX512 protocol sequential logic, the MTBP signal is omitted because the effective time of the MTBP signal can be 0;
s1.2, according to BREAK signal and MAB signal sequential logic in the DMX512 protocol; according to the effective configurable parameters of the COM serial port of the computer, setting the communication speed as b, the data bit as d, the stop bit as s, setting the parity check bit as none, solving the b, d and s, and outputting as a first simulation time sequence parameter;
s1.3, solving COM serial port configuration parameters suitable for generating data fields, solving b, d and S, and outputting second simulation time sequence parameters;
s2, writing a first message data frame according to a BREAK signal and a MAB signal of the DMX512 protocol sequential logic, and writing a second message data frame according to a data field;
s3, configuring parameters of a COM serial port on a computer as first simulation time sequence parameters; the COM serial port sends a control frame signal to the level conversion circuit according to the first message data frame;
s4, configuring parameters of a COM serial port on a computer as second simulation time sequence parameters; the COM serial port sends a data frame signal to the level conversion circuit according to the second message data frame;
s5, the level conversion circuit converts the levels of the control frame signal and the data frame signal into the corresponding levels of the digital dimming control bus and sends the corresponding levels to the digital dimming control bus.
The specific calculation process of the simulation time sequence parameters is as follows: the baud rate b which can be output by the COM serial port is in units of bps, the time of the corresponding minimum unit data bit is t, the units are us, namely b and t meet the following equation:
t=1 second/baud rate=1000000 us/b;
according to the signal sequential logic of the COM serial port, the format of output data is as follows:
start bits (1 bit) +data bits (4-8 bits) +parity bits (0-1 bit) +stop bits (1, 1.5,2 bits).
Now the data bit is set as variable d, and the preferable values of d are 4,5,6,7 and 8; the stop bit is set as a variable s, and the desirable values of s are 1,1.5 and 2; simulating the BREAK signal and the MAB signal, the COM serial port configuration parameters need to meet the following formula conditions:
equation (1) 1000000/b=t;
formula (2) s is greater than or equal to 8us;
the s is less than or equal to 12us;
formula (4): (1+d) t is greater than or equal to 88us;
in one embodiment of the present invention, the baud rate b=250000 bps of the COM serial port corresponds to a minimum unit data bit time of t=1000000 us/250000 bps=4us; according to the DMX512 protocol sequential logic, the BREAK signal time is not less than 88us, and the MAB signal time is generally not less than 8us and not more than 12us.
Since there are only three s-ary arrays, the simplest substitution approach can be used to solve the above approach.
When s=1, according to the formula (2) and the formula (3), the preferable values of t are t=8, 9, 10, 11, 12, and t=8, 9, 10, 11, 12 are substituted into the formula (1), so that t is equal to 8us and 10us because b is a positive integer; substituting the value of t=8us into the formula (4), (1+d) with the value of 8 being larger than or equal to 88, and obtaining that d is larger than or equal to 10 can meet the condition, wherein the value range of d is only 4,5,6,7 and 8, so that t=8 is unsuitable;
substituting the value of t=10us into the formula (4), (1+d) with the value of 10 being more than or equal to 88, and obtaining that d is more than or equal to 7.8 can meet the condition, wherein d can be d=8 because the range of the value of the data bit d is only 4,5,6,7 and 8;
other combinations are also equally deduced, as long as all the above 4 formulas are satisfied;
the parameter configuration of a group of analog BREAK signal and MAB signal COM serial ports can be obtained, namely, the first analog time sequence parameter is b=100000 bps, d=8 bits, s=1; at this time, the COM serial port data frame format is 1bit start bit, 8bit data bit, 1bit stop bit, and the communication rate is 100000bps.
Transmitting a BREAK signal: when the transmission Data data=0 is configured, the serial port transmission side Data line Tx is kept at the low level BREAK for a time= (1+8) ×10us=90 us, and the condition that 88us is satisfied.
Meanwhile, the delay time of the stop bit is ts=s=t=1×10us=10us to generate an MAB signal, and the MAB signal meets the use requirements of more than or equal to 8us and less than or equal to 12us of the standard.
Because the formats of the SC signal and the data field are the same, the same COM serial port parameter configuration, that is, the second analog timing parameter in the embodiment, the communication rate b=250000bps is adopted; data bit d=8 bits; stop bit s=1 bit; the parity bit p is set to none; transmitting SC signal, then transmitting the first data frame of data field to the nth data frame, with 512 fields at most;
and finally, a first level signal formed by the control frame signal and the data frame signal is output to an RS485 bus through an RS 232-to-RS 485 level conversion circuit.
The configuration parameters can have a plurality of solutions, and the solution can be used as long as the solution is a solution of a COM serial port output DMX512 protocol, and repeated calculation is not needed.
According to the embodiment, the sequential logic signal conforming to the DMX512 protocol is directly output through the COM port or the USB port of the computer, and protocol conversion of output signals is not needed through the MCU singlechip circuit, so that hardware cost is saved, signal output delay is lower, control signal transmission speed is increased, and equipment connection is more convenient.
The scheme can be used for interconnection between various computer ports and various analog-digital dimming protocols, is compatible with various bus level conversion circuits, and has high scheme compatibility.
As another embodiment of the invention, the device for timing logic of the analog-digital dimming protocol through the computer comprises a parameter calculation module, a data conversion module, a parameter configuration module, a transmission control module and a level conversion circuit.
The parameter calculation module is used for calculating the analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be analog;
the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the digital dimming protocol time sequence logic and the analog time sequence parameter;
the parameter configuration module is used for configuring parameters of the first port into simulation time sequence parameters;
the transmission control module is used for controlling the first port to transmit a first level signal to the level conversion circuit according to the message data frame;
the level conversion circuit is used for converting the level of the first level signal into the level corresponding to the digital dimming control bus and sending the level to the digital dimming control bus.
By the device of the embodiment, the method of the timing logic through the computer analog digital dimming protocol in the embodiment is realized.
Preferably, the parameter calculation module comprises a first calculation unit and a second calculation unit;
the digital dimming protocol data packet includes: control frames and data frames;
the first calculation unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;
the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.
Preferably, the data conversion module comprises a first conversion unit and a second conversion unit;
the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;
the second conversion unit is configured to convert the control frame into a second packet data frame according to the second analog timing parameter.
Preferably, the transmission control module comprises a first control unit and a second control unit;
the first control unit is used for controlling the parameter configuration module to configure the parameter of the first port into the first analog time sequence parameter and controlling the first port to send a control frame signal to the level conversion circuit according to the first message data frame;
the second control unit is configured to control the parameter configuration module to configure the parameter of the first port to the second analog timing parameter, and control the first port to send a data frame signal to the level conversion circuit according to the second message data frame.
The invention also discloses a terminal device, which comprises a processor and a storage device, wherein the storage device is used for storing one or more programs; the processor implements the above-described method of testing impact properties of a material when one or more programs are executed by the processor. The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, referred to as a control center for the test equipment, that interfaces and lines to various parts of the overall test equipment.
The storage means may be used for storing computer programs and/or modules, and the processor may implement various functions of the terminal device by running or executing the computer programs and/or modules stored in the storage means, and invoking data stored in the storage means. The storage device may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the terminal device, etc. In addition, the storage device may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid state storage device.
Wherein the terminal device integrated modules/units may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as a stand alone product. Based on such understanding, the present invention may implement all or part of the flow of the method of the above-described embodiments, or may be implemented by a computer program to instruct related hardware, and the computer program may be stored in at least one computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth.
It should be noted that the embodiments of the apparatus and device described above are only schematic, where the units described as separate units may or may not be physically separated, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the device embodiment provided by the invention, the connection relation between the modules represents that the modules have communication connection, and can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing embodiments have been provided for the purpose of illustrating the invention in further detail, and are to be understood that the foregoing embodiments are merely illustrative of the invention and are not to be construed as limiting the scope of the invention. It should be noted that any modifications, equivalent substitutions, improvements, etc. made by those skilled in the art without departing from the spirit and principles of the present invention are intended to be included in the scope of the present invention.
Claims (8)
1. A method for using computer analog digital dimming protocol sequential logic, comprising:
calculating a simulation time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet required to be simulated;
converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;
configuring parameters of the first port as the analog timing parameters;
the first port is controlled to send a first level signal to a level conversion circuit according to the message data frame so that the level conversion circuit can convert the first level signal into a digital dimming signal and send the digital dimming signal to a digital dimming control bus;
the calculating of the analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be simulated specifically comprises the following steps:
calculating the minimum unit data bit time according to the communication rate which can be simulated by the first port;
and obtaining the analog time sequence parameter of the first port according to the signal rule of the digital dimming protocol time sequence logic and the minimum unit data bit time.
2. The method according to claim 1, wherein the converting the digital dimming protocol data packet into the message data frame according to the analog timing parameter is specifically:
the digital dimming protocol data packet includes: control frames and data frames;
obtaining a first simulation time sequence parameter according to the time sequence logic of the control frame and the minimum unit data bit time;
and obtaining a second simulation time sequence parameter according to the time sequence logic of the data frame and the minimum unit data bit time.
3. The method according to claim 2, wherein the converting the digital dimming protocol data packet into the message data frame according to the analog timing parameter is specifically:
converting the control frame into a first message data frame according to the first simulation time sequence parameter;
and converting the data frame into a second message data frame according to the second simulation time sequence parameter.
4. The method according to claim 3, wherein the configuring the parameter of the first port as the analog timing parameter controls the first port to send a first level signal to a level conversion circuit according to the message data frame, specifically:
the first port is configured as a first analog time sequence parameter, and is controlled to send a control frame signal to a level conversion circuit according to the first message data frame;
and then, the first port is configured as a second analog time sequence parameter, and the first port is controlled to send a data frame signal to a level conversion circuit according to the second message data frame.
5. The device for timing logic through the computer analog digital dimming protocol is characterized by comprising a parameter calculation module, a data conversion module, a parameter configuration module, a transmission control module and a level conversion circuit;
the parameter calculation module is used for calculating the analog time sequence parameter according to the configurable parameter of the first port of the computer and the digital dimming protocol data packet to be analog;
the data conversion module is used for converting the digital dimming protocol data packet into a message data frame according to the analog time sequence parameter;
the parameter configuration module is used for configuring parameters of the first port into the simulation time sequence parameters;
the sending control module is used for controlling the first port to send a first level signal to the level conversion circuit according to the message data frame;
the level conversion circuit is used for converting the first level signal into a digital dimming signal and then sending the digital dimming signal to the digital dimming control bus;
the parameter calculation module comprises a first calculation unit and a second calculation unit;
the digital dimming protocol data packet includes: control frames and data frames;
the first calculation unit is used for calculating a first simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the control frame to be simulated;
the second calculating unit is used for calculating a second simulation time sequence parameter according to the configurable parameter of the first port of the computer and the time sequence logic of the data frame to be simulated.
6. The apparatus according to claim 5, wherein the data conversion module comprises a first conversion unit and a second conversion unit;
the first conversion unit is used for converting the control frame into a first message data frame according to the first analog time sequence parameter;
the second conversion unit is configured to convert the data frame into a second packet data frame according to the second analog timing parameter.
7. The apparatus according to claim 6, wherein the transmission control module comprises a first control unit and a second control unit;
the first control unit is used for controlling the parameter configuration module to configure the parameter of the first port into the first analog time sequence parameter and controlling the first port to send a control frame signal to the level conversion circuit according to the first message data frame;
the second control unit is configured to control the parameter configuration module to configure the parameter of the first port to the second analog timing parameter, and control the first port to send a data frame signal to the level conversion circuit according to the second message data frame.
8. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored computer program, wherein the computer program, when run, controls a device in which the computer readable storage medium is located to perform the method of timing logic by a computer analog digital dimming protocol according to any of claims 1 to 4.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202059630U (en) * | 2011-04-28 | 2011-11-30 | 上海理工大学 | Decoding device based on DMX512 protocol |
| CN102573184A (en) * | 2010-12-17 | 2012-07-11 | 明阳半导体股份有限公司 | Lighting fixture control chip, device, system as well as addressing method thereof |
| CN203368812U (en) * | 2013-03-28 | 2013-12-25 | 天津亿达海营照明有限公司 | Wireless DMX light emitting diode (LED) indoor lamp dimming controller |
| CN207947935U (en) * | 2018-04-04 | 2018-10-09 | 深圳市聪讯智能科技有限公司 | A kind of RS485 turns the controller of DMX512 |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573184A (en) * | 2010-12-17 | 2012-07-11 | 明阳半导体股份有限公司 | Lighting fixture control chip, device, system as well as addressing method thereof |
| CN202059630U (en) * | 2011-04-28 | 2011-11-30 | 上海理工大学 | Decoding device based on DMX512 protocol |
| CN203368812U (en) * | 2013-03-28 | 2013-12-25 | 天津亿达海营照明有限公司 | Wireless DMX light emitting diode (LED) indoor lamp dimming controller |
| CN207947935U (en) * | 2018-04-04 | 2018-10-09 | 深圳市聪讯智能科技有限公司 | A kind of RS485 turns the controller of DMX512 |
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