CN103166818B - A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof - Google Patents
A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof Download PDFInfo
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Abstract
The invention provides a kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof, this cluster comprises N digital sound console, unit cascaded or be connected with the FPGA of switch device respectively by FPGA; The transmission interface of FPGA unit is connected by 4 groups of differential signal lines with the receiving interface of opposite end, wherein one group be used for transmitting HCLK signal, another three groups for transmitting DX signal; Receiving interface is connected by 4 groups of differential signal lines with the transmission interface of opposite end, wherein one group be used for transmitting HCLK signal, another three groups for transmitting DR signal; Every group of differential signal line comprises 21 passages, and each passage comprises 24Bit. The present invention extends to 252 by port number by original 16, can realize like this transfer of data of high-speed and high-efficiency, meets the user demand of various large-scale application scenarios; Under the prerequisite that takies less resource, realize FS inspection and CRC check simultaneously, ensured the reliability of product.
Description
Technical field
The present invention relates to Audio Signal Processing technical field, relate in particular to a kind of efficient unlimited digital sound consoleCluster and method for transmitting signals thereof.
Background technology
Universal along with digital media applications, from the language interview recording of going out, to the making of program, layout,Broadcast, and the digitlization of turn-key system, automation, progressively realize to digital medium technique transition.Collection, processing and the broadcast of whole signal are all to exist with digital audio format, particularly with audio workstationDigital Media greatly facilitate editor and the control to audio material, audio workstation system becomesBroadcasting station audio frequency is made the main number media device broadcasting. Another nucleus equipment that program making is broadcastedBe sound console, sound console is the switching centre that program making is broadcasted, and it is connecting simulation number miscellaneousWord input-output equipment, converges the audio signal of various device, distribute and realize various signalsInput and output control.
At present, digital sound console carrys out extended audio I/O channel number by cascade system. As Fig. 3 and TuShown in 5, set up FPGA unit in digital sound console, this FPGA unit has digital audio and video signalsPacking/unpacking/synchronizing function, multiple like this digital sound consoles are unit cascaded by FPGA, can pass through FPGATransmitted in both directions multi-path digital audio signal between two digital sound consoles is realized in unit; Also multiple numerals can be adjustedSound platform is connected with a switch device respectively, realizes the forwarding of digital audio and video signals by switch device.
Be cascaded as example with two digital sound consoles, under above-mentioned cascade system, digital sound console 1 is adjusted with numeralAs shown in Figure 1, transmission interface X1 and the FPGA of FPGA unit 1 are mono-for connected mode between sound platform 2Between the receiving interface R2 of unit 2, there are 4 groups of differential signal lines, respectively in order to transmit CLK signal, FSSignal (frame synchronization clock signal), DX signal (transmission data-signal), blank; FPGA unit 1Receiving interface R1 and the transmission interface X2 of FPGA unit 2 between also there are 4 groups of differential signal lines, pointNot for transmit CLK signal, FS signal (frame synchronization clock signal), DR signal (reception data-signal),Blank. Wherein, the clock frequency of CLK signal is 24.56MHZ, is low-speed clock signal, has limited everyThe transmission speed of frame data; In signals transmission, the data channel number of each FPGA unit is 16,Each passage is 32Bit, and wherein only 24Bit is employed conventionally, and 8Bit does not use, and this has just caused bandwidthThe waste of resource. And in the application scenario of various large-scale sound program recordings, to available data channel number, dataTransfer rate has more and more higher demand, thereby is necessary to make improvements.
Summary of the invention
The object of the present invention is to provide a kind of efficient unlimited digital sound console cluster and side signal transmission thereofMethod, realizes the cluster of the digital sound console of unlimited amount, increases the data transmission channel between digital sound console,Improve the message transmission rate between digital sound console.
The object of the invention is to be achieved through the following technical solutions:
An efficient unlimited digital sound console cluster, comprises N digital sound console;
Each digital sound console comprises the DSP unit and the FPGA unit that are connected, each digital sound console itBetween by FPGA unit cascaded;
Described DSP unit, for receiving simulated audio signal, by the each railway digital obtaining after its analog-to-digital conversionAudio signal is issued to the FPGA unit of local terminal together with default signal forward-path information; Receive local terminalThe digital audio and video signals that FPGA unit reports, enters this digital audio and video signals and described simulated audio signalThe processing of line correlation audio frequency, controls output afterwards;
Described FPGA unit, the digital audio and video signals issuing for receiving local terminal DSP unit, will be wherein oneAfter road or digital audio and video signals more than road packing, being forwarded to next stage numeral according to signal forward-path adjustsSound platform; In the time of the digital audio and video signals receiving from upper level digital sound console, judge whether local terminal is orderGround, after if so, being unpacked, report to the DSP unit of local terminal, otherwise forward it to next progressionWord sound console;
Described FPGA unit comprises transmission interface and receiving interface; The FPGA of described transmission interface and opposite endThe receiving interface of unit connects by 4 groups of differential signal lines, and wherein one group of differential signal line is for transmitting high speedClock signal (HCLK signal), three groups of differential signal lines are used for transmitting transmission data-signal (DX signal);Described receiving interface is connected by 4 groups of differential signal lines with the transmission interface of the FPGA unit of opposite end, whereinOne group of differential signal line is used for transmitting HCLK signal, three groups of differential signal lines for transmitting reception data-signal(DR signal); Every group of differential signal line comprises 21 data channel, and each data channel comprises 24BitData;
Described FPGA unit, also for by three groups of differential signals for transmitting DX signal/DR signalIn line the 32Bit remaining bandwidth of one group of differential signal line fill in frame synchronization clock (FS) detected value, anotherThe 32Bit remaining bandwidth of group differential signal line is filled in CRC check value;
The value of described N is not more than 17; The clock frequency of described HCLK signal is 98.034MHZ.
Wherein, whether described FPGA unit, also fall for detecting in real time the digital sound console being connected with local terminalElectricity passes through digital signal line transmission voltage modulation signal to opposite end in the time power down being detected.
An efficient unlimited digital sound console cluster, comprises N digital sound console; Also comprise that switch establishesStandby;
Each digital sound console comprises the DSP unit and the FPGA unit that are connected, and described switch is establishedStandby the 2nd FPGA unit that comprises, each digital sound console is respectively by FPGA unit and a switch deviceThe 2nd FPGA unit be connected;
Described DSP unit, for receiving the analogue audio frequency letter of inputting by audio input interface in outer signals sourceNumber, by the each railway digital audio signal obtaining after its analog-to-digital conversion together with under default signal forward-path informationSend to a FPGA unit; Receive the digital audio and video signals that a FPGA unit reports, to this numeral soundFrequently signal and described simulated audio signal carry out related audio processing, control afterwards output;
A described FPGA unit, the digital audio and video signals issuing for receiving DSP unit, will be wherein oneAfter road or digital audio and video signals more than road packing, be forwarded to switch device together with signal forward-path;In the time receiving the digital audio and video signals of switch device, after being unpacked, report to the DSP unit of local terminal;
Described the 2nd FPGA unit, for receiving digital audio and video signals and the signal from each digital sound consoleForward-path information, is forwarded to designation number sound console according to this signal forward-path by digital audio and video signalsThe one FPGA unit;
A described FPGA unit and the 2nd FPGA unit include transmission interface and receiving interface; DescribedTransmission interface is connected by 4 groups of differential signal lines with the receiving interface of the FPGA unit of opposite end, wherein one groupDifferential signal line is used for transmitting HCLK signal, three groups of differential signal lines for transmitting DX signal; Described connecingReceive interface be connected by 4 groups of differential signal lines with the transmission interface of the FPGA unit of opposite end, wherein one group poorSub-signal line is used for transmitting HCLK signal, three groups of differential signal lines for transmitting DR signal; Every group of differenceHolding wire comprises 21 data channel, and each data channel comprises 24Bit data;
A described FPGA unit and the 2nd FPGA unit, also for by for transmitting DX signal/DRIn three groups of differential signal lines of signal the 32Bit remaining bandwidth of one group of differential signal line fill in FS detected value,The 32Bit remaining bandwidth of another group differential signal line is filled in CRC check value;
The value of described N is not more than 16; The clock frequency of described HCLK signal is 98.034MHZ.
Whether the switch device that wherein, a described FPGA unit is also connected with local terminal for real-time detectionPower down is passed through digital signal line transmission voltage modulation signal to opposite end in the time power down being detected;
Described the 2nd FPGA unit is also for detecting in real time the whether power down of the digital sound console that is connected with local terminal,In the time power down being detected, pass through digital signal line transmission voltage modulation signal to opposite end.
A method for transmitting signals for digital sound console cluster described above, sends in this digital sound console clusterThe method for transmitting signals of the FPGA unit of end and the FPGA unit of receiving terminal comprises:
Data transmission procedure: by the FPGA unit of the transmission interface of the FPGA unit of transmitting terminal and receiving terminalReceiving interface connect by 4 groups of differential signal lines, utilize wherein one group of differential signal line transmission HCLK letterNumber, utilize other three groups of differential signal lines transmission DX signal, and every group of differential signal line comprises 21 dataPassage, each data channel comprises 24Bit data.
DRP data reception process: by the FPGA unit of the receiving interface of the FPGA unit of transmitting terminal and receiving terminalTransmission interface connect by 4 groups of differential signal lines, utilize wherein one group of differential signal line transmission HCLK letterNumber, utilize other three groups of differential signal lines transmission DR signal, and every group of differential signal line comprises 21 dataPassage, each data channel comprises 24Bit data;
Described FPGA unit also carries out FS detection and CRC check operation, and by believing for transmitting DXNumber/three groups of differential signal lines of DR signal in the 32Bit remaining bandwidth of one group of differential signal line fill in FSThe 32Bit remaining bandwidth of detected value, another group differential signal line is filled in CRC check value.
Compared with prior art, the embodiment of the present invention has following beneficial effect:
1), in the embodiment of the present invention, the untapped 8Bit of every passage in prior art is effectively utilized,Thereby it is (complete that the 16CH of original 32Bit/CH (8Bit/CH does not wherein use) is transformed to 24Bit/CHPortion use) 21CH; Meanwhile, will all use for the holding wire and the NC holding wire that transmit FS signal beforeIn transmission DX signal, thereby make the differential signal line that transmits DX signal be increased to three by one; SeparatelyThe double frequency function that also utilizes FPGA unit itself to have outward promotes 4 by clock signal by 24.576MHZDoubly, reach 98.034MHZ, become at a high speed from low speed. So, port number is expanded by initial 16CHTo 21CH × 3 × 4=252CH, can realize like this transfer of data of high-speed and high-efficiency, meet various large-scale answeringWith the user demand of occasion.
2) adopt after the present invention, every group of differential signal line is available in a FS signal period98.034MHZ/48kHz=2048Bit, if transmission 84CH, the bandwidth needing is 84CH × 24Bit/CH=2016Bit, every group of differential signal line remaining bandwidth in each FS signal period is 32Bit. Thereby the present invention makesPlace FS test value, use another differential signal line with the residue 32Bit of a differential signal line whereinResidue 32Bit place CRC check value, can under the prerequisite that takies less resource, realize so simultaneouslyFS checks and CRC check, has ensured the reliability of product.
3) based on having advantages of high-speed and high-efficiency, maximum can realize the cluster of 17 digital sound consoles, greatlyMeet market user demand, had larger market application foreground.
Brief description of the drawings
Fig. 1 is the connection diagram of the digital sound console of two cascades of prior art employing.
Fig. 2 is the connection diagram of the digital sound console of two cascades adopting in the embodiment of the present invention.
Fig. 3 is the schematic diagram of a kind of cascade system of digital sound console in the embodiment of the present invention.
Fig. 4 is the digital audio communication method flow diagram of the cluster of digital sound console shown in Fig. 3.
Fig. 5 is the schematic diagram of the another kind of cascade system of digital sound console in the embodiment of the present invention.
Fig. 6 is the system architecture diagram of the cluster that is made up of n platform digital sound console in the embodiment of the present invention.
Detailed description of the invention
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and realityExecute example, the present invention is further elaborated. Only should be appreciated that specific embodiment described hereinOnly, in order to explain the present invention, be not intended to limit the present invention.
In the present embodiment, the implementation of digital sound console cluster has two kinds, will introduce respectively below.
The first cascade system refers to Fig. 3. This cluster comprise digital sound console 1, digital sound console 2,Digital sound console 3. In the time of cascade, the FPGA unit 1 of digital sound console 1 and the FPGA of digital sound console 2Unit 2 connects, and the FPGA unit 2 of digital sound console 2 connects with the FPGA unit of digital sound console 33Connect. Digital sound console 1, digital sound console 2, digital sound console 3 include following part: DSPUnit, FPGA unit, power module.
Wherein, DSP unit, for receiving the received analogue audio frequency letter of each audio input interface of local terminalNumber, the each railway digital audio signal obtaining after its analog-to-digital conversion is issued with default signal forward-path informationTo FPGA unit; Receive the digital audio and video signals that FPGA unit sends, connect in conjunction with the input of local terminal audio frequencyThe simulated audio signal that mouth is received, carries out controlling the output of local terminal appointment audio output interface after various processing;
FPGA unit, the digital audio and video signals sending for receiving DSP unit, is packed after processingBe forwarded to designation number sound console according to signal forward-path; At the number receiving from other digital sound consolesWhen word audio signal, judge whether local terminal is destination, if so, this digital audio and video signals is reported to thisThe DSP unit of end, otherwise forward it to next stage digital sound console.
As shown in Figure 4, the process of said system sound intermediate frequency signal forward process is:
401, according to current user demand, difference preset signals forward-path in each digital sound console.
402, at each digital sound console end, the simulated audio signal that the audio input interface of local terminal is received entersRow analog-to-digital conversion process, is sent to each railway digital audio signal after treatment the FPGA unit of local terminal.
403, Yi road or multi-path digital audio frequency letter will wherein be specified according to signal forward-path in FPGA unitNumber packing be sent to next stage digital sound console together with signal forward-path information.
404, the FPGA unit of next stage digital sound console is received after digital audio and video signals, according to wherein carryingSignal forward-path information judge that whether local terminal is that signal forwards destination, if so, believes DABNumber unpack after processing and report to the DSP unit of local terminal, otherwise forward it to next stage digital sound console, straightTo being forwarded to destination.
405, at each digital sound console end, DSP unit reports FPGA unit according to default ruleDigital audio and video signals and local terminal audio input interface receive simulated audio signal carry out respective handling, controlThe audio output interface of local terminal processed is exported each road simulated audio signal.
The second implementation refers to Fig. 5. Multiple digital sound consoles also can be by handing over except cascade systemThe equipment of changing planes is realized communication. Its voice communication process is: difference preset signals in each digital sound consoleForward-path; Each digital sound console is believed digital audio and video signals by FPGA unit together with signal forward-pathBreath is forwarded to switch device, and switch device is forwarded to digital audio and video signals according to signal forward-path againThe digital sound console of specifying. This process is also to have applied the digital audio and video signals forward process merit of FPGA unitEnergy.
Which kind of in the present embodiment, no matter adopt above-mentioned implementation, in digital sound console cluster, be connectedBetween digital sound console or between digital sound console and switch device, all adopt following data transmission method:
As shown in Figure 2, be only described as an example of two digital sound consoles being connected example herein. Numeral tuningThe FPGA unit 1 of platform 1 comprises transmission interface X1 and receiving interface R1, the FPGA of digital sound console 2Unit 2 comprises transmission interface X2 and receiving interface R2.
Transmission interface X1 is connected with receiving interface R2 by 4 groups of differential signal lines. These 4 groups of differential signal linesIn, one group is used for transmitting HCLK signal (high-speed clock signal), and its clock frequency is 98.034MHZ,Compared with the CLK signal that is 24.56MHZ with the clock frequency of transmitting in prior art, frequency is increased to 4 times;Other three groups of differential signal lines are all used for transmitting DX signal (transmission data-signal), compared with prior art,The FS signal (frame synchronization clock signal) of one group of differential signal line transmission is replaced with to DX signal, adopt simultaneouslyTransmit DX signal with untapped one group of differential signal line. Like this, just there are three groups of differential signal lines specialIn transmission DX signal, be compared with prior art increased to 3 times.
Corresponding therewith, receiving interface R1 is connected with transmission interface X2 by 4 groups of differential signal lines. These 4 groupsIn differential signal line, one group is used for transmitting HCLK signal (high-speed clock signal), and its clock frequency is98.034MHZ, compared with the CLK signal that is 24.56MHZ with the clock frequency of transmitting in prior art frequentlyRate is increased to 4 times; Other three groups of differential signal lines are all used for transmitting DR signal (reception data-signal),Compared with prior art, the FS signal (frame synchronization clock signal) of one group of differential signal line transmission is replacedFor DX signal, adopt untapped one group of differential signal line to transmit DR signal simultaneously.
In the present embodiment, for further realizing high-speed and high-efficiency, to the untapped 8Bit of every passage in prior artEffectively utilize, by original 32Bit/CH (8Bit/CH does not wherein use, and has used 24Bit/CH)16CH be transformed to the 21CH of 24Bit/CH (all use).
Now, the data available port number between digital sound console 1 and digital sound console 2 is by initial 16CHExtend to 21CH × 3 × 4=252CH, can realize like this transfer of data of high-speed and high-efficiency, meet various largeThe user demand of type application scenario.
In order to realize at a high speed, in said process, one group of differential signal line of transmission FS signal will be exclusively used in originallyCancel transmission FS signal, then transmission DX signal/DR signal. Thereby, now can for what ensure productBy property, very important FS detects and CRC inspection, and the present embodiment adopts following methods to recover FS and detectsCheck with CRC:
Adopt after the present invention, every group of differential signal line is available in a FS signal period98.034MHZ/48kHz=2048Bit, if transmission 84CH, the bandwidth needing is 84CH × 24Bit/CH=2016Bit, every group of differential signal line remaining bandwidth in each FS signal period is 32Bit. Thereby, the present embodimentFrom 3 groups of differential signal lines for transmitting DX signal/DR signal, choose at random one group of differential signal lineAnd use its residue 32Bit to place FS test value, select one group of differential signal line and use its residue 32BitPlace CRC check value, can under the prerequisite that takies less resource, realize like this FS inspection and CRC simultaneouslyVerification, has ensured the reliability of product.
The cluster being formed by n digital sound console as shown in Figure 6, wherein, each digital sound console itselfThere is the data-handling capacity of 16 passages, there is again 252 passages and other digital sound console numbersReportedly defeated. In actual applications, the quantity of the digital sound console of composition cluster can be up to 17, greatly fullFoot user's user demand.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, not all at thisAny amendment of doing within bright spirit and principle, be equal to and replace and improvement etc., all should be included in the present inventionProtection domain within.
Claims (5)
1. an efficient unlimited digital sound console cluster, comprises N digital sound console; It is characterized in that,
Each digital sound console comprises the DSP unit and the FPGA unit that are connected, between each digital sound consoleUnit cascaded by FPGA;
Described DSP unit, for receiving simulated audio signal, by the each way word tone obtaining after its analog-to-digital conversionFrequently signal is issued to the FPGA unit of local terminal together with default signal forward-path information; Receive local terminal FPGAThe digital audio and video signals that unit reports, to this digital audio and video signals and the described simulated audio signal sound of being correlated withFrequently process, control afterwards output;
Described FPGA unit, the digital audio and video signals issuing for receiving local terminal DSP unit, a wherein roadOr be forwarded to the tuning of next stage numeral according to signal forward-path after digital audio and video signals packing more than a roadPlatform; In the time of the digital audio and video signals receiving from upper level digital sound console, judge whether local terminal is destination,If so, after being unpacked, report to the DSP unit of local terminal, otherwise forward it to next stage digital sound console;
Described FPGA unit comprises transmission interface and receiving interface; The FPGA of described transmission interface and opposite end is mono-The receiving interface of unit connects by 4 groups of differential signal lines, and wherein one group of differential signal line is for transmitting high speed clockHCLK signal, three groups of differential signal lines are used for transmitting transmission data DX signal; Described receiving interface and opposite endThe transmission interface of FPGA unit connect by 4 groups of differential signal lines, wherein one group of differential signal line is for transmissionHCLK signal, three groups of differential signal lines are used for transmitting reception data DR signal; Every group of differential signal line comprises21 data channel, each data channel comprises 24Bit data;
Described FPGA unit, also for by three groups of differential signal lines for transmitting DX signal/DR signal32Bit remaining bandwidth in each frame synchronization clock FS signal period of one group of differential signal line is filled in FS inspection32Bit remaining bandwidth in each FS signal period of measured value, another group differential signal line is filled in CRC checkValue; The value of described N is not more than 17; The clock frequency of described HCLK signal is 98.034MHZ.
2. efficient unlimited digital sound console cluster as claimed in claim 1, is characterized in that described FPGAUnit also, for detecting in real time the whether power down of the digital sound console that is connected with local terminal, passes through in the time power down being detectedDigital signal line transmission voltage modulation signal is to opposite end.
3. an efficient unlimited digital sound console cluster, comprises N digital sound console; It is characterized in that,Also comprise switch device;
Each digital sound console comprises the DSP unit and the FPGA unit that are connected, described switch deviceComprise the 2nd FPGA unit, each digital sound console is respectively by the of a FPGA unit and switch deviceTwo FPGA unit are connected;
Described DSP unit, the simulated audio signal of inputting by audio input interface for receiving outer signals source,The each railway digital audio signal obtaining after its analog-to-digital conversion is issued to together with default signal forward-path informationThe one FPGA unit; Receive the digital audio and video signals that a FPGA unit reports, to this digital audio and video signalsAnd described simulated audio signal carries out related audio processing, control output afterwards;
A described FPGA unit, the digital audio and video signals issuing for receiving DSP unit, a wherein roadOr be forwarded to switch device together with signal forward-path after digital audio and video signals packing more than a road; ConnecingWhile receiving the digital audio and video signals of switch device, after being unpacked, report to the DSP unit of local terminal;
Described the 2nd FPGA unit, turns for receiving from digital audio and video signals and the signal of each digital sound consoleSend out routing information, according to this signal forward-path, digital audio and video signals is forwarded to first of designation number sound consoleFPGA unit;
A described FPGA unit and the 2nd FPGA unit include transmission interface and receiving interface; DescribedSend interface to be connected by 4 groups of differential signal lines with the receiving interface of the FPGA unit of opposite end, wherein one group of difference letterNumber line is used for transmitting for transmitting high speed clock HCLK signal, three groups of differential signal lines and sends data DX signal;Described receiving interface is connected by 4 groups of differential signal lines with the transmission interface of the FPGA unit of opposite end, wherein one groupDifferential signal line is used for transmitting HCLK signal, three groups of differential signal lines receive data DR signal for transmitting;Every group of differential signal line comprises 21 data channel, and each data channel comprises 24Bit data;
A described FPGA unit and the 2nd FPGA unit, also for by for transmitting DX signal/DR letterNumber three groups of differential signal lines in 32Bit in each frame synchronization clock FS signal period of one group of differential signal lineRemaining bandwidth is filled in the 32Bit residue in each FS signal period of FS detected value, another group differential signal lineBandwidth is filled in CRC check value; The value of described N is not more than 16; The clock frequency of described HCLK signal is98.034MHZ。
4. efficient unlimited digital sound console cluster as claimed in claim 3, is characterized in that described firstFPGA unit is also for detecting in real time the whether power down of the switch device that is connected with local terminal, in the time power down being detectedBy digital signal line transmission voltage modulation signal to opposite end;
Described the 2nd FPGA unit is also for detecting in real time the whether power down of the digital sound console that is connected with local terminal,When power down detected, pass through digital signal line transmission voltage modulation signal to opposite end.
5. a method for transmitting signals for digital sound console cluster as described in claim 1 or 3, is characterized in that,The method for transmitting signals of the FPGA unit of transmitting terminal and the FPGA unit of receiving terminal in this digital sound console clusterComprise:
Data transmission procedure: by the FPGA unit of the transmission interface of the FPGA unit of transmitting terminal and receiving terminalReceiving interface connects by 4 groups of differential signal lines, utilizes wherein one group of differential signal line transmitting high speed clockHCLK signal, utilize other three groups of differential signal lines transmission to send data DX signal, and every group of differential signalLine comprises 21 data channel, and each data channel comprises 24Bit data;
DRP data reception process: by the FPGA unit of the receiving interface of the FPGA unit of transmitting terminal and receiving terminalTransmission interface connects by 4 groups of differential signal lines, utilize wherein one group of differential signal line transmission HCLK signal,Utilize other three groups of differential signal lines transmission to receive data DR signal, and every group of differential signal line comprise 21 numbersAccording to passage, each data channel comprises 24Bit data;
Described FPGA unit also carries out frame synchronization clock FS detection and CRC check operation, and passes through for transmissionIn three groups of differential signal lines of DX signal/DR signal in each FS signal period of one group of differential signal line 32Bit remaining bandwidth fill in FS detected value, another group differential signal line each FS signal period in 32BitRemaining bandwidth is filled in CRC check value.
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