CN103166818A - High-efficiency limitless digital sound console cluster and signal transmission method thereof - Google Patents
High-efficiency limitless digital sound console cluster and signal transmission method thereof Download PDFInfo
- Publication number
- CN103166818A CN103166818A CN2013100598970A CN201310059897A CN103166818A CN 103166818 A CN103166818 A CN 103166818A CN 2013100598970 A CN2013100598970 A CN 2013100598970A CN 201310059897 A CN201310059897 A CN 201310059897A CN 103166818 A CN103166818 A CN 103166818A
- Authority
- CN
- China
- Prior art keywords
- differential signal
- signal
- fpga unit
- sound console
- digital sound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The invention provides a high-efficiency limitless digital sound console cluster and a signal transmission method thereof. The cluster comprises digital sound consoles with the number of N, the digital sound consoles are in cascade connection with one another through a field programmable gate array (FPGA) unit, or respectively connected with an FPGA of switch equipment, a sending interface of the FPGA unit is connected with a receiving interface of the opposite end through four groups of differential signal lines, one group of differential signal lines is used for transmitting high-speed clock (HCLK) signals, the other three groups of differential signal lines are used for transmitting DX signals, the receiving interface is connected with the sending interface of the opposite end through four groups of differential signal lines, one group of differential signal lines is used for transmitting HCLK signals, the other three groups are used for transmitting DR signals, each group of differential signal lines comprises 21 channels, and each channel includes 24 bit. According to the high-efficiency limitless digital sound console cluster and the signal transmission method thereof, the number of the channels is increased from 16 to 252, so that high-speed high-efficiency data transmission can be achieved, and usage requirements in various large application situations are met. In addition, on the premise that resource occupancy is less, a factor of safety (FS) test and a cyclic redundancy check (CRC) can be achieved at the same time, and reliability of the products are guaranteed.
Description
Technical field
The present invention relates to the Audio Signal Processing technical field, relate in particular to a kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof.
Background technology
Universal along with digital media applications, from the language interview recording of going out, to making, layout, the broadcast of program, and the digitlization of turn-key system, automation, progressively realized to digital medium technique transition.The collection of whole signal, processing and broadcast are all to exist with digital audio format, particularly greatly facilitate editor and control to audio material with the Digital Media of audio workstation, audio workstation system has become the broadcasting station audio frequency and has made the main number media device that broadcasts.Another nucleus equipment that program making is broadcasted is sound console, sound console is the switching center that program making is broadcasted, it is connecting analog digital input-output equipment miscellaneous, the audio signal of various device is converged, distributes and realizes the input and output control of various signals.
At present, digital sound console comes extended audio I/O channel number by cascade system.As shown in Figure 3 and Figure 5, set up the FPGA unit in digital sound console, this FPGA unit has the packing/unpacking/synchronizing function of digital audio and video signals, a plurality of like this digital sound consoles are unit cascaded by FPGA, can realize transmitted in both directions multi-path digital audio signal between two digital sound consoles by the FPGA unit; Also a plurality of digital sound consoles can be connected with a switch device respectively, realize the forwarding of digital audio and video signals by switch device.
Be cascaded as example with two digital sound consoles, under above-mentioned cascade system, connected mode between digital sound console 1 and digital sound console 2 as shown in Figure 1, have 4 groups of differential signal lines between the receiving interface R2 of the transmission interface X1 of FPGA unit 1 and FPGA unit 2, respectively in order to transmit CLK signal, FS signal (frame synchronization clock signal), DX signal (transmission data-signal), blank; Also have 4 groups of differential signal lines between the transmission interface X2 of the receiving interface R1 of FPGA unit 1 and FPGA unit 2, be respectively used to transmit CLK signal, FS signal (frame synchronization clock signal), DR signal (reception of data signal), blank.Wherein, the clock frequency of CLK signal is 24.56MHZ, is low-speed clock signal, has limited the transmission speed of every frame data; In signals transmission, the data channel number of each FPGA unit is 16, and each passage is 32Bit, usually wherein only 24 Bit be employed, 8 Bit do not use, this has just caused the waste of bandwidth resources.And in the application scenario of various large-scale sound program recordings, available data channel number, message transmission rate are had more and more higher demand, thereby be necessary to make improvements.
Summary of the invention
The object of the present invention is to provide a kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof, realize the cluster of the digital sound console of unlimited amount, increase the data transmission channel between digital sound console, improve the message transmission rate between digital sound console.
The objective of the invention is to be achieved through the following technical solutions:
A kind of efficient unlimited digital sound console cluster comprises N digital sound console;
Each digital sound console comprises the DSP unit that is connected and FPGA unit, and is unit cascaded by FPGA between each digital sound console;
Described DSP unit is used for receiving simulated audio signal, and each railway digital audio signal that obtains after its analog-to-digital conversion is issued to the FPGA unit of local terminal together with default signal forward-path information; The digital audio and video signals of sending out on reception local terminal FPGA unit carries out the related audio processing to this digital audio and video signals and described simulated audio signal, controls afterwards output;
Described FPGA unit be used for to receive the digital audio and video signals that local terminal DSP unit issues, and wherein is forwarded to the next stage digital sound console according to the signal forward-path after the packing of the digital audio and video signals more than a tunnel or a tunnel; When the digital audio and video signals that receives from the upper level digital sound console, judge whether local terminal is the destination, if report to the DSP unit of local terminal after it being unpacked, otherwise forward it to the next stage digital sound console;
Described FPGA unit comprises transmission interface and receiving interface; The receiving interface of the FPGA unit of described transmission interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for transmission DX signal; The transmission interface of the FPGA unit of described receiving interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for the transmission DR signal; Every group of differential signal line comprises 21 data passages, and each data channel comprises 24Bit.
Wherein, described FPGA unit also is used for filling in the CRC check value by 32 Bit remaining bandwidths of filling in FS detected value, another group differential signal line for 32 Bit remaining bandwidths of the one group of differential signal line of three groups of differential signal lines that transmits DX signal/DR signal.
Wherein, the value of described N is not more than 17; The clock frequency of described HCLK signal is 98.034MHZ.
Wherein, described FPGA unit also is used for detecting in real time the whether power down of the digital sound console that is connected with local terminal, passes through digital signal line transmission voltage modulation signal to the opposite end when power down being detected.
A kind of efficient unlimited digital sound console cluster comprises N digital sound console and switch device;
Each digital sound console comprises the DSP unit that is connected and a FPGA unit, and described switch device comprises the 2nd FPGA unit, and each digital sound console is connected by the 2nd FPGA unit of a FPGA unit and switch device respectively;
Described DSP unit be used for to receive the simulated audio signal that the outer signals source input by audio input interface, and each railway digital audio signal of obtaining after its analog-to-digital conversion is issued to a FPGA unit together with the signal forward-path information of presetting; Receive the digital audio and video signals of sending out on a FPGA unit, this digital audio and video signals and described simulated audio signal are carried out related audio process, control afterwards output;
A described FPGA unit is used for receiving the digital audio and video signals that the DSP unit issues, and wherein is forwarded to switch device together with the signal forward-path after the packing of the digital audio and video signals more than a tunnel or a tunnel; When receiving the digital audio and video signals of switch device, after being unpacked, it reports to the DSP unit of local terminal;
Described the 2nd FPGA unit is used for receiving digital audio and video signals and signal forward-path information from each digital sound console, according to this signal forward-path, digital audio and video signals is forwarded to a FPGA unit of designation number sound console;
A described FPGA unit and the 2nd FPGA unit include transmission interface and receiving interface; The receiving interface of the FPGA unit of described transmission interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for transmission DX signal; The transmission interface of the FPGA unit of described receiving interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for the transmission DR signal; Every group of differential signal line comprises 21 data passages, and each data channel comprises 24Bit.
Wherein, a described FPGA unit and the 2nd FPGA unit, the 32 Bit remaining bandwidths that also are used for the one group of differential signal line of three groups of differential signal lines by being used for transmission DX signal/DR signal are filled in the FS detected value, another 32 Bit remaining bandwidths of organizing differential signal line are filled in the CRC check value.
Wherein, the value of described N is not more than 16; The clock frequency of described HCLK signal is 98.034MHZ.
Wherein, a described FPGA unit and the 2nd FPGA unit also are used for detecting in real time the whether power down of switch device/digital sound console of being connected with local terminal, pass through digital signal line transmission voltage modulation signal to the opposite end when power down being detected.
A kind of method for transmitting signals of the cluster of digital sound console as mentioned above, in this digital sound console cluster, the method for transmitting signals of the FPGA unit of the FPGA unit of transmitting terminal and receiving terminal comprises:
Data transmission procedure: the receiving interface of the FPGA unit of the transmission interface of the FPGA unit of transmitting terminal and receiving terminal is connected by 4 groups of differential signal lines, utilizing wherein, one group of differential signal line transmits the HCLK signal, utilizes other three groups of differential signal lines transmission DX signal, and every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data.
DRP data reception process: the transmission interface of the FPGA unit of the receiving interface of the FPGA unit of transmitting terminal and receiving terminal is connected by 4 groups of differential signal lines, utilizing wherein, one group of differential signal line transmits the HCLK signal, utilizes other three groups of differential signal lines transmission DR signal, and every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data.
Wherein, described FPGA unit also carries out FS detection and CRC check operation, and fills in the CRC check value by 32 Bit remaining bandwidths of filling in FS detected value, another group differential signal line for 32 Bit remaining bandwidths of the one group of differential signal line of three groups of differential signal lines that transmits DX signal/DR signal.
Compared with prior art, the embodiment of the present invention has following beneficial effect:
1) in the embodiment of the present invention, untapped 8 Bit effectively utilize to every passage in prior art, thereby original 32Bit/CH(8Bit/CH is not wherein used) 16CH be transformed to 24Bit/CH(and all use) 21CH; Simultaneously, holding wire and the NC holding wire that is used for before transmission FS signal all is used for transmission DX signal, thereby makes the differential signal line that transmits the DX signal increase to three by one; Also utilize in addition the double frequency function that FPGA unit itself has that clock signal is promoted 4 times by 24.576MHZ, reach 98.034MHZ, become at a high speed by low speed.So, port number is extended to 21CH * 3 * 4=252CH by initial 16CH, can realize like this transfer of data of high-speed and high-efficiency, satisfy the user demand of various large-scale application scenarios.
2) after employing the present invention, every group of differential signal line is at a FS available 98.034MHZ/48kHz=2048Bit in the signal period, if transmission 84CH, the bandwidth that needs is 84CH * 24Bit/CH=2016 Bit, every group of differential signal line each FS in the signal period remaining bandwidth be 32Bit.Thereby, the present invention uses wherein, and residue 32 Bit of a differential signal line place the FS test value, use residue 32 Bit of another differential signal line to place the CRC check value, can realize simultaneously FS check and CRC check under the prerequisite of less resource taking like this, guarantee the reliability of product.
3) based on having advantages of high-speed and high-efficiency, maximum can realize the cluster of 17 digital sound consoles, has greatly satisfied the market user demand, and larger market application foreground is arranged.
Description of drawings
Fig. 1 is the connection diagram of the digital sound console of two cascades adopting of prior art.
Fig. 2 is the connection diagram of the digital sound console of two cascades adopting in the embodiment of the present invention.
Fig. 3 is the schematic diagram of a kind of cascade system of digital sound console in the embodiment of the present invention.
Fig. 4 is the digital audio communication method flow diagram of digital sound console cluster shown in Figure 3.
Fig. 5 is the schematic diagram of the another kind of cascade system of digital sound console in the embodiment of the present invention.
Fig. 6 is the system architecture diagram of the cluster that is comprised of n platform digital sound console in the embodiment of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
In the present embodiment, the implementation of digital sound console cluster has two kinds, and the below will introduce respectively.
The first cascade system sees also Fig. 3.This cluster comprises digital sound console 1, digital sound console 2, digital sound console 3.When cascade, the FPGA unit 2 of the FPGA unit 1 of digital sound console 1 and digital sound console 2 is connected, and the FPGA unit 3 of the FPGA unit 2 of digital sound console 2 and digital sound console 3 is connected.Digital sound console 1, digital sound console 2, digital sound console 3 include following part: DSP unit, FPGA unit, power module.
Wherein, the DSP unit is used for receiving the received simulated audio signal of each audio input interface of local terminal, and each railway digital audio signal that obtains after its analog-to-digital conversion is issued to the FPGA unit with default signal forward-path information; The digital audio and video signals that reception FPGA sends the unit in conjunction with the received simulated audio signal of local terminal audio input interface, carries out controlling the output of local terminal appointment audio output interface after various processing;
The FPGA unit be used for to receive the digital audio and video signals that the DSP unit sends, and be forwarded to the designation number sound console according to the signal forward-path after will its packing processing; When the digital audio and video signals that receives from other digital sound consoles, judge whether local terminal is the destination, if this digital audio and video signals is reported to the DSP unit of local terminal, otherwise forward it to the next stage digital sound console.
As shown in Figure 4, the process of said system sound intermediate frequency signal forward process is:
401, according to current user demand, difference preset signals forward-path in each digital sound console.
402, at each digital sound console end, the simulated audio signal that the audio input interface of local terminal is received carries out analog-to-digital conversion process, each railway digital audio signal after processing is sent to the FPGA unit of local terminal.
403, the FPGA unit according to the signal forward-path wherein appointment a road or multi-path digital audio signal the packing be sent to the next stage digital sound console together with signal forward-path information.
404, after digital audio and video signals is received in the FPGA unit of next stage digital sound console, judge according to the signal forward-path information of wherein carrying whether local terminal is that signal forwards the destination, if, digital audio and video signals is unpacked and report to the DSP unit of local terminal after processing, otherwise forward it to the next stage digital sound console, until be forwarded to the destination.
405, at each digital sound console end, the simulated audio signal that the digital audio and video signals that the DSP unit reports the FPGA unit according to default rule and local terminal audio input interface receive carries out respective handling, controls the audio output interface of local terminal and exports each road simulated audio signal.
The second implementation sees also Fig. 5.A plurality of digital sound consoles also can be realized communication by switch device except cascade system.Its voice communication process is: difference preset signals forward-path in each digital sound console; Each digital sound console is forwarded to switch device with digital audio and video signals together with signal forward-path information by the FPGA unit, and switch device is forwarded to digital audio and video signals according to the signal forward-path digital sound console of appointment again.This process is also to have used the digital audio and video signals forward process function of FPGA unit.
In the present embodiment, no matter adopt above-mentioned which kind of implementation, in the digital sound console cluster, between the digital sound console that is connected or between digital sound console and switch device, all adopt following data transmission method:
As shown in Figure 2, only be described as an example of two digital sound consoles being connected example herein.The FPGA unit 1 of digital sound console 1 comprises transmission interface X1 and receiving interface R1, and the FPGA unit 2 of digital sound console 2 comprises transmission interface X2 and receiving interface R2.
Transmission interface X1 is connected with receiving interface R2 by 4 groups of differential signal lines.In these 4 groups of differential signal lines, one group is used for transmission HCLK signal (high-speed clock signal), and its clock frequency is 98.034MHZ, compares frequency with the clock frequency of transmitting in the prior art CLK signal that is 24.56MHZ and is increased to 4 times; Other three groups of differential signal lines all are used for transmitting DX signal (transmission data-signal), compared with prior art, the FS signal (frame synchronization clock signal) of one group of differential signal line transmission is replaced with the DX signal, adopt simultaneously untapped one group of differential signal line to transmit the DX signal.Like this, just there are three groups of differential signal lines to be exclusively used in transmission DX signal, compared with prior art increase to 3 times.
Corresponding therewith, receiving interface R1 is connected with transmission interface X2 by 4 groups of differential signal lines.In these 4 groups of differential signal lines, one group is used for transmission HCLK signal (high-speed clock signal), and its clock frequency is 98.034MHZ, compares frequency with the clock frequency of transmitting in the prior art CLK signal that is 24.56MHZ and is increased to 4 times; Other three groups of differential signal lines all are used for transmitting DR signal (reception of data signal), compared with prior art, the FS signal (frame synchronization clock signal) of one group of differential signal line transmission is replaced with the DX signal, adopt simultaneously untapped one group of differential signal line to transmit DR signal.
In the present embodiment, for further realizing high-speed and high-efficiency, untapped 8 Bit effectively utilize to every passage in prior art, and original 32Bit/CH(8Bit/CH is not wherein used, and have used 24Bit/CH) 16CH be transformed to 24Bit/CH(and all use) 21CH.
At this moment, the data available port number between digital sound console 1 and digital sound console 2 extends to 21CH * 3 * 4=252CH by initial 16CH, can realize like this transfer of data of high-speed and high-efficiency, satisfies the user demand of various large-scale application scenarios.
In order to realize at a high speed, will originally be exclusively used in one group of differential signal line cancellation transmission FS signal of transmission FS signal in said process, then transmission DX signal/DR signal.Thereby this moment, very important FS detected and the CRC check in order to guarantee the reliability of product, and the present embodiment adopts following methods to recover FS detection and CRC check:
After adopting the present invention, every group of differential signal line is at a FS available 98.034MHZ/48kHz=2048Bit in the signal period, if transmission 84CH, the bandwidth that needs is 84CH * 24Bit/CH=2016 Bit, every group of differential signal line each FS in the signal period remaining bandwidth be 32Bit.Thereby, the present embodiment is from being used for 3 groups of differential signal lines of transmission DX signal/DR signal, choose at random one group of differential signal line and use its residue 32 Bit to place the FS test value, select one group of differential signal line and use its residue 32 Bit placement CRC check values, can realize simultaneously FS check and CRC check under the prerequisite of less resource taking like this, guarantee the reliability of product.
The cluster that is comprised of n digital sound console as shown in Figure 6, wherein, the data-handling capacity of 16 passages that each digital sound console itself has has again 252 passages and other digital sound consoles and carries out transfer of data.In actual applications, the quantity that forms the digital sound console of cluster can up to 17, greatly satisfy user's user demand.
The above is only preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. an efficient unlimited digital sound console cluster, comprise N digital sound console; It is characterized in that,
Each digital sound console comprises the DSP unit that is connected and FPGA unit, and is unit cascaded by FPGA between each digital sound console;
Described DSP unit is used for receiving simulated audio signal, and each railway digital audio signal that obtains after its analog-to-digital conversion is issued to the FPGA unit of local terminal together with default signal forward-path information; The digital audio and video signals of sending out on reception local terminal FPGA unit carries out the related audio processing to this digital audio and video signals and described simulated audio signal, controls afterwards output;
Described FPGA unit be used for to receive the digital audio and video signals that local terminal DSP unit issues, and wherein is forwarded to the next stage digital sound console according to the signal forward-path after the packing of the digital audio and video signals more than a tunnel or a tunnel; When the digital audio and video signals that receives from the upper level digital sound console, judge whether local terminal is the destination, if report to the DSP unit of local terminal after it being unpacked, otherwise forward it to the next stage digital sound console;
Described FPGA unit comprises transmission interface and receiving interface; The receiving interface of the FPGA unit of described transmission interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for transmission DX signal; The transmission interface of the FPGA unit of described receiving interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for the transmission DR signal; Every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data.
2. efficient unlimited digital sound console cluster as claimed in claim 1, it is characterized in that, described FPGA unit also is used for filling in the CRC check value by 32 Bit remaining bandwidths of filling in FS detected value, another group differential signal line for 32 Bit remaining bandwidths of the one group of differential signal line of three groups of differential signal lines that transmits DX signal/DR signal.
3. efficient unlimited digital sound console cluster as claimed in claim 1, is characterized in that, the value of described N is not more than 17; The clock frequency of described HCLK signal is 98.034MHZ.
4. efficient unlimited digital sound console cluster as described in as arbitrary in claims 1 to 3, it is characterized in that, described FPGA unit also is used for detecting in real time the whether power down of the digital sound console that is connected with local terminal, passes through digital signal line transmission voltage modulation signal to the opposite end when power down being detected.
5. an efficient unlimited digital sound console cluster, comprise N digital sound console; It is characterized in that, also comprise switch device;
Each digital sound console comprises the DSP unit that is connected and a FPGA unit, and described switch device comprises the 2nd FPGA unit, and each digital sound console is connected by the 2nd FPGA unit of a FPGA unit and switch device respectively;
Described DSP unit be used for to receive the simulated audio signal that the outer signals source input by audio input interface, and each railway digital audio signal of obtaining after its analog-to-digital conversion is issued to a FPGA unit together with the signal forward-path information of presetting; Receive the digital audio and video signals of sending out on a FPGA unit, this digital audio and video signals and described simulated audio signal are carried out related audio process, control afterwards output;
A described FPGA unit is used for receiving the digital audio and video signals that the DSP unit issues, and wherein is forwarded to switch device together with the signal forward-path after the packing of the digital audio and video signals more than a tunnel or a tunnel; When receiving the digital audio and video signals of switch device, after being unpacked, it reports to the DSP unit of local terminal;
Described the 2nd FPGA unit is used for receiving digital audio and video signals and signal forward-path information from each digital sound console, according to this signal forward-path, digital audio and video signals is forwarded to a FPGA unit of designation number sound console;
A described FPGA unit and the 2nd FPGA unit include transmission interface and receiving interface; The receiving interface of the FPGA unit of described transmission interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for transmission DX signal; The transmission interface of the FPGA unit of described receiving interface and opposite end is connected by 4 groups of differential signal lines, and wherein one group of differential signal line is used for transmission HCLK signal, three groups of differential signal lines are used for the transmission DR signal; Every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data.
6. efficient unlimited digital sound console cluster as claimed in claim 5, it is characterized in that, a described FPGA unit and the 2nd FPGA unit, the 32 Bit remaining bandwidths that also are used for the one group of differential signal line of three groups of differential signal lines by being used for transmission DX signal/DR signal are filled in the FS detected value, another 32 Bit remaining bandwidths of organizing differential signal line are filled in the CRC check value.
7. efficient unlimited digital sound console cluster as claimed in claim 5, is characterized in that, the value of described N is not more than 16; The clock frequency of described HCLK signal is 98.034MHZ.
8. efficient unlimited digital sound console cluster as described in as arbitrary in claim 5 to 7, it is characterized in that, a described FPGA unit and the 2nd FPGA unit, also be used for detecting in real time the whether power down of switch device/digital sound console of being connected with local terminal, pass through digital signal line transmission voltage modulation signal to the opposite end when power down being detected.
9. the method for transmitting signals as digital sound console cluster as described in claim 1 or 5, is characterized in that, in this digital sound console cluster, the method for transmitting signals of the FPGA unit of the FPGA unit of transmitting terminal and receiving terminal comprises:
Data transmission procedure: the receiving interface of the FPGA unit of the transmission interface of the FPGA unit of transmitting terminal and receiving terminal is connected by 4 groups of differential signal lines, utilizing wherein, one group of differential signal line transmits the HCLK signal, utilizes other three groups of differential signal lines transmission DX signal, and every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data;
DRP data reception process: the transmission interface of the FPGA unit of the receiving interface of the FPGA unit of transmitting terminal and receiving terminal is connected by 4 groups of differential signal lines, utilizing wherein, one group of differential signal line transmits the HCLK signal, utilizes other three groups of differential signal lines transmission DR signal, and every group of differential signal line comprises 21 data passages, and each data channel comprises the 24Bit data.
10. the method for transmitting signals of digital sound console cluster as claimed in claim 9, it is characterized in that, in the method, described FPGA unit also carries out FS detection and CRC check operation, and fills in the CRC check value by 32 Bit remaining bandwidths of filling in FS detected value, another group differential signal line for 32 Bit remaining bandwidths of the one group of differential signal line of three groups of differential signal lines that transmits DX signal/DR signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310059897.0A CN103166818B (en) | 2013-02-26 | 2013-02-26 | A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310059897.0A CN103166818B (en) | 2013-02-26 | 2013-02-26 | A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103166818A true CN103166818A (en) | 2013-06-19 |
| CN103166818B CN103166818B (en) | 2016-05-11 |
Family
ID=48589570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310059897.0A Active CN103166818B (en) | 2013-02-26 | 2013-02-26 | A kind of efficient unlimited digital sound console cluster and method for transmitting signals thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103166818B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103701551A (en) * | 2013-12-17 | 2014-04-02 | 深圳市东微智能科技有限公司 | Multichannel digital sound console and signal processing method thereof |
| WO2018130045A1 (en) * | 2017-01-10 | 2018-07-19 | 深圳华云数码有限公司 | Data transmission device, method, and inkjet printing system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1791336A2 (en) * | 2005-11-26 | 2007-05-30 | Wolfson Microelectronics Plc | Digital audio device and method |
| CN201557161U (en) * | 2009-10-19 | 2010-08-18 | 南京莱斯信息技术股份有限公司 | Parallel expansion multi-path audio switching mixing device |
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN102833666A (en) * | 2012-07-27 | 2012-12-19 | 深圳市东微智能科技有限公司 | Cascadable digital audio matrix, digital audio communication system and digital audio communication method |
-
2013
- 2013-02-26 CN CN201310059897.0A patent/CN103166818B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1791336A2 (en) * | 2005-11-26 | 2007-05-30 | Wolfson Microelectronics Plc | Digital audio device and method |
| CN201557161U (en) * | 2009-10-19 | 2010-08-18 | 南京莱斯信息技术股份有限公司 | Parallel expansion multi-path audio switching mixing device |
| CN101951313A (en) * | 2010-09-08 | 2011-01-19 | 烽火通信科技股份有限公司 | FPGA-based SFI4.1 device |
| CN102833666A (en) * | 2012-07-27 | 2012-12-19 | 深圳市东微智能科技有限公司 | Cascadable digital audio matrix, digital audio communication system and digital audio communication method |
Non-Patent Citations (2)
| Title |
|---|
| 王龙: "基于FPGA+DSP的音频监测系统设计", 《复旦大学硕士学位论文》 * |
| 赵明: "大气光通信调制编码技术研究", 《华中科技大学硕士学位论文》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103701551A (en) * | 2013-12-17 | 2014-04-02 | 深圳市东微智能科技有限公司 | Multichannel digital sound console and signal processing method thereof |
| WO2018130045A1 (en) * | 2017-01-10 | 2018-07-19 | 深圳华云数码有限公司 | Data transmission device, method, and inkjet printing system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103166818B (en) | 2016-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20150123832A (en) | Universal remote radio head | |
| WO2017128905A1 (en) | Communication system using single host and multiple ring topology most networks | |
| CN102025923A (en) | Digital matrix control system and digital matrix control method for realizing multi-mode access | |
| CN102611719A (en) | Vehicle-mounted MOST (Media Oriented Systems Transport) network system | |
| CN106919180A (en) | The cluster communication system and method for a kind of unmanned plane | |
| CN101394197B (en) | Baseband data transmission method and device for CDMA distributed base station system | |
| CN103166818A (en) | High-efficiency limitless digital sound console cluster and signal transmission method thereof | |
| CN103281773A (en) | System and method for processing data | |
| CN102833666A (en) | Cascadable digital audio matrix, digital audio communication system and digital audio communication method | |
| CN104598403A (en) | Cluster storage system based on PCIE (peripheral component interface express) switch | |
| CN103959895A (en) | Method, device and system for wireless access | |
| CN103209041B (en) | A kind of GSM-R network interface data acquisition method | |
| CN213072889U (en) | 5G optical platform based on DOCSIS | |
| CN103517332A (en) | Base station, data processing method and communication system | |
| CN104796289A (en) | Electric power SDH data service protection configuration method and data service transmission method | |
| CN206602511U (en) | Control system based on DMR and GSM R dual mode communications | |
| CN102307199A (en) | Multimedia transmission and processing apparatus | |
| CN105430666A (en) | Community access method and fiber distribution system | |
| CN101557544B (en) | Module connecting 2B+D scheduling desks by E1 line and method | |
| CN204069019U (en) | For the communication gate of track traffic | |
| CN104796201A (en) | Digital optical transceiver based on secondary multiplexing and demultiplexing | |
| US20180034882A1 (en) | Method and apparatus for bonding communication technologies | |
| CN103200210A (en) | Digital value input device and digital value input method based on high level data link control | |
| CN102761953B (en) | Configuring method for uplink timing advance | |
| CN101296202B (en) | wireless communication system, base station, core network control surface node device and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: 2, 202-B building, C building, Hua Han Innovation Park, No. 16, Lang Shan Road, Guangdong, Shenzhen, Nanshan District 518000, China Patentee after: Shenzhen East micro smart Polytron Technologies Inc Address before: 518107, Hua Han Innovation Park office building, 16 Lang Shan Road, Shenzhen, Guangdong, Nanshan District D403 Patentee before: Shenzhen Tendzone Intelligent Technology Co., Ltd. |
|
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: Room 401, Block D, Huahan Innovation Park, 16 Longshan Road, North District, Xili Street, Nanshan District, Shenzhen City, Guangdong Province, 518000 Patentee after: Shenzhen East micro smart Polytron Technologies Inc Address before: 518000 202-B, 2 floor, block C, office building, Hua Han Innovation Park, 16 Langshan Road, Nanshan District, Shenzhen, Guangdong. Patentee before: Shenzhen East micro smart Polytron Technologies Inc |
|
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 518000 R & D building 1601, block a, building 7, Wanke Yuncheng phase I, Xili community, Xili street, Nanshan District, Shenzhen City, Guangdong Province (16 / F, block a, building 1, international innovation Valley) Patentee after: SHENZHEN TENDZONE INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: Room 401, Block D, Huahan Innovation Park, 16 Longshan Road, North District, Xili Street, Nanshan District, Shenzhen City, Guangdong Province, 518000 Patentee before: SHENZHEN TENDZONE INTELLIGENT TECHNOLOGY Co.,Ltd. |