CN103313397B - A kind of implementation method of LTE downlink system resource impact - Google Patents

Abstract

The invention provides the implementation method of resource impact in a kind of Long Term Evolution (LTE) system, the resource impact of LTE downlink system is realized.The present invention devises one group of control register, reception and the generation of mapping address for control channel data；And the data of master sync signal, auxiliary synchronous signals and reference signal are produced and address is produced.The data and mapping address of various signals send into moderator together after producing, various signals are written in subframe buffering device by moderator with priority set in advance by rule to be mapped, then the sequentially reading from small to large by address, the data of reading, by carrying out IFFT conversion after address conversion, radio frequency part are given after finally being buffered by fifo queue using each symbol as one group.The present invention carries out different resource impacts by the flexible configuration to register, and configurability is strong, and can meet the requirement of LTE system high speed processing.

Description

A kind of implementation method of LTE downlink system resource impact

Technical field

It is a kind of implementation method of resource impact in LTE wireless communication systems the present invention relates to wireless communication technology field, Suitable for the resource impact of LTE downlink system, this method is easy to extension, and configuration is flexible.

Background technology

The descending use OFDMA (Orthogonal of LTE (Long Term Evolution, Long Term Evolution) wireless communication systems Frequency Division Multiple Access, orthogonal frequency division multiplexing multiple access) mode, can flexibly it enter in frequency domain Row Resource Distribution and Schedule, involved resource includes PDCCH (Physical Downlink Control Channel, thing Manage down control channel) signal, PBCH (Physical Broadcast Channel, Physical Broadcast Channel) signals and PDSCH (Physical Downlink Shared Channel, Physical Downlink Shared Channel) signal, PSCH (Primary Synchronization Channel, primary synchronization channel) signal, SSCH (Secondary Synchronization Channel, auxiliary synchronization channel) signal, RS (Reference Signal, reference signal).By " the data from multiple channels Block " is multiplexed in a shared data channel, i.e., so-called resource impact.

The implementation method generally existing hardware configuration of existing resource impact is complicated, the low defect of data transmission bauds, and Without configurability, it is impossible to meet the requirement that LTE system carries out resource impact adjustment in real time, therefore the invention provides one kind Configurable resource impact implementation method, flexibly controls to carry out different resource impacts using the control register group of design. The present invention uses multimode parallel pipelining process operation, it is possible to reduce data delay, improves processing and the transmission rate of data.

The content of the invention

It is an object of the present invention to provide a kind of implementation method of resource impact suitable for LTE downlink system, by setting Count one group of control register and to its flexible configuration to produce data and the address of various signal resources；Using moderator and subframe Buffer realizes the ruling and mapping of various signal resources；And OFDM is completed by address translator, IFFT and CP insertion (Orthogonal Frequency Division Multiple, OFDM) is modulated, the various letters after resource impact Number being sent to radio-frequency module is transmitted wirelessly.

The present invention is realized using following technological means：

1. the implementation method of resource impact in a kind of LTE downlink system, using FPGA (Field-Programmable Gate Array, field programmable gate array) Technology design carry out resource impact modules, to realize downlink system resource The flexible configuration of mapping, it is characterised in that：

1.1. design general control register is used for controlling to produce PSCH signals, SSCH signals, the data of RS signals and reflecting Penetrate address；Design PDCCH control registers are used for controlling CCH (Control Channel, control channel)/BCH (Broadcast Channel, broadcast channel) data sink and address generator；Design PDSCH control registers are used for controlling SCH (Shared Channel, shared channel) data sink and address generator；

1.2. design CCH/BCH, SCH data sink and address generator are respectively intended to control PDCCH signals, PBCH letters Number and PDSCH signal datas reception, while controlling generation different by PDSCH control registers and PDCCH control registers Mapping address is flexibly mapped PDCCH signals, PBCH signals and PDSCH signals；

1.3. design moderator is arbitrated to various signal resources, with certain priority orders by the number of various resources Mapped according to the correspondence position write according to its corresponding address in subframe buffering device；

1.4. design subframe buffering device and address translator complete the mapping of resource, and its writing address is by various signal resources Mapping address determine that and reading address and producing in order, the data of reading are using each symbol as one group, while address translator The input address that address conversion is IFFT is read, the data of reading are sent into the address of the input and IFFT is carried out (Inverse Fast Fourier Transform, Inverse Fast Fourier Transforms) is converted and CP (Cyclic Prefix, circulation Prefix) insert to complete OFDM modulation, it is then placed in FIFO (First In First Out, FIFO) queue and is delayed Punching, to be supplied to the continuous data flow of radio frequency part.

2. the present invention devises one group of control register to control the generations of various signal resources flexibly to be mapped, Control register includes：

2.1. designed general control register has 128, wherein 17 as 3 cell identifications number, is referred to as： CellID, CellID1 and CellID2, the number of the PSCH signals for controlling Z-C (Zadoff-Chu) sequence generation different districts According to and control M sequence produce different districts SSCH signals data, in combination with current sign count value and sub-frame count value Control LFSR (Linear Feedback Shift Register, linear feedback shift register) produces RS data together； The Dynamic gene position of PSCH, SSCH and RS signal takes 32, the parameter adjustment for above-mentioned signal respectively；

2.2. designed PDSCH control registers have 128, wherein 100 map institute's foundation as PDSCH signals Resource bitmap block (Resource Bitmap bitmap, RB bitmap), for controlling PDSCH signals to be mapped to resource block , separately there are last transmission block (Last Transport Block, Last TB) of two conducts mark and empty transmission block in position (Null TB) indicates, the reception for controlling PDSCH signal datas；

2.3. designed PDCCH control registers have 128, resource bitmap block (RB bitmap) therein, last Individual transmission block (Last TB) mark and empty transmission block (Null TB) mark are as the effect in PDSCH control registers, separately The outer data for devising a flag " BCH " to distinguish current transmission are the data of PBCH signals or the number of PDCCH signals Control to distribute to the symbol numbers of PDCCH channels according to, a control bit CCH SYM.

3. resource impact is carried out in units of subframe, mapping address of the various resources in subframe buffering device is by frequency The subcarriers numerical value and resource block counting values in domain and the symbol count value of time domain are determined jointly.

4. using subframe buffering device as resource network trrellis diagram, each memory cell represents a resource particle, subframe buffering Device is realized using two-port RAM (Random Access Memory, random access memory) with the read-write mode of table tennis.

5. moderator according to the rules to various resources arbitrate by good priority, priority is by high to Low order： PDCCH signals, PDSCH signals, RS signals, PSCH and SSCH signals, PDBCH signals.

The present invention is a kind of implementation method of resource impact in LTE system, compared with prior art, with following substantially excellent Gesture and beneficial effect：

Devise control register group flexibly to be controlled come the mapping to various resources, configurability is strong, by writing The control word of control register can control various signals to be entered in real time according to Current resource occupancy situation, area interference situation etc. The different resource allocation of row and mapping, improve resource utilization and anti-interference.

By the way of parallel pipelining process operation, with HDL (Hardware Description Language, Hardware description language Speech) hardware module is designed in fpga chip to realize resource impact function, wanting for LTE system high throughput can be met Ask, logical resource can be saved again, simplify logical complexity, there is very strong practical value.

Brief description of the drawings

Fig. 1 is the frame format schematic diagram employed in the present invention；

The implementation method block diagram that Fig. 2 maps for LTE system downlink resource in the present invention；

Fig. 3 is general control register schematic diagram；

Fig. 4 is SCH/CCH control register schematic diagrames；

Fig. 5 receives state of a control figure for channel data in the present invention；

Fig. 6 is mapping schematic diagram of the various resources in resource grid in the present invention；

Embodiment

Embodiments of the invention are described further below in conjunction with Figure of description：LTE systems provided by the present invention The implementation method of resource impact in system, it is adaptable to LTE downlink system, the present invention is with 2 transmission antennas, 10MHz system bandwidths, just Its mapping process is illustrated exemplified by normal CP LTE downlink system, its input signal is the letter after channel coding and constellation modulation Track data, output signal is sent to radio-frequency module and transmitted wirelessly.

LTE system therein uses FDD (Frequency Division Duplex, FDD) pattern, and frame structure is such as Shown in Fig. 1, a radio frames are transmitted per 10ms, a radio frames are made up of 10 subframes, there are two time slots in each subframe, often OFDM symbol number in individual time slotDetermined by CP length.By taking normal CP, 10M bandwidth as an example, each time slot has 7 Corresponding RB (Resource Block, resource block) number on OFDM symbol, frequency domainFor 50, the subcarrier in each RB NumberFor 12, i.e., a total of 600 subcarriers.

The present invention realizes the real-time control of resource impact by designing one group of control register, and Fig. 2 reflects for downlink resource The implementation method block diagram penetrated, receives PBCH signals, PDCCH signals and the PDSCH after channel coding and constellation modulation first The data of signal, while its respective mapping address is produced by PDCCH control registers and the control of PDSCH control registers, by General control register control produces the data and mapping address for synchronous PSCH signals and SSCH signals, and for believing Then various resources are sent into moderator, moderator is with certain priority by the RS of road estimation data and mapping address together The data of various signals are written in subframe buffering device according to its respective mapping address and mapped, in subframe buffering device Data by address is sequentially read from small to large, and the data of reading pass through progress IFFT changes after address conversion using each symbol as one group Change with CP insertions, and give radio frequency part after being buffered by FIF0.

Control register group designed by the present invention mainly includes 3 registers：General control register, PDCCH controls Register and PDSCH control registers.

The Dynamic gene that general control register is mainly used to the cell identification number of transmission system and determined by modulation system, To adapt to different cells and modulation system, as shown in figure 3, including 3 cell identifications CellID, CellID1 and CellID2, and PSCH Dynamic gene, SSCH Dynamic gene, RS Dynamic gene.

The reception and mapping address of PDCCH control registers and PDSCH control registers for control channel data Generation, as shown in figure 4, resource bitmap block (RB bitmap) is constituted by 100, to adapt to highest 20M system bandwidth, often One RB representing on frequency domain, last transmission block mark and empty transmission block mark are used for representing the state of transmission block, With the reception of control channel data.In order to save resource, PBCH signals are transmitted with PDCCH signals by same port, Therefore BCH flag bits are devised in PDCCH control registers comes controlling transmission PBCH signals or PDCCH signals.In addition, Provided in LTE protocol, the symbolic number for being used to transmit PDCCH signals in each subframe can be 0,1 or 2, therefore in PDCCH controls Grey frame portion point in CCH symbolic number control bits, Fig. 4 is devised in register and represents that PDCCH control registers control to deposit than PDSCH Control bit more than device.

CCH/BCH data sinks and address generator and SCH data sinks and address generator are used for receiving letter Track data simultaneously produces its respective mapping address.

The data of PDCCH signals, PBCH signals and PDSCH signals are all the numbers after channel coding, constellation modulation According to, its receive by PDCCH control registers and PDSCH control registers last transmission block (Last TB) flag bit and Empty transmission block (Null TB) flag bit is controlled by state machine, as shown in Figure 5.Data are received in 501 status requests, if please Ask and 502 states are then gone to when being allowed to.In pending datas such as 502 states effectively, if data effectively, go to 503 states.503 Whether the current TB of status checkout is sky TB, and TB, then go to 504 states if not empty；If it is empty TB, then go to 506 states. Under 504 states, when having request of data and data are effective, data storage, and check whether current TB terminates, if TB terminates, Go to 505 states；Otherwise, the operation under 504 states is continued.In 505 states, data output read request is waited, if there are data defeated Go out read request, then go to 506 states.In 506 states, check whether current TB is last TB, if last TB, then Go to 507 states；Otherwise, 501 states are gone to, request again receives data.507 states, wait present sub-frame to terminate, if currently Subframe terminates, then goes to 501 states, and request again receives data；Otherwise continue to wait in this state.

For PBCH signals, its mapping position is provided by LTE protocol, as shown in Figure 60 1,4 before subframe 0, time slot 1 72 subcarriers of centre are taken on individual OFDM symbol, frequency domain, are defined by formula (3)：

Wherein, k '=0,1..., 71, l=0,1..., 3

That is 7~symbol 10 of the PBCH signals only in subframe 0 is mapped, and 72 of resource block RB22~RB27 are located on frequency domain On subcarrier.

For PDCCH signals and PDSCH signals, it is controlled to account for by PDCCH control registers and PDSCH control registers According to symbol numbers, the present invention in, in order to reserve more resources give user carry out flexible allocation, setting PDCCH signals occupy The symbol 0 of each subframe, as shown in Figure 60 2, setting PDSCH signals occupy 1~symbol of symbol 13 in subframe, such as the institutes of Figure 60 3 Show.And the specific mapping position of PDCCH signals and PDSCH signals in occupied symbol, by PDCCH control registers and Resource bitmap block in PDSCH control registers carries out flexible in real time according to Current resource occupancy situation, area interference situation etc. Configuration, control which of resource grid RB is used for the transmission block for transmitting current demand signal.

PSCH generators are used for producing the data and mapping address of PSCH signals.The data of wherein PSCH signals are by 62 ZC sequences produce, produce formula for example shown in formula (1)：

In formula 1, u is to define the relation of the two in CellID2 root system number, LTE protocol, i.e., as CellID2=0, u For 25, CellID2=1 when, when u is 29, CellID2=2, u is 34, therefore, by the cell identification in general control register Number CellID2 can control to produce the PSCH signal datas of different districts.In addition, in general control register PSCH adjustment because Son can be adjusted to 62 data of generation to obtain the data of final PSCH signals, and modulation factor depends on modulation methods Formula.

The mapping position of PSCH signals is fixed, is mapped to based on symmetrical 62 subcarriers of direct current, it is located at son In 7th OFDM symbol of frame 0 and subframe 5, the subcarrier maps position of PSCH signal frequency domains is provided by LTE protocol, according to public affairs Formula (2) is produced：

N=0 ..., 61 (2)

I.e. mapping position is that 62 sons being located on the frequency domain of symbol 6 in resource grid in the middle of resource block RB22~RB27 are carried Ripple, as shown in Figure 60 4.

SSCH generators are used for producing the data and mapping address of SSCH signals.Wherein SSCH signals are based on M sequence Cell identification CellID1 and CellID2 in maximal-length sequence, general control register can control M sequence to carry out not Same cyclic shift, so as to produce the sequence that two length are 31, sends, two sequences for distinguishing in subframe 0 or subframe 5 After row are interleaved and cascaded, by the Dynamic gene in general control register be adjusted after obtain the data of SSCH signals, Modulation factor depends on modulation system.

The mapping position of SSCH signals is also fixed, and unlike PSCH signals, and the mapping position of SSCH signals is On the subcarrier of 6th symbol of subframe 0 and subframe 5, specific subcarrier maps position is produced according to formula (2).That is SSCH The frequency domain mapping address of signal is that 62 sons being located on the frequency domain of symbol 5 in resource grid in the middle of resource block RB22~RB27 are carried Ripple, as shown in Figure 60 5.

RS generators are used for producing the data and mapping address of RS signals.The data of RS signals are produced by LFSR, LFSR initial seed value be by the cell identification CellID2 in general control register and current symbol count value and Sub-frame count value composition, therefore the cell identification CellID2 of general control register can control generation different districts RS data, are then adjusted the data for obtaining final RS by the Dynamic gene in general control register, and modulation factor takes Certainly in modulation system.

The RS signals of downlink system use dispersed structure, and identical RS data are inserted to 2 transmission antennas in the present invention, with Simplify RS signal structures, improve channel estimation accuracy, therefore RS 12 ash frame institutes of the mapping position as representated by Figure 60 6 Show：In a sub- frame in, RS data are mapped in the symbol 0 in time domain, symbol 4, symbol 7 and symbol 11, and on frequency domain Mapping position is subcarrier 0, subcarrier 3, subcarrier 6 and the subcarrier 9 of each resource block (RB).

PDCCH signals, PBCH signals, PDSCH signals, PSCH signals, SSCH signals and RS signals mapping position it is each not It is identical, illustrated above, and the production method of its mapping address each in a buffer is identical, Subcarriers numerical value and RB count values on respective frequency domain respectively, and symbol count value in time domain are collectively constituted, i.e.,：

Mapping address=symbol count value × 600+RB count values × 12+ subcarriers numerical value

Wherein, the count range of subcarriers numerical value is that the count range of 0~11, RB count values is 0~49, symbol count The count range of value is 0~13.The relation of three is, when subcarriers numeric counter is to 11, and RB count values add 1, and RB is counted When value count down to 49, symbol count value adds 1.

Moderator is used for arbitrating various signal resources.The data and mapping address of various signal resources are all sent into Moderator, moderator according to the priority that sets, i.e. PDCCH signals, PDSCH signals, RS signals, PSCH and SSCH signals, The data of various signal resources, are written in the subframe buffering device of corresponding mapping address and complete money by the order of PBCH signals respectively The mapping in source.

Subframe buffering device, using a two-port RAM, realized as resource grid by the read-write mode of table tennis, if Data of the depth of two-port RAM for 2 subframes are put, i.e. 600 × 14 × 2=16800, subframe buffering device A carries out write operation, write After the data of a complete subframe, subframe buffering device B is given, subframe buffering device B starts read operation, while subframe buffering device A is then Write the data of a subframe.

Address translator is used for the input address for IFFT by the reading address conversion of subframe buffering device.In subframe buffering device Data are that 600 data are one group according to address sequentially reading from small to large, each symbol is read, and carry out IFFT conversion, and root According to system bandwidth 10MHz, IFFT points are 1024 points, it is therefore desirable to by address conversion by 600 data of each symbol It is respectively fed at IFFT high 300 addresses and low 300 addresses, i.e., the data on the frequency domain of each symbol at 0~299 address Send at IFFT input address 724~1023, at the data feeding IFFT input address 0~299 at 300~599 addresses, and its Zero filling processing is performed at his 300~723 addresses.The operation that the IFFT conversion and CP for carrying out afterwards at 1024 points are inserted.

To ensure the data continuity for being transferred to radio-frequency module, buffered before feeding radio-frequency module outwards transmitting Processing, is realized by FIFO in the present invention.

It is described above, it is a kind of embodiment of the present invention under systematic parameter, not for being any limitation as to the present invention, this Invention be applicable under different systematic parameters.

Claims (5)

1. a kind of implementation method of LTE downlink system resource impact, using FPGA (Field-Programmable Gate Array, field programmable gate array) Technology design carry out resource impact modules, to realize downlink system resource impact Flexible configuration, it is characterised in that：

1.1. design general control register is used for controlling to produce PSCH signals, SSCH signals, the data of RS signals and mapping ground Location；Design PDCCH control registers are used for controlling CCH (Control Channel, control channel)/BCH (Broadcast Channel, broadcast channel) data sink and address generator；Design PDSCH control registers are used for controlling SCH (Shared Channel, shared channel) data sink and address generator；

1.2. design CCH/BCH, SCH data sink and address generator be respectively intended to control PDCCH signals, PBCH signals and The reception of PDSCH signal datas, while by the mapping different with the control generation of PDCCH control registers of PDSCH control registers Address is flexibly mapped PDCCH signals, PBCH signals and PDSCH signals；

1.3. design moderator is arbitrated to various signal resources, is pressed the data of various resources with certain priority orders Mapped according to the correspondence position in its corresponding address write-in subframe buffering device；

1.4. design subframe buffering device and address translator complete the mapping of resource, and its writing address is reflected by various signal resources Penetrate address decision, and read address and produce in order, the data of reading using each symbol as one group, while address translator by its The input address that address conversion is IFFT is read, the data of reading are sent into the address of the input and IFFT (Inverse are carried out Fast Fourier Transform, Inverse Fast Fourier Transforms) convert and CP (Cyclic Prefix, cyclic prefix) insertions To complete OFDM modulation, it is then placed in FIFO (First In First Out, FIFO) queue and enters row buffering, provides Give radio frequency part continuous data flow.

2. the implementation method of the resource impact according to claim 1, it is characterised in that devise one group of control register To control the generations of various signal resources flexibly to be mapped, control register includes：

2.1. designed general control register has 128, wherein 17 as 3 cell identifications number, is referred to as：CellID、 CellID1 and CellID2, for control Z-C (Zadoff-Chu) sequence produce different districts PSCH signals data and control M sequence processed produces the data of the SSCH signals of different districts, started to control in combination with current sign count value and sub-frame count value one LFSR (Linear Feedback Shift Register, linear feedback shift register) processed produces RS data；PSCH、 The Dynamic gene position of SSCH and RS signals takes 32, the parameter adjustment for above-mentioned signal respectively；

2.2. designed PDSCH control registers have 128, wherein 100 resources that institute's foundation is mapped as PDSCH signals Bitmap block (Resource Bitmap bitmap, RB bitmap), for controlling PDSCH signals to be mapped to the position of resource block, It is another to have last transmission block (Last Transport Block, Last TB) of two conducts mark and empty transmission block (Null TB) indicate, the reception for controlling PDSCH signal datas；

2.3. designed PDCCH control registers have 128, resource bitmap block (RB bitmap) therein, last biography Defeated piece (Last TB) indicates and empty transmission block (Null TB) mark is as the effect in PDSCH control registers, set in addition The data for having counted a flag " BCH " to distinguish current transmission are the data of PBCH signals or the data of PDCCH signals, one Individual control bit CCH SYM control to distribute to the symbol numbers of PDCCH channels.

3. the implementation method of the resource impact according to claim 1, it is characterised in that：Resource impact is using subframe to be single Position carry out, mapping address of the various resources in subframe buffering device by frequency domain subcarriers numerical value and resource block counting values And the symbol count value of time domain is determined jointly.

4. the implementation method of the resource impact according to claim 1, it is characterised in that：Money is used as using subframe buffering device Source grid chart, each memory cell represents a resource particle, and subframe buffering device uses two-port RAM (Random Access Memory, random access memory) realized with the read-write mode of table tennis.

5. the implementation method of the resource impact according to claim 1, it is characterised in that：Moderator is good excellent according to the rules First level is arbitrated to various resources, and priority is by high to Low order：PDCCH signals, PDSCH signals, RS signals, PSCH With SSCH signals, PDBCH (Physical Downlink Broadcast CHannel physical downs broadcast channel) signal.