CN106711187A - High K power device with high withstand voltage and low specific on-resistance - Google Patents
High K power device with high withstand voltage and low specific on-resistance Download PDFInfo
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- CN106711187A CN106711187A CN201611121043.0A CN201611121043A CN106711187A CN 106711187 A CN106711187 A CN 106711187A CN 201611121043 A CN201611121043 A CN 201611121043A CN 106711187 A CN106711187 A CN 106711187A
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 3
- 239000010931 gold Substances 0.000 claims 3
- 229910052737 gold Inorganic materials 0.000 claims 3
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000000779 depleting effect Effects 0.000 abstract 1
- 238000005429 filling process Methods 0.000 abstract 1
- 229910052735 hafnium Inorganic materials 0.000 description 10
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
Abstract
The invention relates to a high K power device with high withstand voltage and low specific on-resistance, which belongs to the technical field of power semiconductor devices. The high K power device introduces a high K dielectric slot into a drift region so as to assist in depleting the drift region and reduce conductive resistance of the device, and can modulate in-body electric field distribution of the device to increase the breakdown voltage of the device. A high-concentration N type bar is introduced into a low interface of the high K dielectric slot, when in an on state, a low-resistance channel is provided, and the conductive resistance of the device is reduced. The auxiliary depletion function of the high K dielectric slot is used for improving the concentration of the N type bar and the drift region, so as to further reduce the conductive resistance of the device; when in an off state, an ionization integral path is shortened, the in-body electric field can be improved, and the breakdown voltage of the device can be increased; and the structure of the shallow and wide high K dielectric slot can be implemented more easily during the filling process. By adopting the high K power device, various high K semiconductor power devices with transverse low specific on-resistance, high withstand voltage and excellent performance can be obtained.
Description
Technical field
The low K power devices high than leading of high withstand voltage of the present invention belong to power semiconductor device technology field.
Background technology
Power semiconductor, the microelectronics device that can be worked under high pressure, high current from P=IV, exactly a class
Part.And develop along the direction for improving power and frequency.Requirement based on the above, the design requirement of power device has high hitting
Wear voltage BV, it is low than conducting resistance Ron, sp and realize the rapid translating between ON state and OFF state.For generally grinding at this stage
The silicon materials device studied carefully, than the relation that conducting resistance Ron, sp and breakdown voltage BV exponentially increase --- i.e. " the silicon limit ", than
Conducting resistance increase can increase the conduction loss of device, reduce the performance of device.Device is realized than conducting resistance Ron, sp and
Compromise between pressure-resistant BV, is the main research work of design power device.
With continuing to develop for semiconductor process technique, the grid size of device is reduced to .18um by .5um, and device is more next
Smaller, integrated level more and more higher, power consumption is more and more lower.So reducing the table of device while retainer member breakdown voltage high
Area i.e. the length of drift region, the another Consideration as design power device.Slot type power device is by media slot
Go deep into drift region, be bent downwardly drift region, reduce lateral drift section length so that the surface area of device is greatly reduced, and is subtracted
Small production cost.And lateral channel can be transformed into longitudinal channel by slot grid structure.During ON state, there is electronics at the edge of groove grid
Accumulation, formed raceway groove, make device inside CURRENT DISTRIBUTION more uniform；During OFF state, slot grid structure can optimize longitudinal electric field, and
Longitudinal media slot undertakes part drain voltage, makes that device is pressure-resistant to be improved.
In order to further optimize the relation more pressure-resistant than conducting resistance and device, the Chen Xing academicians that assist propose superjunction power device
Part, but there is substrate-assisted depletion effect in super junction power device so that N bars and P bar charge unbalances, and then largely effect on device
The voltage endurance of part.And high K dielectric slot structure is introduced in the drift region of device, due to the dielectric coefficient of silicon materials（εs=
11.9）Much smaller than the dielectric coefficient of hafnium（Hafnium dielectric coefficient is even thousands of up to hundreds of）, the electrical conductivity of silicon materials
More than the electrical conductivity of hafnium.In ON state, the current density of silicon materialsMuch larger than the current density of hafnium,
Device is presented low impedance path's phenomenon；In OFF state, because the dielectric coefficient of hafnium is far above the dielectric coefficient of silicon materials, because
This most power line is terminated in source, therefore silicon layer by high K dielectric and surface field is relatively low, it is to avoid occur shifting to an earlier date
Puncture, improve the pressure-resistant of device.High K dielectric groove can be improved the pressure-resistant of device and reduced the ratio of device with assisted depletion drift region
The effect of conducting resistance.Relative to low-K dielectric slot structure, high K dielectric groove has bigger advantage in technique：（1）Breakdown potential
Pressure is not it is obvious that process allowance is larger with the change of drift region concentration range；（2）Because high K dielectric groove is designed to shallow and wide
Trench structure, is easier to realize, so high K dielectric groove possesses more preferable application prospect in process filling.
The content of the invention
The purpose of the present patent application is by introducing high K dielectric groove assisted depletion drift region in device drift region, carrying
The breakdown voltage of device high, reduces the ratio conducting resistance of device, alleviates " the silicon limit " problem of device.By in high K dielectric groove
Lower interface introduce high concentration N+Bar, there is provided low impedance path, further reduces the conducting resistance of device, and then reduce device
Compare conducting resistance.Deep slot grid structure is introduced on the left side of device, in ON state, electronics is accumulated at gate oxide, there is provided low-resistance
Passage, reduces device and compares conducting resistance.Three's collective effect, has further expanded the low application model than leading high voltage power device
Enclose.
To solve the above problems, following technical scheme is the embodiment of the invention provides：
A kind of low K power devices high than leading of high withstand voltage, its structure cell includes P type substrate 11, oxide layer 32, N-type drift region
21, it is characterised in that：The N-type drift region 21 includes P type trap zone 13, high K dielectric groove 41；Polygate electrodes 54.
Specifically,
The P type trap zone 13 includes p-type heavily doped region 12 and N-type heavily doped region 23, and its upper end is source electrode 52, and left end is grid
Oxidation trough 32.
Specifically,
The source electrode 52 and gate electrode 51 are isolated by passivation layer 33.
Specifically,
The polygate electrodes 54 are arranged on the left end of N drift regions 21.
Specifically,
The polygate electrodes 54 extend to drift region the inside and are connected with oxide layer 31.
Specifically,
The high K dielectric slot structure is connected in being arranged on N-type drift region 21 with P type trap zone 13 and N-type heavily doped region 24.
Specifically,
The upper end of N-type heavily doped region 24 is provided with drain terminal electrode 53.
Specifically,
The drain terminal electrode 53 and source electrode 52 are isolated by passivation layer 34.
Specifically,
The high concentration N-type bar 22 is arranged in N-type drift region 21 and designs in the following of high K dielectric groove 41, with high K dielectric
Groove 41 is connected.
Specifically,
The underlayer electrode 55 is arranged on the lower surface of P type substrate 11.
Compared with prior art, above-mentioned technical proposal has advantages below：
The low K power devices high than leading of a kind of high withstand voltage that the present invention is provided, high K dielectric groove 41 is introduced in drift region 21,
High concentration N-type bar 22 is introduced in the downside of high K dielectric groove 41.The present invention compared with conventional art, i.e., in the drift region of device
Middle introducing high K dielectric groove equivalent to two field plate structures, assisted depletion drift region, it is pressure-resistant to improve device, improves drift region concentration,
Reduce the ratio conducting resistance of device.Introduced when high concentration N-type bar can make device in ON state in K interfaces high and low-resistance is provided
Passage, further reduces the ratio conducting resistance of device, in OFF state, reduces ionization path of integration, improves the breakdown potential of device
Pressure, realizes compromise pressure-resistant and than leading, obtains power figure of merit FOM higher.Using deep slot grid structure, electricity is accumulated in ON state
Son, reduces the ratio conducting resistance of device.Relatively with low-K dielectric slot structure, high K dielectric groove has bigger advantage in technique：
（1）Breakdown voltage is not it is obvious that process allowance is larger with the change of drift region concentration range；（2）Because high K dielectric groove is designed to
The trench structure of shallow and wide, is easier to realize in process filling.
Brief description of the drawings
Fig. 1 is conventional transverse direction high-voltage power device structure generalized section；
Fig. 2 is the low lateral high-voltage device section of structure than conducting resistance of high K dielectric groove of the invention；
Fig. 3 is the OFF state principle schematic of the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention；
Fig. 4 is the ON state principle schematic of the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention；
Fig. 5 is that high K dielectric groove of the invention is low to be contrasted than the lateral high-voltage device of conducting resistance and the transverse electric field of conventional structure
Figure；
Fig. 6 is that high K dielectric groove of the invention is low to be contrasted than the lateral high-voltage device of conducting resistance and the longitudinal electric field of conventional structure
Figure；
Fig. 7 is equipotential lines when the low lateral high-voltage device and conventional structure than conducting resistance of high K dielectric groove of the invention punctures
Distribution map；
Fig. 8 is the structure chart of the low lateral high-voltage device than conducting resistance of high K dielectric groove of shallow slot grid structure of the invention；
Fig. 9 is the structure chart of the low lateral high-voltage device than conducting resistance of high K dielectric groove of medium slot grid structure of the invention；
Figure 10 is the structure chart of the low lateral high-voltage device than conducting resistance of high K dielectric groove of deep slot grid structure of the invention；
Figure 11 is the low lateral high-voltage device profile than conducting resistance of high K dielectric groove of the invention, wherein the 2nd article of high concentration N
Type bar 25 is located at the right side of media slot；
Figure 12 is the low lateral high-voltage device profile than conducting resistance of high K dielectric groove of the invention, is set on the basis of Fig. 2
Two gate electrodes of meter；
Figure 13 is the low lateral high-voltage device knot figure than conducting resistance of high K dielectric groove of deep slot grid structure of the invention, oxygen buried layer
31 are set to stairstepping；
Figure 14 is the low lateral high-voltage device knot figure than conducting resistance of high K dielectric groove of deep slot grid structure of the invention, oxygen buried layer
31 are set to two-sided stairstepping；
Figure 15 is the low lateral high-voltage device knot figure than conducting resistance of high K dielectric groove of deep slot grid structure of the invention, oxygen buried layer
31 are set to part oxygen buried layer structure；
Figure 16 is the low lateral high-voltage device knot figure than conducting resistance of high K dielectric groove of deep slot grid structure of the invention, oxygen buried layer
31 are set to K oxygen buried layers high, i.e., 42 is hafnium；
Figure 17 is the low lateral high-voltage device structure chart than conducting resistance of high K dielectric groove of the invention, its gate electrode groove grid knot
Structure, grid is on the device left side, and grid oxygen thing is that hafnium, i.e., 42 are hafnium；
Figure 18 is the low lateral high-voltage device structure chart than conducting resistance of high K dielectric groove of the invention, its gate electrode groove grid knot
Structure, grid in the devices between, and gate oxide be hafnium, i.e., 42 be hafnium；
Figure 19 is that the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention is applied in body silicon device, its substrate
Material p-type body silicon；
Figure 20 is that the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention is applied in body silicon device, its substrate
Material p-type body silicon, groove grid extend to P type substrate the inside；
Figure 21 is that the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention is applied in PMOS device, its N-type
Drift region 21 is changed into P drift area 12；
Figure 22 is that the low lateral high-voltage device than conducting resistance of high K dielectric groove of the invention is applied in LIGBT, and 14 is p-type weight
Doping, 25 is the N-Buffer areas of high concentration.
Figure 23 is the low lateral high-voltage device section of structure than conducting resistance of high K dielectric groove of the invention.
Claims (10)
1. a kind of low K power devices high than leading of high withstand voltage, its structure cell includes P type substrate 11, SiO2Oxygen buried layer 31, N-type floats
Move area 21, it is characterised in that：The N-type drift region 21 includes high K dielectric groove 41, highly doped N bars 22, p-well region 13.
2. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：The p-well region 13
Including p-type heavily doped region 12 and N-type heavily doped region 23, its upper end is source electrode 52, and its left end is gate oxide 32 and polycrystalline
Si-gate field plate 54.
3. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：Described polycrystalline
Si-gate field plate 54 is connected with gate electrode 51.
4. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：The grid gold
Category 51 and source metal 52 are isolated by dielectric layer 32.
5. high performance K power devices high of one kind according to claim 1, it is characterised in that：The high K dielectric groove 41 with
First N-type heavy doping bar 22 is connected.
6. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：The polysilicon
Grid field plate 54 extends to the bottom of drift region 21 after being connected with gate oxide 32.
7. high performance K power devices high of one kind according to claim 1, it is characterised in that：The first N-type heavy doping
The upper end of area 24 is provided with drain metal 53.
8. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：The drain electrode gold
Isolated by dielectric layer 34 between category 53 and source class metal 52.
9. low K power devices high than leading of a kind of high withstand voltage according to claim 1, it is characterised in that：The drain electrode gold
Category 53 and source class metal 52 are across above high K dielectric groove.
10. high performance K power devices high of one kind according to claim 1, it is characterised in that：The SiO2Oxygen buried layer 31
It is connected with P type substrate 11 with N-type drift region 21.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611121043.0A CN106711187A (en) | 2016-12-08 | 2016-12-08 | High K power device with high withstand voltage and low specific on-resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611121043.0A CN106711187A (en) | 2016-12-08 | 2016-12-08 | High K power device with high withstand voltage and low specific on-resistance |
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| Publication Number | Publication Date |
|---|---|
| CN106711187A true CN106711187A (en) | 2017-05-24 |
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ID=58937599
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192778A (en) * | 2018-08-01 | 2019-01-11 | 长沙理工大学 | A kind of separate gate slot type power device with double longitudinal field plates |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120228695A1 (en) * | 2011-03-11 | 2012-09-13 | Globalfoundries Singapore Pte. Ltd. | Ldmos with improved breakdown voltage |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
| CN106024858A (en) * | 2016-05-19 | 2016-10-12 | 电子科技大学 | HK SOI LDMOSdevice having three-grating structure |
-
2016
- 2016-12-08 CN CN201611121043.0A patent/CN106711187A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120228695A1 (en) * | 2011-03-11 | 2012-09-13 | Globalfoundries Singapore Pte. Ltd. | Ldmos with improved breakdown voltage |
| CN104201206A (en) * | 2014-08-29 | 2014-12-10 | 电子科技大学 | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device |
| CN106024858A (en) * | 2016-05-19 | 2016-10-12 | 电子科技大学 | HK SOI LDMOSdevice having three-grating structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109192778A (en) * | 2018-08-01 | 2019-01-11 | 长沙理工大学 | A kind of separate gate slot type power device with double longitudinal field plates |
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| CB02 | Change of applicant information |
Address after: 410114 No. 960, Section 2, Wanjiali South Road, Tianxin District, Changsha City, Hunan Province Applicant after: Changsha University of Sciences and Technology Address before: 410114 No. 2, 960 Wan Li Li South Road, Yuhua District, Changsha, Hunan Applicant before: Changsha University of Sciences and Technology |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170524 |
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