CN106683979A - 在键合前清洗键合表面的方法 - Google Patents
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Abstract
本发明提供了一种在键合前清洗键合表面的方法，包括如下步骤：提供两个用于键合的第一表面和第二表面，所述第一表面为非晶表面，第二表面为晶体表面；在键合前采用氨水分别清洗所述第一表面和第二表面，清洗所述第一表面所采用的氨水浓度和清洗温度两个参数中的至少一个参数高于清洗所述第二表面所采用的参数。
Description
技术领域
本发明涉及半导体材料制造领域，尤其涉及一种在键合前清洗键合表面的方法。
背景技术
键合是半导体工艺中常见工艺。键合界面接触是否良好是衡量键合质量的重要标准。现有技术中将两个衬底进行键合后，有时在衬底缺口的对侧会发现键合接触的不良区域。附图1所示是现有技术中键合界面产生不良区域的示意图。在衬底10的缺口11的对侧的键合区域，会产生键合界面的接触不良。如何避免这一区域产生接触不良，是现有技术需要解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种能够提高键合界面质量的键合方法。
为了解决上述问题，本发明提供了一种在键合前清洗键合表面的方法，包括如下步骤：提供两个用于键合的第一表面和第二表面，所述第一表面为非晶表面，第二表面为晶体表面；在键合前采用氨水分别清洗所述第一表面和第二表面，清洗所述第一表面所采用的氨水浓度和清洗温度两个参数中的至少一个参数高于清洗所述第二表面所采用的参数。
可选的，所述氨水为含有过氧化氢的缓冲溶液。
可选的，所述第一表面的表面材料为氧化物。
可选的，所述第二表面的表面材料为半导体。
可选的，所述第一表面的表面材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。
可选的，所述第二表面的表面材料选自于硅晶体、锗硅晶体、碳化硅晶体、氮化镓晶体以及砷化镓晶体中的任意一种。
可选的，所述第二表面的表面材料为表面覆盖非晶薄膜的半导体，所述非晶薄膜的厚度小于50nm。
可选的，所述非晶薄膜的材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。
本发明通过清洗所述第一表面所采用的氨水浓度和清洗温度两个参数中的至少一个参数高于清洗所述第二表面所采用的参数的方法，降低了晶体表面的键合活性，从而降低键合波的传播速度，有利于键合面形成密切接触。
附图说明
附图1所示是现有技术中键合界面产生不良区域的示意图。
附图2所示是本发明一具体实施方式所述方法的实施步骤示意图。
具体实施方式
下面结合附图对本发明提供的一种在键合前清洗键合表面的方法的具体实施方式做详细说明。
附图2所示是本具体实施方式所述方法的实施步骤示意图，包括如下步骤：步骤S20，提供用于键合的第一表面和第二表面；步骤S21，在键合前采用氨水清洗所述第一表面；步骤S22，在键合前采用氨水清洗所述第二表面。
步骤S20，提供用于键合的第一表面和第二表面。所述第一表面为非晶表面，第二表面为晶体表面。
作为一个具体实施方式，所述第一表面的表面材料为氧化物，所述第二表面的表面材料为半导体。在这一具体实施方式中，所述第一表面可以是形成于一支撑衬底表面的氧化层。所述支撑衬底的材料选自于硅晶体、锗硅晶体、碳化硅晶体、氮化镓晶体以及砷化镓晶体中的任意一种，也可以是蓝宝石衬底以及金属衬底等；所述第一表面的表面材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。例如可以是在单晶硅衬底表面的氧化硅层，所述第一表面是该氧化硅层的表面。而第二表面可以是一半导体衬底的一个表面。所述半导体衬底的材料选自于硅晶体、锗硅晶体、碳化硅晶体、氮化镓晶体以及砷化镓晶体中的任意一种，例如可以是单晶硅衬底，所述第二表面为该衬底的一个面。
作为一个具体实施方式，所述第二表面的表面材料也可以是表面覆盖非晶薄膜的半导体，所述非晶薄膜的厚度小于50nm。所述非晶薄膜的材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。所述半导体的材料选自于硅晶体、锗硅晶体、碳化硅晶体、氮化镓晶体以及砷化镓晶体中的任意一种。例如所述第二表面可以是覆盖厚度小于50nm氧化硅层的单晶硅。由于非晶薄膜的厚度较小，因此该表面在键合中会表现出半导体材料的特征。
步骤S21，在键合前采用氨水清洗所述第一表面。在键合前需要对第一表面进行清洗以去除杂质，清洗所采用的方法包括RCA标准清洗法或者其他类似的清洗方法。为了去除金属污染物和有机污染物，所采用的清洗方法中应当包括采用氨水清洗的步骤。在本具体实施方式中，该步骤所采用的清洗液优选为氨水的缓冲溶液，即NH4OH、H2O2、H2O按照一比例配比形成的溶液。该配比的比例范围例如可以是1:1:5～1:2:7。清洗的温度范围根据实际需要可以是50℃～80℃。
步骤S22，在键合前采用氨水清洗所述第二表面。在键合前需要对第二表面进行清洗以去除杂质，清洗所采用的方法包括RCA标准清洗法或者其他类似的清洗方法。为了去除金属污染物和有机污染物，所采用的清洗方法中应当包括采用氨水清洗的步骤。在本具体实施方式中，该步骤所采用的清洗液优选为氨水的缓冲溶液，即NH4OH、H2O2、H2O按照一比例配比形成的溶液。该配比的比例范围例如可以是1:1:5～1:2:7。清洗的温度范围根据实际需要可以是50℃～80℃。在本步骤中，所采用的清洗液中氨水的浓度，即NH4OH在溶液中的浓度，应当低于步骤S21，或者所采用的清洗温度低于步骤S21。也可以是上述两个条件均被实施，即NH4OH在溶液中的浓度低于步骤S21，且所采用的清洗温度也低于步骤S21。并优选为NH4OH在溶液中的浓度低于步骤S21，因为实践表明氨水浓度改变起到的效果要优于温度。例如，NH4OH：H2O2＝1:2条件下，清洗第一表面温度为70℃，清洗第二表面为50℃；如果同为70℃清洗，第一表面使用NH4OH：H2O2＝3：4清洗液，第二表面使用NH4OH：H2O2＝1：2清洗液。也可以是清洗第一表面温度为50℃，清洗第二表面为70℃，并且第一表面使用NH4OH：H2O2＝3：4清洗液，第二表面使用NH4OH：H2O2＝1：2清洗液。
上述两个表面会被用于键合。键合面的形成机制是键合过程中的键合波沿着键合面传播而使两个键合面密切接触。对于具有一缺口的半导体衬底而言，键合波会首先在该缺口处形成并沿着该缺口向外发散。对于不具有缺口的其他形状的键合表面，键合波也会随机选择一个或者几个点形成，并向外发散。键合波的发散速度越慢越有利于键合面形成密切接触。而键合波的发散速度是由表面的键合活性决定的，并且晶体表面的键合活性高于非晶表面。表面覆盖非晶薄膜的半导体材料表面在键合中会表现出半导体材料的特征，即晶体特征。对于非晶和晶体的键合，表面的键合速度主要由键合活性更高的晶体表面决定的。实验发现，氨水清洗有利于活化表面的键合活性，浓度越高活化作用越明显，清洗温度越高活化作用越明显。因此本具体实施方式通过清洗所述第一表面所采用的氨水浓度和清洗温度两个参数中的至少一个参数高于清洗所述第二表面所采用的参数的方法，降低了晶体表面的键合活性，从而降低键合波的传播速度，有利于键合面形成密切接触。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
Claims (8)
1.一种在键合前清洗键合表面的方法，其特征在于，包括如下步骤：
提供用于键合的第一表面和第二表面，所述第一表面为非晶表面，第二表面为晶体表面；
在键合前采用氨水分别清洗所述第一表面和第二表面，清洗所述第一表面所采用的氨水浓度和清洗温度两个参数中的至少一个参数高于清洗所述第二表面所采用的参数。
2.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述氨水为含有过氧化氢的缓冲溶液。
3.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述第一表面的表面材料为氧化物。
4.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述第二表面的表面材料为半导体。
5.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述第一表面的表面材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。
6.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述第二表面的表面材料选自于硅晶体、锗硅晶体、碳化硅晶体、氮化镓晶体以及砷化镓晶体中的任意一种。
7.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述第二表面的表面材料为表面覆盖非晶薄膜的半导体，所述非晶薄膜的厚度小于50nm。
8.根据权利要求1所述的在键合前清洗键合表面的方法，其特征在于，所述非晶薄膜的材料选自于氧化硅、氮化硅和氮氧化硅中的任意一种。
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| JPH05136014A (ja) * | 1991-11-15 | 1993-06-01 | Sumitomo Metal Mining Co Ltd | 貼り合わせｓｏｉ基板の製造方法 |
| CN1996551A (zh) * | 2005-12-28 | 2007-07-11 | 中国科学院半导体研究所 | 晶片直接键合过程中实验参数的优化方法 |
| CN102842488A (zh) * | 2012-08-24 | 2012-12-26 | 上海新傲科技股份有限公司 | 在衬底的双面制造器件的方法以及衬底 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05136014A (ja) * | 1991-11-15 | 1993-06-01 | Sumitomo Metal Mining Co Ltd | 貼り合わせｓｏｉ基板の製造方法 |
| CN1996551A (zh) * | 2005-12-28 | 2007-07-11 | 中国科学院半导体研究所 | 晶片直接键合过程中实验参数的优化方法 |
| CN102842488A (zh) * | 2012-08-24 | 2012-12-26 | 上海新傲科技股份有限公司 | 在衬底的双面制造器件的方法以及衬底 |
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