CN106672892A - Method for reducing depressed deformation of sacrificial layer in three-dimensional stacking in chemical mechanical polishing - Google Patents

Method for reducing depressed deformation of sacrificial layer in three-dimensional stacking in chemical mechanical polishing Download PDF

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Publication number
CN106672892A
CN106672892A CN201611189122.5A CN201611189122A CN106672892A CN 106672892 A CN106672892 A CN 106672892A CN 201611189122 A CN201611189122 A CN 201611189122A CN 106672892 A CN106672892 A CN 106672892A
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China
Prior art keywords
layer
etching
planarization
mechanical polishing
sacrifice layer
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CN201611189122.5A
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Chinese (zh)
Inventor
钱可强
赵洪元
郁元卫
朱健
禹淼
夏燕
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CETC 55 Research Institute
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CETC 55 Research Institute
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Priority to CN201611189122.5A priority Critical patent/CN106672892A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate

Abstract

The invention relates to a method for reducing depressed deformation of a sacrificial layer in three-dimensional stacking in chemical mechanical polishing. The method includes the steps of firstly, growing a stop layer; secondly, etching the stop layer to form an etching trench; thirdly, depositing the sacrificial layer; fourthly, etching the sacrificial layer; fifthly, depositing a planarization layer; sixthly, conducting wafer non-graphical etching; seventhly, removing the sacrificial layer and the planarization layer; eighthly, removing the stop layer; ninthly, adjusting flatness and roughness of a wafer through chemico-mechanical polishing; tenthly, cleaning after grinding. The method has the advantages that since the photoetched sacrificial layer and planarization material filling are added, surface morphological unevenness caused by graphics with huge differences in size and density is removed and the super-thick sacrificial layer CMP cost is reduced greatly; ultra-high planarization uniformity and little depressed deformation can be achieved through non-graphical etching and three-step CMP, so that the planarization requirements on different thicknesses of silicon dioxide sacrificial layers in three-dimensional stacking are met.

Description

The method for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing
Technical field
The present invention relates to a kind of reduce three-dimensional stacked middle sacrifice layer in chemically mechanical polishing（CMP）The method of middle depressed deformation The method of depressed deformation, belongs to micro electro-mechanical system packaging technical field.
Background technology
In radio frequency micro-system, active chip, IPD and MEMS sensor etc. are integrated with by three-dimensional stacked mode many Field device or chip.Wherein MEMS sensor includes the movable structure that can much realize difference in functionality, the reality of movable structure Sacrifice layer process, sacrificial layer material is now typically adopted to include silicon oxide, PSG, particulate metal and polymer etc.；In order to three-dimensional Stacking is mutually compatible, it is contemplated that sensitivity of other device layers to temperature, and using cryogenic oxidation silicon the technique of sacrifice layer is done, conventional Silicon oxide sacrificial layer process flow is as follows：In grown above silicon stop-layer silicon nitride, chemical wet etching stop-layer, shallow slot is etched；So It is fully filled with shallow slot using PECVD cvd silicon oxides afterwards；Recycle CMP（Chemically mechanical polishing）By the silicon oxide beyond shallow slot Remove, and realize global planarizartion；Silicon oxide surface after planarization makees device；Finally the silicon oxide in shallow slot is gone completely Remove, realize the hanging of device.
Traditional sacrifice layer process can realize the uniform global planarizartion of little live width, figure, but for the m-300 of live width 1 The figure of m just occurs serious butterfly depression and structure partial deformation in the presence of simultaneously, can cause very high to flatness requirement Complete device failure；Its reason is, in silicon oxide CMP（Chemically mechanical polishing）Process, big figure grinds relative to little figure Speed is fast, and figure greatly forms butterfly depression through grinding after causing little image hotpoint to planarize；Due to the size span of figure Decades of times is differed, the region meeting of depression to the uniformity of subsequent deposition thin film it is obvious that make a big impact；In addition, this The sacrifice layer process of structure is applied to the hanging device of making, it is impossible to big figure is divided into into many little using the method for graph cut Figure is connected；The complexity of three-dimensional stacked middle device and technique is also considered, sacrifice layer process is made using low temperature.
The method for reducing butterfly depression and deformation at present is the then CMP again by the unnecessary silicon oxide of chemical wet etching, Sophisticated projection is still suffered from after this method etching and stay in shallow slot edge, be unfavorable for planarization.
The content of the invention
The present invention proposes a kind of method for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing, uses It is recessed to solve silicon dioxide sacrificial layer is produced in chemically mechanical polishing in three-dimensional stacked MEMS local deformation and butterfly Fall into.
The technical solution of the present invention：One kind reduces three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing Method, comprise the following steps：
（One）Stop-layer is grown in silicon chip substrate, the material of the production stop-layer is silicon nitride（Si3N4）, nitrogen silication close One kind in thing, carborundum；
（Two）Chemical wet etching stop-layer forms etching groove；
（Three）Deposition of sacrificial layer, fills up etching groove, and the sacrifice layer is silicon oxide（SiO2）, thickness is 2 m-50 m, specifically Thickness is according to step（Two）The depth of middle etching groove determines；
（Four）Chemical wet etching sacrifice layer：Sacrificial layer material on chemical wet etching substrate beyond etching groove；
（Five）Deposited planarization layer；
（Six）Disk is without graphical etching；
（Seven）Chemically mechanical polishing removes sacrifice layer and planarization layer；
（Eight）Stop-layer is removed by dry or wet art lithography etching；
（Nine）Chemically mechanical polishing adjustment disk flatness and roughness, are carried out using lapping liquid of the particle diameter less than 100nm Fine polishing, and improve the flatness and roughness of disk surfaces, reach global planarizartion；
（Ten）Clean after being ground to disk.
The beneficial effect that the present invention is obtained：
1）By increasing by a step chemical wet etching sacrifice layer, post-depositional step can be reduced, greatly reduce smoothing material Filling and chemically mechanical polishing difficulty；
2）By the deposition and levelling of planarization layer material, the material can be caused to be completely covered and fill up sacrifice layer step, be disappeared Except the disk rough surface topography that the sacrifice layer string of deposits is come, it is to avoid zones of different feature size and density are different Affect；
3）By removing planarization layer, sacrifice layer and stop-layer without pattern etching and CMP, greatly reduce Depressed deformation after CMP；
4）By increasing chemical wet etching sacrifice layer and smoothing material filling, eliminate because feature size and density span are too big The surface topography for causing rises and falls, and greatly reduces the cost of thick sacrifice layer CMP；
5）And can realize that the planarization uniformity and minimum depression of superelevation become without pattern etching and three steps CMP using disk Shape, meet it is three-dimensional stacked in different-thickness silicon dioxide sacrificial layer planarization requirement.
Description of the drawings
Accompanying drawing 1 is the schematic diagram of example 1 of existing sacrifice layer CMP local butterfly depression.
Accompanying drawing 2 is the schematic diagram of example 2 of existing sacrifice layer CMP local butterfly depression.
Accompanying drawing 3 is that sacrifice layer is deposited and schematic diagram after chemical wet etching in the present invention.
Accompanying drawing 4 be in the present invention planarization layer material filling after schematic diagram.
Accompanying drawing 5 is without schematic diagram after graphical etching in the present invention.
Accompanying drawing 6 is the schematic diagram in the present invention after first time CMP.
Accompanying drawing 7 is removed and the schematic diagram after second CMP through stop-layer in the present invention.
1 is the step formed after deposition of sacrificial layer in accompanying drawing, and 2 is the step stayed after chemical wet etching sacrifice layer, and 3 silicon chips are served as a contrast Bottom, 4 is etching groove, and 5 are off layer, and 6 is sacrifice layer, and 7 is planarization layer.
Specific embodiment
It is a kind of to reduce the method that three-dimensional stacked middle silicon dioxide sacrificial layer chemically-mechanicapolish polishes depressed deformation, the method include with Lower step：
（One）Stop-layer is grown in silicon chip substrate, the material of the production stop-layer is silicon nitride（Si3N4）, nitrogen silication close One kind in thing, carborundum；
（Two）Chemical wet etching stop-layer forms etching groove；
（Three）Deposition of sacrificial layer, sacrifice layer fills up etching groove, and the sacrifice layer is silicon oxide（SiO2）, thickness is 2 m-50 M, concrete thickness is according to step（Two）The depth of middle etching groove determines；
（Four）Chemical wet etching sacrifice layer：Sacrificial layer material in chemical wet etching silicon chip substrate outside etching groove；
（Five）Deposited planarization layer；
（Six）Disk is without graphical etching；
（Seven）Chemically mechanical polishing removes sacrifice layer and planarization layer outside etching groove；
（Eight）Stop-layer is removed by dry or wet art lithography etching；
（Nine）Chemically mechanical polishing adjustment disk flatness and roughness, are carried out using lapping liquid of the particle diameter less than 100nm Fine polishing, and improve the flatness and roughness of disk surfaces, reach global planarizartion；
（Ten）Clean after being ground to disk.
The step（Four）Middle chemical wet etching sacrifice layer is the sacrificial layer material in chemical wet etching silicon chip substrate outside etching groove, Mask plate used by chemical wet etching sacrifice layer is the mask plate of etching stop layer, and deposits shape in sacrifice layer using reversal photoresist Into step bottom to be formed and shelter, exposed place is performed etching；Photoetching process has good exposure performance, will The mesa sidewall photoresist that deposition of sacrificial layer is formed all is removed.
The step（Five）Middle planarization layer material is dielectric material, high molecular polymer or metal alloy compositions, is had Very strong reflux characteristic, can be good at filling step（Four）In the step that stays；Deposited planarization layer material and step（Three） The sacrifice layer of middle deposition has identical etch rate（0.4um/min~0.6um/min）With CMP grinding rates（200nm/min~ 350nm/min）；The levelling technique of deposited planarization layer is by way of heating or flowing back so that the filling of planarization layer material In step to after chemical wet etching sacrifice layer, improve because the deposition of sacrifice layer causes the rough pattern of disk surfaces, from And realize that sacrificial layer surface is planarized；Planarization layer has good adhesiveness with sacrifice layer；Planarization layer material fill processes 350 DEG C are less than with the temperature of levelling technique.
The step（Six）Carrying out disk can reduce the milling time and cost of sacrifice layer CMP without pattern etching, etching Depth determines according to sacrificial layer thickness in step 3, step（Six）Carry out adopting dry etching, etching homogeneity without pattern etching Require within 1%.
The step（Seven）The sacrifice layer and planarization layer that middle chemically mechanical polishing is removed outside etching groove is comprised the following steps：
1）Quickly ground using lapping liquid and polishing pad, grinding rate is 200nm/min ~ 350nm/min, removes planarization Sacrifice layer outside layer and most of etching groove；
2）Low speed grinding is carried out using lapping liquid and polishing pad, grinding rate is 50nm/min ~ 100nm/min so that grinding work Skill stops at stop-layer, grinds without crossing.
With reference to embodiment, the invention will be further described.
Embodiment 1
A kind of method for reducing three-dimensional stacked middle silicon dioxide sacrificial layer CMP depressed deformation：
As shown in figure 3, growing stop-layer 5 first on silicon substrate 3, then chemical wet etching stop-layer 5, continues to etch silicon substrate 3 The etching groove 4 that 2 m-50 m, width are 3 m-300 m is formed, etching groove 4 is filled up and had more the m of 1 m to 5 by deposition of sacrificial layer 6, Carry out inverting the part that the step 1 of chemical wet etching sacrifice layer formation of deposits is higher by using stop-layer mask plate, then deposit flat Change layer 7, make planarization layer 7 be fully filled with step 2 using levelling technique, such as Fig. 4；
Planarization layer technique is simultaneously removed planarization layer 7 and sacrifice layer 6 without pattern etching by disk after terminating, and is finally being stopped The sacrifice layer that thickness is approximately less than 5um is only left on layer 5, as shown in figure 5, for the sacrifice layer 6 of tens micron thickness needs to utilize Etch and remove the sacrifice layer that major part is higher by silicon chip surface, to improve the efficiency of subsequent CMP；
The sacrifice layer for being higher by silicon chip surface is removed by first time CMP, the step is divided into two steps CMP, be respectively adopted quick（Grind Mill speed 300nm/min）At a slow speed（Grinding rate 60nm/min）Grinding, the grinding that quick grinding can quickly reach setting is thick Degree, at a slow speed grinding allows grinding accurately to stop on stop-layer 5, without there is grinding, as shown in Figure 6；
Finally, the final effect such as Fig. 7 is realized by the removal and second CMP grinding of stop-layer 5, by above-mentioned technical process Reduce the depression defect after sacrifice layer CMP and local deformation；
In sum, a kind of process for reducing three-dimensional stacked middle silicon dioxide sacrificial layer CMP depressed deformation has been invented, by light Carve etching sacrificial layer, the filling of planarization layer material, without pattern etching and three step CMPs, greatly reduce and locally become after CMP The probability that shape and depression occur.
The preferred embodiments of the present invention are above are only, any restriction effect, any affiliated technology are not played to the present invention The technical staff in field, in the range of without departing from technical scheme, pair the invention discloses technical scheme and technology Content makes the variation such as any type of equivalent or modification, belongs to the content without departing from technical scheme, still falls within Within protection scope of the present invention.

Claims (5)

1. a kind of method for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing, is characterized in that including following Step：
（One）Stop-layer is grown in silicon chip substrate, the material of the production stop-layer is silicon nitride, nitrogen silicon compound, carborundum In one kind；
（Two）Chemical wet etching stop-layer simultaneously forms etching groove；
（Three）Deposition of sacrificial layer, sacrifice layer fills up etching groove, and the sacrifice layer is silicon oxide, and thickness is 2 m-50 m；
（Four）Chemical wet etching sacrifice layer：Sacrificial layer material in chemical wet etching silicon chip substrate outside etching groove；
（Five）Deposited planarization layer；
（Six）Disk is without graphical etching；
（Seven）Chemically mechanical polishing removes sacrifice layer and planarization layer outside etching groove；
（Eight）Stop-layer is removed by dry or wet art lithography etching；
（Nine）Chemically mechanical polishing adjustment disk flatness and roughness, are carried out using lapping liquid of the particle diameter less than 100nm Fine polishing, improves the flatness and roughness of disk surfaces, reaches global planarizartion；
（Ten）Clean after being ground to disk.
2. a kind of side for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing according to claim 1 Method, is characterized in that the chemical wet etching sacrifice layer for the sacrificial layer material outside etching groove in chemical wet etching silicon chip substrate；
Mask plate used by chemical wet etching sacrifice layer is the mask plate of etching stop layer, and is sunk in sacrifice layer using reversal photoresist The step bottom that product is formed forms and shelters, and exposed place is performed etching.
3. a kind of side for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing according to claim 1 Method, the material that it is characterized in that the planarization layer is the one kind in dielectric material, high molecular polymer or metal alloy compositions；
Deposited planarization layer has identical etch rate with deposition of sacrificial layer：0.4um/min ~ 0.6um/min and chemical machinery The grinding rate of polishing：200nm/min~350nm/min；
The levelling technique of deposited planarization layer is so that planarization layer material is filled into photoetching by way of heating or flowing back In step after etching sacrificial layer；
The temperature of the planarization layer fill process and levelling technique is less than 350 DEG C.
4. a kind of side for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing according to claim 1 Method, is characterized in that the etching depth of the disk without pattern etching that carry out determines that etching homogeneity is required according to sacrificial layer thickness Within 1%.
5. a kind of side for reducing three-dimensional stacked middle sacrifice layer depressed deformation in chemically mechanical polishing according to claim 1 Method, is characterized in that the chemically mechanical polishing removes sacrifice layer and planarization layer outside etching groove and comprises the following steps：
1）Quickly ground using lapping liquid and polishing pad, grinding rate is 200nm/min ~ 350nm/min, removes planarization Sacrifice layer outside layer and most of etching groove；
2）Low speed grinding is carried out using lapping liquid and polishing pad, grinding rate is 50nm/min ~ 100nm/min so that grinding work Skill stops at stop-layer.
CN201611189122.5A 2016-12-21 2016-12-21 Method for reducing depressed deformation of sacrificial layer in three-dimensional stacking in chemical mechanical polishing Pending CN106672892A (en)

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Cited By (5)

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CN107758607A (en) * 2017-09-29 2018-03-06 湖南大学 A kind of high conformal autologous preparation method of nanoscale of high-aspect-ratio
CN107910261A (en) * 2017-11-16 2018-04-13 睿力集成电路有限公司 The method for planarizing surface of insulation fill stratum
CN111115563A (en) * 2019-12-23 2020-05-08 湖南大学 Method for stripping functional material by full-dry method
CN112864310A (en) * 2019-11-26 2021-05-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN115464549A (en) * 2021-06-11 2022-12-13 芯恩（青岛）集成电路有限公司 Chemical mechanical polishing method

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107758607A (en) * 2017-09-29 2018-03-06 湖南大学 A kind of high conformal autologous preparation method of nanoscale of high-aspect-ratio
CN107910261A (en) * 2017-11-16 2018-04-13 睿力集成电路有限公司 The method for planarizing surface of insulation fill stratum
CN112864310A (en) * 2019-11-26 2021-05-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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CN111115563A (en) * 2019-12-23 2020-05-08 湖南大学 Method for stripping functional material by full-dry method
CN115464549A (en) * 2021-06-11 2022-12-13 芯恩（青岛）集成电路有限公司 Chemical mechanical polishing method
CN115464549B (en) * 2021-06-11 2024-01-30 芯恩（青岛）集成电路有限公司 Chemical mechanical polishing method

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