CN106430080A - Production method for MEMS wide-groove and low-step structure - Google Patents
Production method for MEMS wide-groove and low-step structure Download PDFInfo
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- CN106430080A CN106430080A CN201610893773.6A CN201610893773A CN106430080A CN 106430080 A CN106430080 A CN 106430080A CN 201610893773 A CN201610893773 A CN 201610893773A CN 106430080 A CN106430080 A CN 106430080A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
- B81C1/00468—Releasing structures
- B81C1/00476—Releasing structures removing a sacrificial layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
- B81C1/00611—Processes for the planarisation of structures
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Abstract
The invention discloses a production method for an MEMS wide-groove and low-step structure. The method is characterized in comprising the steps of 1), carrying out photoetching and etching on a silicon wafer, thereby forming a groove; 2), growing a SiO <2 > barrier layer on the silicon wafer with the groove obtained in the step 1); 3),depositing a polycrystalline silicon sacrificial layer on the silicon wafer obtained in the step 2); 4), through adoption of a chemical-mechanical polishing technology, flattening the surface of the silicon wafer by employing Si rough grinding fluid, and removing the polycrystalline silicon sacrificial layer on the surface of the silicon wafer, wherein the groove is still filled up with the polycrystalline silicon sacrificial layer; 5), carrying out chemical-mechanical polishing on a SiO <2 > layer through adoption of SiO <2 > grinding liquid, and removing the SiO <2 > layer of partial thickness on the surface of the silicon wafer, wherein the upper surface of the polycrystalline silicon sacrificial layer in the groove is higher than that of the upper surface of the SiO <2 > barrier layer out of the groove; and 6), planing the polycrystalline silicon sacrificial layer which project out of the upper surface of the silicon wafer in the step 5) through adoption of Si fine grinding liquid, thereby forming the MEMS wide-groove and low-step structure.
Description
Technical field
The present invention relates to the manufacture field of mems device, the making of the low ledge structure of specifically a kind of MEMS sipes
Method.
Background technology
Micro-cavity structure in MEMS (MEMS) is one of MEMS common structure.It generally comprises curved beam
With shell etc., this structure is commonly used to fabricate movable micro-structural, is applied in all kinds of microsensors and microactuators.
In recent years, the MEMS technology development that microelectric technique is produced with the mixing together of the field such as machinery, optics is swift and violent, especially
It is even more to be widely used based on the wave filter of MEMS technology.The MEMS pair such as traditional pressure sensor, acceleration transducer
Movable micro-cavity structure required precision is not very high, but the emerging device such as wave filter based on MEMS technology is to micro-cavity structure precision
Require very harsh, the upper support layer of microcavity requires close to Utopian smooth.
During technique is realized, supporting layer to be carried out, the foundation stone work that difficult point is exactly following will be carried out, that is, carry out sacrifice
The planarization of layer, the sacrifice layer in groove and groove theca externa step the smaller the better (less than 50nm).The wave filter of different frequency
Groove width is different, the widest even up to 500 μm, therefore, realize the low ledge structure of sipes be carry out MEMS filter most critical,
Most crucial work.
The low ledge structure of sipes to be realized, is exactly mainly the planarization carrying out sacrifice layer.Traditional flatening process has instead
Quarter, glass backflow, spin coating film layer etc., anti-carving is using dry etching technology etching sacrificial layer, by with faster than lower figure
Etch rate etches away the figure of eminence to make surface planarisation, but smoothened for close for surface step be that a kind of local is flat
Smoothization, anti-carves and does not enable global planarizartion；Glass backflow is to flow by BPSG to realize planarizing, and glass backflow also can only
Obtain part to planarize, be insufficient for global planarizartion requirement；Equally, spin coating film layer is also to be limited to too high shoulder height
And it is not suitable for low step technique.
CMP CMP process is the best-of-breed technology realizing global planarizartion, in planarization identical material, maximum
Shoulder height can reach 50 angstroms.But directly CMP is carried out to sacrifice layer, still cannot realize the low step of sipes (groove width 500 μ
M, step be less than 50nm) structure, specifically：
First, because in groove sacrifice layer and groove theca externa be bi-material material (otherwise the later stage cannot releasing sacrificial layer, then
Micro-cavity structure cannot be formed), in planarization process, process endpoint is uncontrollable；
2nd, because CMP is to reach removal and the planarization of material, machinery by chemistry and two kinds of active forces of machinery
Effect is the main cause of inhomogeneities in piece, and subregion polishing speed is very fast, and subregion polishing speed is relatively slow, flat
During smoothization, surface sacrificial layer is removed totally by the very fast region of polishing speed, and the slower region surface of polishing speed is still
Remaining polycrystalline, (still fills up sacrifice layer) only in order to ensure that whole silicon chip surface sacrifice layer all dries in groove, necessarily lead to throw
Sacrifice layer in the very fast region trenches of optical speed formed throwing, formed sunk structure as shown in Figure 4, and the height being recessed with
The width of groove is directly proportional, and that is, groove is wider, and recess heights are bigger, and this is also CMP (as tungsten CMP, copper CMP, polycrystalline CMP
Deng) common problem.
This depression that CMP is formed, shoulder height can control in 200nm, still has away from the requirement less than 50nm
Not small distance.
Therefore, it is badly in need of a kind of method realizing the low ledge structure of MEMS sipes.
Content of the invention
Present invention aim to address in prior art, the manufacturing process of the low ledge structure of MEMS sipes is complicated, manufacture efficiency
Low problem.
Employed technical scheme comprise that such for realizing the object of the invention, a kind of making of the low ledge structure of MEMS sipes
Method is it is characterised in that comprise the following steps：
1) photoetching, etching are carried out on silicon chip, forms groove；
2) in step 1) in the tool fluted grown above silicon SiO that obtains2Barrier layer；
3) in step 2) in depositing polysilicon sacrifice layer on the silicon chip that obtains；
4) adopt CMP process, with Si rough lapping liquid, the surface of silicon chip is carried out with planarizing process, remove silicon
The polysilicon sacrificial layer on piece surface, still fills up polysilicon sacrificial layer in described groove；
5) adopt SiO2Lapping liquid is to SiO2Layer is chemically-mechanicapolish polished, and removes the SiO of the segment thickness of silicon chip surface2
Layer, in described groove, the upper surface of polysilicon sacrificial layer is higher than the outer SiO of groove2The upper level on barrier layer；
6) adopt Si lappingout grinding fluid by step 5) in the polysilicon sacrificial layer that protrudes of silicon chip upper surface throw flat, formed a kind of
The low ledge structure of MEMS sipes.
Further, described step 1) in gash depth be 1～10 μm, width be 10 μm～500 μm.
Further, described step 2) in SiO2The thickness on barrier layer is 100nm～2000nm.
Further, described step 3) in polysilicon sacrificial layer thickness be more than groove depth；Described polysilicon sacrificial layer
Can also be amorphous silicon material (amorphous silicon α-Si), polyimides or Other substrate materials.
Further, described step 4) in CMP process in, in addition to the polysilicon sacrificial layer in groove, silicon chip
The polysilicon sacrificial layer in remaining region of surface is milled away, and polishing is in SiO2Barrier layer terminates.
Further, described step 5) in the SiO that gets rid of of silicon chip surface2The thickness of layer is 200～300nm.
What deserves to be explained is, described step 6) in chemically-mechanicapolish polished, Si lappingout grinding fluid SiO outer to groove2Stop
The polycrystalline protruding at groove, almost without amount of grinding, effectively can be thrown flat, form the structure of the low step of wide groove, ensure ditch simultaneously by layer
The rough surface of polycrystalline in groove.
The solution have the advantages that mathematical, the present invention has advantages below：
1) all techniques that the inventive method adopts are regular IC process, effectively by MEMS technology and IC process compatible.
2) the inventive method employs three sections of CMP to realize the planarization of sacrifice layer, and three sections of CMP can be one
By being integrated into a process menu on platform board, one time CMP process can be achieved with, and process is simple, make efficiency are high.
Brief description
Fig. 1 is to carry out photoetching, etching on silicon chip, forms the silicon chip generalized section after groove；
Fig. 2 is the one layer of SiO of grown above silicon in Fig. 12Generalized section behind barrier layer；
Fig. 3 is the generalized section after depositing one layer of polysilicon sacrificial layer on the silicon chip of Fig. 2；
Fig. 4 is to carry out the generalized section after CMP rough polishing to polysilicon layer on the silicon chip of Fig. 3；
Fig. 5 is to SiO on the silicon chip of Fig. 42Barrier layer carries out the generalized section after CMP planarization；
Fig. 6 is to carry out CMP finishing polish to polysilicon sacrificial layer on the silicon chip of Fig. 5, ultimately forms a kind of MEMS sipes low
The generalized section of ledge structure；
In figure：Silicon chip 1, groove 2, SiO2Behind barrier layer 3,4, CMP rough polishing of polysilicon sacrificial layer due to polishing not
Uniformly or excessively throw the recessed polysilicon sacrifice layer 41 being formed, secondary SiO2The convex polysilicon sacrificial layer being formed after the CMP of barrier layer
42nd, the low step polysilicon sacrificial layer 43 being formed after three CMP finishing polishes.
Specific embodiment
With reference to embodiment, the invention will be further described, but only should not be construed the above-mentioned subject area of the present invention
It is limited to following embodiments.Without departing from the idea case in the present invention described above, according to ordinary skill knowledge and used
With means, make various replacements and change, all should include within the scope of the present invention.
A kind of preparation method of the low ledge structure of MEMS sipes is it is characterised in that comprise the following steps：
1) as shown in figure 1, photoetching, etching are carried out on silicon chip 1, form groove 2；
Specifically：From<100>Crystal orientation, 625 ± 20 μm of thickness, the P-type silicon piece 1 of resistivity 10-20 Ω cm, cleaning,
Oxidation, oxidated layer thickness is 0.6 ± 0.05 μm；Carry out conventional lithographic, output trench region；Use ammonium fluoride corrosive agent, etching is gone
Fall the SiO on trench region 22；With at the KOH solution of mass percent 20%～30%, 70 DEG C, wet etching 3～5min, shape
Become groove 2, the depth of groove is 1～5 μm；
2) as shown in Fig. 2 in step 1) in obtain have on the silicon chip 1 of groove 2 and grow SiO2Barrier layer 3；
Specifically：The silicon chip 1 defining groove 2 is carried out, at 1000 DEG C, adopts thermal oxidation technology, grow 1 μm
Thick SiO2Barrier layer 3；
3) as shown in figure 3, in step 2) in depositing polysilicon sacrifice layer 4 on the silicon chip 1 that obtains；
Specifically：At 625 DEG C, one layer of 1～5 μm of polysilicon sacrificial layer 4 is deposited using LPCVD, polysilicon sacrificial layer 4
Thickness have to be larger than the depth of groove；
4) as shown in figure 4, adopting CMP process, with Si rough lapping liquid, the surface of silicon chip 1 is planarized
Process, remove the polysilicon sacrificial layer 4 of silicon chip surface, in described groove 2, fill up polysilicon sacrificial layer 41；
Specifically：From silicon rough polishing solution, using chemically mechanical polishing (CMP) technique, silicon chip is planarized, by silicon
The polysilicon layer on piece surface removes totally, still fills up polysilicon sacrificial layer 41, its thickness is suitable with gash depth, shape in groove
Become sunk structure as shown in Figure 4, polysilicon sacrificial layer SiO outer with groove in groove2Layer shoulder height is about 100～300nm.
5) as shown in figure 5, adopting SiO2Lapping liquid is to SiO2Layer chemically-mechanicapolish polished, remove silicon chip surface 200～
The SiO of 300nm2Layer, in described groove, the upper surface of polysilicon sacrificial layer is higher than the outer SiO of groove2The upper level on barrier layer；
Specifically：Due to SiO2Polishing fluid is to SiO2Corrosion rate be slightly larger than its corrosion rate to polysilicon, therefore go
Fall the SiO of 200～300nm thickness of silicon chip surface2Behind barrier layer, the polysilicon sacrificial layer 32 in groove defines convex
Structure, polysilicon SiO outer with groove in groove2The shoulder height of layer is about 100～200nm.
6) as shown in fig. 6, using Si lappingout grinding fluid by step 5) in the polysilicon sacrificial layer that protrudes of silicon chip upper surface throw flat,
Form a kind of low ledge structure of MEMS sipes.
Specifically：From silicon precise polishing solution, using chemically mechanical polishing (CMP) technique, silicon chip is planarized, by ditch
The polysilicon of groove internal projection throws flat, the formation low ledge structure of sipes, polysilicon layer SiO outer with groove in groove2The shoulder height 0 of layer
～50nm.
Claims (6)
1. a kind of preparation method of the low ledge structure of MEMS sipes is it is characterised in that comprise the following steps：
1) photoetching, etching are carried out on silicon chip, forms groove；
2) in step 1) in the tool fluted grown above silicon SiO that obtains2Barrier layer；
3) in step 2) in depositing polysilicon sacrifice layer on the silicon chip that obtains；
4) adopt CMP process, with Si rough lapping liquid, the surface of silicon chip is carried out with planarizing process, remove silicon chip table
The polysilicon sacrificial layer in face, still fills up polysilicon sacrificial layer in described groove；
5) adopt SiO2Lapping liquid is to SiO2Layer is chemically-mechanicapolish polished, and removes the SiO of the segment thickness of silicon chip surface2Layer, institute
The upper surface stating polysilicon sacrificial layer in groove is higher than the outer SiO of groove2The upper level on barrier layer；
6) adopt Si lappingout grinding fluid by step 5) in the polysilicon sacrificial layer that protrudes of silicon chip upper surface throw flat, form a kind of MEMS width
The low ledge structure of groove.
2. a kind of low ledge structure of MEMS sipes according to claim 1 preparation method it is characterised in that：Described step
1) gash depth in is 1～10 μm, and width is 10 μm～500 μm.
3. a kind of low ledge structure of MEMS sipes according to claim 1 preparation method it is characterised in that：Described step
2) SiO in2The thickness on barrier layer is 100nm～2000nm.
4. a kind of low ledge structure of MEMS sipes according to claim 1 preparation method it is characterised in that：Described step
3) the polysilicon sacrificial layer thickness in is more than the depth of groove；Described polysilicon sacrificial layer can also be amorphous silicon material, polyamides
Imines or photoresist.
5. a kind of low ledge structure of MEMS sipes according to claim 1 preparation method it is characterised in that：Described step
4) in the CMP process in, in addition to the polysilicon sacrificial layer in groove, the polysilicon in remaining region of silicon chip surface is sacrificial
Domestic animal layer is milled away, and polishing is in SiO2Barrier layer terminates.
6. a kind of low ledge structure of MEMS sipes according to claim 1 preparation method it is characterised in that：Described step
5) SiO that in, silicon chip surface is got rid of2The thickness of layer is 200～300nm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112158795A (en) * | 2020-09-01 | 2021-01-01 | 瑞声声学科技(深圳)有限公司 | Preparation method of silicon wafer with rough surface and silicon wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112158795B (en) * | 2020-09-01 | 2023-09-01 | 瑞声声学科技(深圳)有限公司 | Preparation method of silicon wafer with rough surface and silicon wafer |
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