CN107578996B - A kind of three-dimensional storage and its flattening method - Google Patents
A kind of three-dimensional storage and its flattening method Download PDFInfo
- Publication number
- CN107578996B CN107578996B CN201710771687.2A CN201710771687A CN107578996B CN 107578996 B CN107578996 B CN 107578996B CN 201710771687 A CN201710771687 A CN 201710771687A CN 107578996 B CN107578996 B CN 107578996B
- Authority
- CN
- China
- Prior art keywords
- nucleus
- substrate
- barrier layer
- peripheral region
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
This application involves a kind of three-dimensional storage and its flattening methods; before planarisation step; it is controlled by oxidated layer thickness; and increase the second barrier layer that setting is flushed with the first barrier layer of nucleus in depletion region and peripheral region; since the removal speed on barrier layer is slower than the removal speed of oxide layer; therefore; on the one hand; barrier layer can protect the laminated construction of nucleus; avoid the influence as caused by excessive grinding in the prior art; three-dimensional storage integrated artistic uniformity is improved, yield is improved;On the other hand, barrier layer can protect peripheral region and depletion region, avoid the occurrence of recess.Simultaneously; since the major part of the nucleus of device, depletion region and peripheral region is blocked layer protection; the only juncture area of peripheral region and depletion region and the protrusion of stepped area is flattened, so that the planarization time greatly shortens, improves element manufacturing efficiency.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology field more particularly to a kind of three-dimensional storage and its planarization sides
Method.
Background technique
Nand flash memory is a kind of storage equipment more better than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.Currently, the nand flash memory of planar structure is
Close to the limit of true extension, in order to further improve memory capacity, the carrying cost of every bit is reduced, proposes 3D structure
Nand memory.
In 3D nand memory structure, by the way of vertical stacking multi-layer data storage unit, stack is realized
The multi-layer data storage unit of 3D nand memory structure, these vertical stackings is referred to as step.However in the mistake of production step
Cheng Zhong, after step formation, it is poor that top layer and the lowest level of step will form a very big step height, it is often necessary to
It is filled with oxide layer, then chemical mechanical grinding (CMP, Chemical Mechanical is carried out to device surface
Planarization)。
But lapping uniformity is poor in planarization process in the prior art, and wafer segment region has caused by grinding deficiency
Oxide layer residual or grinding excess caused by core space damage, peripheral region recess the defects of, to subsequent channel etching with
And Metal Bonding Technology impacts.
Summary of the invention
In view of this, the present invention provides a kind of three-dimensional storage and its flattening method, to solve wafer in the prior art
Partial region has core space damage caused by oxide layer residual caused by grinding deficiency or grinding excess, peripheral region recess
The defects of, the problem of being impacted to subsequent channel etching and Metal Bonding Technology.
To achieve the above object, the invention provides the following technical scheme:
A kind of three-dimensional storage flattening method, applied to the production of three-dimensional storage, the three-dimensional storage includes lining
Bottom, the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at the peripheral region and institute
It states between nucleus, is directed toward the depletion region and stepped region that the nucleus direction is set gradually along the peripheral region
Domain;Step structure is formed on the stepped area substrate;Be formed on the nucleus substrate including the first sub- lamination and
The cross layered laminated construction of second sub- lamination, and the laminated construction is the first barrier layer away from the surface of the substrate;
The three-dimensional storage flattening method includes:
Deposited oxide layer makes surface and the first barrier layer court of the oxide layer of the depletion region away from the substrate
It is flushed to the surface of the substrate;
The oxide layer for removing the peripheral region makes surface and institute of the oxide layer of the peripheral region away from the substrate
The oxide layer for stating depletion region is flushed away from the surface of the substrate;
The second barrier layer is formed in all oxide layers;
Remove the second barrier layer of the nucleus and the oxide layer of the nucleus;
First time planarization is carried out, the peripheral region, the depletion region, the stepped area and the core space are made
The surface in domain flushes to second barrier layer surface for deviating from the substrate;
Remove the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the nucleus
First barrier layer;
It carries out second to planarize, makes the peripheral region, the depletion region, the stepped area and the core space
The surface in domain flushes the surface that the depletion region oxide layer deviates from the substrate.
Preferably, progress planarization for the first time is identical with the technique that second of planarization of the progress uses, specifically
Include:
It is planarized using chemical mechanical milling tech.
Preferably, first barrier layer is identical with the material on second barrier layer and the first sub- lamination,
For SiN or polysilicon.
Preferably, second barrier layer with a thickness ofIncluding endpoint value.
The present invention also provides another three-dimensional storage flattening methods, applied to the production of three-dimensional storage, described three
Tieing up memory includes substrate, and the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at institute
It states between peripheral region and the nucleus, is directed toward the spaciousness that the nucleus direction is set gradually along the peripheral region
Region and stepped area;Step structure is formed on the stepped area substrate;Be formed on the nucleus substrate including
First sub- lamination and the cross layered laminated construction of the second sub- lamination, and the laminated construction is the away from the surface of the substrate
One barrier layer;
The three-dimensional storage flattening method includes:
Deposited oxide layer makes surface and the first barrier layer court of the oxide layer of the depletion region away from the substrate
It is flushed to the surface of the substrate;
The oxide layer for removing the peripheral region makes surface and institute of the oxide layer of the peripheral region away from the substrate
The oxide layer for stating depletion region is flushed away from the surface of the substrate;
Remove the oxide layer of the nucleus;
In the oxide layer of the peripheral region, the depletion region and the stepped area and the nucleus
The first barrier layer on form the second barrier layer;
First time planarization is carried out, the peripheral region, the depletion region, the stepped area and the core space are made
The surface in domain flushes to second barrier layer surface for deviating from the substrate;
Remove the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the nucleus
First barrier layer;
It carries out second to planarize, makes the peripheral region, the depletion region, the stepped area and the core space
The surface in domain flushes the surface that the depletion region oxide layer deviates from the substrate.
Preferably, progress planarization for the first time is identical with the technique that second of planarization of the progress uses, specifically
Include:
It is planarized using chemical mechanical milling tech.
Preferably, first barrier layer is identical with the material on second barrier layer and the first sub- lamination,
For SiN or polysilicon.
Preferably, second barrier layer with a thickness ofIncluding endpoint value.
The present invention also provides a kind of three-dimensional storages, using three-dimensional storage flattening method described in any of the above one
Production is formed;
The three-dimensional storage includes:
Substrate, the substrate are divided into nucleus and surround the peripheral region of the nucleus, and are located at described outer
It encloses between region and the nucleus, is directed toward the depletion region that the nucleus direction is set gradually along the peripheral region
And stepped area;Step structure is formed on the stepped area substrate;It is formed on the nucleus substrate including first
Sub- lamination and the cross layered laminated construction of the second sub- lamination;
The oxide layer of the substrate is covered, the oxide layer planarizes the difference in height of the nucleus Yu other regions,
And the oxide layer is flat surface away from the surface of the substrate.
Preferably, the first sub- lamination in the laminated construction of the nucleus of the three-dimensional storage be SiN or polysilicon,
Second sub- lamination is SiO2。
It can be seen via above technical scheme that three-dimensional storage production method provided by the invention, planarisation step it
Before, it is controlled by oxidated layer thickness, and increase the first barrier layer of setting with nucleus in depletion region and peripheral region
The second barrier layer flushed, since the removal speed on barrier layer is slower than the removal speed of oxide layer, on the one hand, stop
Layer can protect the laminated construction of nucleus, avoids the influence as caused by excessive grinding in the prior art, improves three-dimensional and deposit
Reservoir integrated artistic uniformity improves yield;On the other hand, barrier layer can protect peripheral region and depletion region,
Avoid the occurrence of recess.Simultaneously as the major part of the nucleus of device, depletion region and peripheral region is blocked layer guarantor
Shield, the only juncture area of peripheral region and depletion region and the protrusion of stepped area are flattened, so that planarization
Time greatly shortens, and improves element manufacturing efficiency.
The present invention also provides a kind of three-dimensional storages, are made to be formed of above-mentioned flattening method, due to flatening process
The defects of changing, damaging so as to avoid the oxide layer residual and nucleus of nucleus, improves wafer yield;Simultaneously also
The recess of peripheral region and stepped area can be improved, reduce the influence to subsequent metal connecting line technics.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Figure 1A-Fig. 1 C is prior art three-dimensional storage flatening process schematic cross-section;
Fig. 2A-Fig. 2 C is defect schematic diagram existing for three-dimensional storage flatening process in the prior art;
Fig. 3 is a kind of three-dimensional storage flattening method flow chart provided in an embodiment of the present invention;
Fig. 4 A- Fig. 4 G is a kind of three-dimensional storage flatening process schematic cross-section provided in an embodiment of the present invention;
Fig. 5 is another three-dimensional storage flattening method flow chart provided in an embodiment of the present invention;
Fig. 6 A- Fig. 6 B is another three-dimensional storage flattening method technique section signal provided in an embodiment of the present invention
Figure.
Specific embodiment
Just as described in the background section, three-dimensional storage lapping uniformity in prior art planarization process is poor,
Wafer segment region has the defects of core space caused by oxide layer residual caused by grinding deficiency or grinding excess damages, right
Subsequent channel etching and Metal Bonding Technology impact.
Specifically, three-dimensional storage after nucleus is formed, can form biggish difference in height with peripheral region, to avoid
Follow-up process is influenced, needs filling oxide layer to be planarized again with the method for chemical mechanical grinding, in conjunction with Figure 1A-Fig. 1 C, mesh
Preceding flattening method is as follows:
Deposited oxide layer, usually silica (SiO2);A referring to Figure 1, substrate 01 peripheral region P (Peri),
Equal deposited oxide layer 02 on depletion region O (Open), stepped area S (Stair) and nucleus C (Core), wherein core space
It include laminated construction 03 on the C of domain, top layer (i.e. outermost layer of the laminated construction away from substrate) is silicon nitride layer, after can be used as
Continuous chemical mechanical grinding barrier layer.
The oxide layer of nucleus is etched into a part;B referring to Figure 1, only etching removes the part oxygen on nucleus C
Change layer, and retains a part of oxide layer.
Chemical mechanical grinding is parked in nucleus laminated top silicon nitride barrier 031, determines nucleus by measuring
Oxide layer above stops grinding after being abraded away totally.C referring to Figure 1, using the top layer silicon nitride of nucleus C as blocking
Layer stops grinding, to planarize the semi-finished product of three-dimensional storage.
But, on the one hand, since chemical mechanical grinding rate is unstable, need repeatedly to measure to determine nucleus oxide layer
Whether it has been milled away, has caused existing flatening process efficiency lower;On the other hand, because lapping uniformity is poor, wafer
Partial region has oxide layer 02 caused by grinding deficiency and remains, and refers to Fig. 2A;Or nucleus caused by grinding excess
Laminated construction 03 damages the defects of (referring to Fig. 2 B), impacts to subsequent channel etching and Metal Bonding Technology.Again
On the one hand, technique is protected since peripheral region P and stepped area S lacks at present, and there are depression defect (referring to Fig. 2 C), to rear
Continuous Metal Bonding Technology impacts.
Based on this, the present invention provides a kind of three-dimensional storage flattening method, so that chemical mechanical milling tech difficulty drops
Low, working hour shortens.The defects of avoiding oxide layer residual and nucleus from damaging, improves wafer yield;It simultaneously can also be to periphery
The recess of region and stepped area is improved, and the influence to subsequent metal connecting line technics is reduced.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
A kind of three-dimensional storage flattening method, applied to the production of three-dimensional storage, the three-dimensional storage includes lining
Bottom, the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at the peripheral region and institute
It states between nucleus, is directed toward the depletion region and stepped region that the nucleus direction is set gradually along the peripheral region
Domain;Step structure is formed on the stepped area substrate;Be formed on the nucleus substrate including the first sub- lamination and
The cross layered laminated construction of second sub- lamination, and the laminated construction is the first barrier layer away from the surface of the substrate;
Fig. 3 is referred to, the three-dimensional storage flattening method includes:
S101: deposited oxide layer makes surface and first resistance of the oxide layer of the depletion region away from the substrate
The surface of barrier towards the substrate flushes;
Fig. 4 A is referred to, in the present embodiment before deposited oxide layer 13, the peripheral region P on substrate 11 is produced
Necessary peripheral region structure (details is not showed that in figure) and laminated construction 12, this implementation are produced on nucleus C
Laminated construction 12 includes the first sub- lamination 121 and the second sub- lamination 122 in example, and the first sub- lamination 121 and the second sub- lamination 122 are handed over
Fork stacking, forms laminated construction 12.
It should be noted that the specific material of the first sub- lamination 121 and the second sub- lamination 122 is not limited in the present embodiment,
After as long as the two can be individually selected the property being etched away during meeting wet etching, and the first sub- lamination can be used as
The barrier layer of continuous technique, that is, when needing to be etched away the second sub- lamination, will not impact the first sub- lamination, or carve
When etching off removes the first sub- lamination, the second sub- lamination will not be impacted.It is carved since silicon nitride or polysilicon and silica have
It is different to lose rate, and it is relatively easy to draw materials, optional in the present embodiment, the material of the first sub- lamination 121 is silicon nitride (SiN)
Or polysilicon;And the material of the second sub- lamination 122, it is optionally identical as the material of oxide layer, it is silica (SiO2).In this hair
In bright other embodiments, the first sub- lamination and the second sub- lamination can also be other materials, not limit in the present embodiment this
It is fixed.
In the present embodiment, laminated construction 12 is in the first barrier layer 121A namely the present embodiment away from the surface of substrate 11
First barrier layer 121A is the first sub- lamination, silicon nitride (SiN) or polysilicon layer.The subsequent first sub- lamination is as resistance for convenience
Barrier, the thickness of the first barrier layer 121A can be some compared to the thickness thickness of other the first sub- laminations in the present embodiment.
Deposited oxide layer in this step is complete in peripheral region P, depletion region O, stepped area S and nucleus C
At the oxide deposition carried out after necessary structure.Since oxide layer uses depositing operation, the oxidation thickness of various pieces
It spends identical.
The specific thickness of oxide layer is not limited in the present embodiment, what needs to be satisfied is that, the oxide layer 13 at depletion region O is carried on the back
Surface and nucleus C superimposed layer structure 12 (not including the first barrier layer of top) from substrate 11 deviate from the table of substrate 11
Face flushes.That is, as shown in Figure 4 A, the thickness of oxide layer 13 meets in the present embodiment, the oxide layer 13 of depletion region O is away from lining
The surface at bottom 11 is flushed with the lower surface of the first barrier layer 121A of nucleus C, as shown in dotted line in Fig. 4 A.
S102: removing the oxide layer of the peripheral region, and the oxide layer of the peripheral region is made to deviate from the table of the substrate
Face is flushed with the oxide layer of the depletion region away from the surface of the substrate;
The concrete technology for not limiting the oxide layer of removal peripheral region in the present embodiment optionally removes peripheral region
The technique that oxide layer uses is hard mask etching technique.It should be noted that the oxidated layer thickness due to removal is identical,
The oxide layer of sloping portion in the present embodiment at the boundary position of peripheral region P and depletion region O is not removed.Also protect
A wedge angle is stayed, as shown in J in Fig. 4 B.
S103: the second barrier layer is formed in all oxide layers;
As shown in Figure 4 C, the second barrier layer 14 is formed in oxide layer 13, the second barrier layer 14 is using heavy in the present embodiment
Product method is formed, and the second barrier layer 14 covers the position where entire oxide layer 13.The second blocking is not limited in the present embodiment
The thickness of layer 14, optionally, the thickness on the second barrier layer 14 can protect peripheral region and depletion region to grind in chemical machinery
It will not be damaged when mill.It should be noted that subsequent milling time needs are longer when the thickness on the second barrier layer 14 is too thick, therefore,
In the present embodiment, optionally, second barrier layer with a thickness ofIncluding endpoint value.
The material on the second barrier layer is not limited in the present embodiment, the material on the second barrier layer can be with the material on the first barrier layer
Matter is identical, can not also be identical, and optionally, the second barrier layer material is identical as the first barrier layer material, is silicon nitride or more
Crystal silicon.
S104: the second barrier layer of the nucleus and the oxide layer of the nucleus are removed;
Refer to Fig. 4 D, in the present embodiment by etching technics by nucleus C the second barrier layer 14 and oxide layer
13 removals.With first pass through etched portions nucleus oxide layer in the prior art, then grind the whole nucleus oxygen of removal again
Unlike the step of changing layer, the oxide layer 13 in the present embodiment on nucleus C is all removed using etching technics, etches oxygen
Change layer to the first barrier layer of nucleus C to end.In etching process, core can be grabbed by analyzing the ingredient of reactant
Region first stops layer signal to avoid oxide layer from remaining to determine whether to etch the oxide layer of nucleus completely.
S105: carrying out first time planarization, makes the peripheral region, the depletion region, the stepped area and described
The surface of nucleus flushes to second barrier layer surface for deviating from the substrate;
Fig. 4 E is referred to, after by oxide layer removal most of on entire substrate, using flatening process by all protrusions
It is planarized with the part on the first barrier layer and the second barrier layer, it is unlimited in the present embodiment to determine flatening process specific method, it is optional
, it is planarized using chemical mechanical milling tech.
As shown in Figure 4 E, by the of the second barrier layer 14 of stepped area S in Fig. 4 D and oxide layer 13 and pointed part
Two barrier layers and oxide layer are removed using chemical mechanical milling tech.Due to need chemical mechanical grinding remove region relative to
For the region (B referring to Figure 1) for needing chemical mechanical grinding to remove in the prior art, milling area is smaller, therefore, Neng Gou great
It is big to shorten chemical mechanical polishing time.
And since peripheral region and depletion region also have barrier layer to be protected, thus in chemical mechanical planarization process
In, it is not in depression problem.Because region area is smaller and milling time is short, recess can also be changed stepped area well
It is kind.
S106: the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the core are removed
First barrier layer in region;
Fig. 4 F is referred to, all first barrier layers and the second barrier layer are removed.After removal, not by the first barrier layer and
Two barrier layer protected regions and with there are a lesser height between the barrier layer protected region in the first barrier layer and second
It is poor to spend.
S107: carrying out second and planarize, and makes the peripheral region, the depletion region, the stepped area and described
The surface of nucleus flushes the surface that the depletion region oxide layer deviates from the substrate.
Fig. 4 G is referred to, is planarized by second, difference in height described in removal process S106.It is optional in the present embodiment
, second, which is carried out, using chemical mechanical grinding planarizes.Since the difference in height is smaller, milling time is shorter, even if not hindering
The defects of recess, will not occur in barrier protection.
Three-dimensional storage production method provided by the invention is controlled before planarisation step by oxidated layer thickness, with
And increase the second barrier layer that setting is flushed with the first barrier layer of nucleus in depletion region and peripheral region, due to stopping
The removal speed of layer is slower than the removal speed of oxide layer, therefore, on the one hand, barrier layer can protect the lamination knot of nucleus
Structure avoids the influence as caused by excessive grinding in the prior art, improves three-dimensional storage integrated artistic uniformity, improve good
Rate;On the other hand, barrier layer can protect peripheral region and depletion region, avoid the occurrence of recess.Simultaneously as device
Nucleus, depletion region and peripheral region major part be blocked layer protection, only peripheral region and depletion region
The protrusion of juncture area and stepped area is flattened, so that the planarization time greatly shortens, improves element manufacturing
Efficiency.
Further, in first time planarization process, since chemical mechanical grinding area reduces, and there are barrier layer,
So that chemical mechanical milling tech difficulty reduces, and then shortens grinding working hour, element manufacturing efficiency is improved.
The embodiment of the present invention also provides another three-dimensional storage flattening method, the system applied to three-dimensional storage
To make, the three-dimensional storage includes substrate, and the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, with
And between the peripheral region and the nucleus, the nucleus direction is directed toward along the peripheral region and is successively set
The depletion region and stepped area set;Step structure is formed on the stepped area substrate;Shape on the nucleus substrate
At there is a laminated construction cross layered including the first sub- lamination and the second sub- lamination, and the laminated construction is away from the substrate
Surface is the first barrier layer;
Fig. 5 is referred to, the three-dimensional storage flattening method includes:
S201: deposited oxide layer makes surface and first resistance of the oxide layer of the depletion region away from the substrate
The surface of barrier towards the substrate flushes;
S202: removing the oxide layer of the peripheral region, and the oxide layer of the peripheral region is made to deviate from the table of the substrate
Face is flushed with the oxide layer of the depletion region away from the surface of the substrate;
S203: the oxide layer of the nucleus is removed;
S204: in the oxide layer of the peripheral region, the depletion region and the stepped area and the core
The second barrier layer is formed on first barrier layer in region;
S205: carrying out first time planarization, makes the peripheral region, the depletion region, the stepped area and described
The surface of nucleus flushes to second barrier layer surface for deviating from the substrate;
S206: the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the core are removed
First barrier layer in region;
S207: carrying out second and planarize, and makes the peripheral region, the depletion region, the stepped area and described
The surface of nucleus flushes the surface that the depletion region oxide layer deviates from the substrate.
Unlike a upper embodiment, step S203 and step S204;Specifically, on the basis of Fig. 4 B, figure is referred to
6A first removes the oxide layer 23 of nucleus C, exposes the first barrier layer 221A on nucleus C, ibid embodiment, this
The oxide layer 23 removed on nucleus C in embodiment is all removed using etching technics, etching oxidation layer to core space
End on the first barrier layer of domain C.In etching process, it can be stopped by analyzing the ingredient of reactant to grab nucleus first
Layer signal avoids oxide layer from remaining to determine whether to etch the oxide layer of nucleus completely.
Fig. 6 B is referred to, in the oxide layer 23 of the peripheral region P, the depletion region O and the stepped area S,
And the second barrier layer 24 is formed on the first barrier layer 221A of the nucleus C;The second barrier layer 24 is adopted in the present embodiment
It is formed with deposition method, and the second barrier layer 24 covers the position where entire oxide layer 23.Second is not limited in the present embodiment
The thickness on barrier layer 24, optionally, the thickness on the second barrier layer 24 can protect peripheral region and depletion region in chemical machine
Tool will not damage when grinding.It should be noted that subsequent milling time needs are longer when the thickness on the second barrier layer 24 is too thick,
Therefore, in the present embodiment, optionally, second barrier layer with a thickness ofIncluding endpoint value.
The material on the second barrier layer is not limited in the present embodiment, the material on the second barrier layer can be with the material on the first barrier layer
Matter is identical, can not also be identical, and optionally, the second barrier layer material is identical as the first barrier layer material, is silicon nitride or more
Crystal silicon.
Three-dimensional storage production method provided by the invention is controlled before planarisation step by oxidated layer thickness, with
And increase the second barrier layer that setting is flushed with the first barrier layer of nucleus in depletion region and peripheral region, due to stopping
The removal speed of layer is slower than the removal speed of oxide layer, therefore, on the one hand, barrier layer can protect the lamination knot of nucleus
Structure avoids the influence as caused by excessive grinding in the prior art, improves three-dimensional storage integrated artistic uniformity, improve good
Rate;On the other hand, barrier layer can protect peripheral region and depletion region, avoid the occurrence of recess.Simultaneously as device
Nucleus, depletion region and peripheral region major part be blocked layer protection, only peripheral region and depletion region
The protrusion of juncture area and stepped area is flattened, so that the planarization time greatly shortens, improves element manufacturing
Efficiency.
Further, in first time planarization process, since chemical mechanical grinding area reduces, and there are barrier layer,
So that chemical mechanical milling tech difficulty reduces, and then shortens grinding working hour, element manufacturing efficiency is improved.
On the basis of the above embodiments, the present embodiment additionally provides a kind of three-dimensional storage, which passes through above-mentioned
Three-dimensional storage flattening method is formed, and Fig. 4 G is referred to, and the three-dimensional storage includes:
Substrate 11, substrate 11 divides for nucleus C and surrounds the peripheral region P of nucleus C, and is located at peripheral region
Between P and nucleus C, peripherally region P is directed toward the depletion region O and stepped area S that the direction nucleus C is set gradually;
Step structure is formed on stepped area S substrate;It is formed on nucleus C substrate including the first sub- lamination 121 and the second son
The cross layered laminated construction 12 of lamination 122;
Cover the oxide layer 13 of substrate 11, oxide layer 13 planarize nucleus C and other regions (including peripheral region P,
Depletion region O and stepped area S) difference in height, and oxide layer 13 away from substrate 11 surface be flat surface.Oxide layer 13 passes through
The flattening method crossed in above example makes to form the consistent oxide layer of each region height.
The present invention also provides a kind of three-dimensional storages, are made to be formed of above-mentioned flattening method, due to flatening process
The defects of changing, damaging so as to avoid the oxide layer residual and nucleus of nucleus, improves wafer yield;Simultaneously also
The recess of peripheral region and stepped area can be improved, reduce the influence to subsequent metal connecting line technics.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of three-dimensional storage flattening method, which is characterized in that applied to the production of three-dimensional storage, the three-dimensional storage
Device includes substrate, and the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at the periphery
Between region and the nucleus, along the peripheral region be directed toward depletion region that the nucleus direction is set gradually and
Stepped area;Step structure is formed on the stepped area substrate;It is formed on the nucleus substrate including the first son
Lamination and the cross layered laminated construction of the second sub- lamination, and the laminated construction is first to stop away from the surface of the substrate
Layer;
The three-dimensional storage flattening method includes:
In the peripheral region of the substrate, depletion region, stepped area and nucleus deposited oxide layer, make the depletion region
Oxide layer flushed away from the surface of the substrate with the surface of the first barrier layer towards the substrate;
The oxide layer for removing the part peripheral region, makes the removal portion of oxide layer back of the peripheral region from the substrate
Surface and the oxide layer of the depletion region flushed away from the surface of the substrate;
Second is formed in the oxide layer on the peripheral region of the substrate, depletion region, stepped area and nucleus to stop
Layer;
Remove the second barrier layer of the nucleus and the oxide layer of the nucleus;
First time planarization is carried out, the peripheral region, the depletion region, the stepped area and the nucleus are made
Surface flushes to the second barrier layer of the depletion region surface for deviating from the substrate;
Remove the first of the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the nucleus
Barrier layer;
It carries out second to planarize, flushes the surface of the peripheral region, the stepped area and the nucleus described
Depletion region oxide layer deviates from the surface of the substrate.
2. three-dimensional storage flattening method according to claim 1, which is characterized in that the progress first time planarization
It is identical with the technique that second of planarization of the progress uses, it specifically includes:
It is planarized using chemical mechanical milling tech.
3. three-dimensional storage flattening method according to claim 1, which is characterized in that first barrier layer and described
The material of second barrier layer and the first sub- lamination is identical, is SiN or polysilicon.
4. three-dimensional storage flattening method according to claim 1, which is characterized in that the thickness on second barrier layer
ForIncluding endpoint value.
5. a kind of three-dimensional storage flattening method, which is characterized in that applied to the production of three-dimensional storage, the three-dimensional storage
Device includes substrate, and the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at the periphery
Between region and the nucleus, along the peripheral region be directed toward depletion region that the nucleus direction is set gradually and
Stepped area;Step structure is formed on the stepped area substrate;It is formed on the nucleus substrate including the first son
Lamination and the cross layered laminated construction of the second sub- lamination, and the laminated construction is first to stop away from the surface of the substrate
Layer;
The three-dimensional storage flattening method includes:
In the peripheral region of the substrate, depletion region, stepped area and nucleus deposited oxide layer, make the depletion region
Oxide layer flushed away from the surface of the substrate with the surface of the first barrier layer towards the substrate;
The oxide layer for removing the part peripheral region, makes the removal portion of oxide layer back of the peripheral region from the substrate
Surface and the oxide layer of the depletion region flushed away from the surface of the substrate;
Remove the oxide layer of the nucleus;
In the oxide layer of the peripheral region, the depletion region and the stepped area and the nucleus
The second barrier layer is formed on one barrier layer;
First time planarization is carried out, the peripheral region, the depletion region, the stepped area and the nucleus are made
Surface flushes to the second barrier layer of the depletion region surface for deviating from the substrate;
Remove the first of the second barrier layer of the peripheral region, the second barrier layer of the depletion region and the nucleus
Barrier layer;
It carries out second to planarize, flushes the surface of the peripheral region, the stepped area and the nucleus described
Depletion region oxide layer deviates from the surface of the substrate.
6. three-dimensional storage flattening method according to claim 5, which is characterized in that the progress first time planarization
It is identical with the technique that second of planarization of the progress uses, it specifically includes:
It is planarized using chemical mechanical milling tech.
7. three-dimensional storage flattening method according to claim 5, which is characterized in that first barrier layer and described
The material of second barrier layer and the first sub- lamination is identical, is SiN or polysilicon.
8. three-dimensional storage flattening method according to claim 5, which is characterized in that the thickness on second barrier layer
ForIncluding endpoint value.
9. a kind of three-dimensional storage, which is characterized in that using three described in claim 1-4 any one or 5-8 any one
Dimension memory flattening method makes to be formed;
The three-dimensional storage includes:
Substrate, the substrate is divided into nucleus and surrounds the peripheral region of the nucleus, and is located at the external zones
Between domain and the nucleus, the depletion region and platform that the nucleus direction is set gradually are directed toward along the peripheral region
Rank region;Step structure is formed on the stepped area substrate;It is formed on the nucleus substrate folded including the first son
Layer and the cross layered laminated construction of the second sub- lamination;
The oxide layer of the substrate is covered, the oxide layer planarizes the difference in height of the nucleus Yu other regions, and institute
It is flat surface that oxide layer, which is stated, away from the surface of the substrate.
10. three-dimensional storage according to claim 9, which is characterized in that the nucleus of the three-dimensional storage is folded
The first sub- lamination in layer structure is SiN or polysilicon, and the second sub- lamination is SiO2。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710771687.2A CN107578996B (en) | 2017-08-31 | 2017-08-31 | A kind of three-dimensional storage and its flattening method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710771687.2A CN107578996B (en) | 2017-08-31 | 2017-08-31 | A kind of three-dimensional storage and its flattening method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107578996A CN107578996A (en) | 2018-01-12 |
CN107578996B true CN107578996B (en) | 2019-02-22 |
Family
ID=61030960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710771687.2A Active CN107578996B (en) | 2017-08-31 | 2017-08-31 | A kind of three-dimensional storage and its flattening method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107578996B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109920791B (en) * | 2019-03-15 | 2021-05-04 | 长江存储科技有限责任公司 | 3D NAND memory device and manufacturing method thereof |
CN110137177B (en) * | 2019-06-18 | 2021-07-20 | 长江存储科技有限责任公司 | Memory and forming method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1705129A (en) * | 2004-05-31 | 2005-12-07 | 海力士半导体有限公司 | Semiconductor device with flowable insulation layer formed on capacitor and method for fabricating the same |
US9449987B1 (en) * | 2015-08-21 | 2016-09-20 | Sandisk Technologies Llc | Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors |
CN106024798A (en) * | 2015-03-31 | 2016-10-12 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
CN106876263A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | A kind of chemical and mechanical grinding method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120030193A (en) * | 2010-09-17 | 2012-03-28 | 삼성전자주식회사 | Method for manufacturing three dimensional semiconductor device |
KR20120047325A (en) * | 2010-11-01 | 2012-05-11 | 삼성전자주식회사 | Three dimensional semiconductor device and method for manufacturing the same |
US8759899B1 (en) * | 2013-01-11 | 2014-06-24 | Macronix International Co., Ltd. | Integration of 3D stacked IC device with peripheral circuits |
-
2017
- 2017-08-31 CN CN201710771687.2A patent/CN107578996B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1705129A (en) * | 2004-05-31 | 2005-12-07 | 海力士半导体有限公司 | Semiconductor device with flowable insulation layer formed on capacitor and method for fabricating the same |
CN106024798A (en) * | 2015-03-31 | 2016-10-12 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method of fabricating the same |
US9449987B1 (en) * | 2015-08-21 | 2016-09-20 | Sandisk Technologies Llc | Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors |
CN106876263A (en) * | 2017-03-07 | 2017-06-20 | 长江存储科技有限责任公司 | A kind of chemical and mechanical grinding method |
Also Published As
Publication number | Publication date |
---|---|
CN107578996A (en) | 2018-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7452817B2 (en) | CMP method providing reduced thickness variations | |
CN106876263A (en) | A kind of chemical and mechanical grinding method | |
CN102814727B (en) | Method for chemically and mechanically grinding shallow trench isolation structure | |
CN106115612B (en) | A kind of wafer planarization method | |
CN107578996B (en) | A kind of three-dimensional storage and its flattening method | |
JP3683705B2 (en) | How to fill shallow trenches | |
CN107845636A (en) | A kind of preparation method of Flash wafers | |
CN106672892A (en) | Method for reducing depressed deformation of sacrificial layer in three-dimensional stacking in chemical mechanical polishing | |
JP4202826B2 (en) | Chemical mechanical polishing method of organic film and manufacturing method of semiconductor device | |
CN107591407A (en) | A kind of 3D nand memories and its manufacture method | |
CN102339741A (en) | Groove structure filled with metal and forming method thereof, and chemical mechanical polishing method | |
CN102437047B (en) | Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method | |
CN104078346A (en) | Planarization method for semi-conductor device | |
CN111584419A (en) | Method for forming trench isolation structure and trench isolation structure | |
US20080318420A1 (en) | Two step chemical mechanical polish | |
CN104576539B (en) | Method for forming semiconductor structure | |
CN102361022A (en) | Method for manufacturing embedded flash memory | |
CN104269353B (en) | One kind planarization preprocess method | |
CN105914143A (en) | Chemico-mechanical polishing planarization method | |
Rhoades et al. | Advances in CMP for TSV Reveal | |
TWI473155B (en) | Process method for planarizing a semiconductor device | |
CN103972093B (en) | The preparation method that fin formula field effect transistor sacrifices grid | |
CN106430080A (en) | Production method for MEMS wide-groove and low-step structure | |
CN103128648A (en) | Chemical machinery lapping device and method of processing crystal plates in lapping process | |
CN109817571A (en) | A kind of preparation method of planarization process method and three-dimensional storage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |