CN105990130A - Planarization method - Google Patents
Planarization method Download PDFInfo
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- CN105990130A CN105990130A CN201510056936.0A CN201510056936A CN105990130A CN 105990130 A CN105990130 A CN 105990130A CN 201510056936 A CN201510056936 A CN 201510056936A CN 105990130 A CN105990130 A CN 105990130A
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Abstract
The present invention provides a planarization method. According to the planarization method, a second filling layer is adopted to replace photoresist adopted in a traditional reverse process to cover the surfaces of a first filling layer; the second filling layer outside second recesses in the first filling layer is removed through first chemical mechanical polishing; with the second filling layer inside the second recesses adopted as a mask, most of the first filling layer is removed through adopting first etching; after the second filling layer inside the second recesses is removed, the residual first filling layer is removed through second chemical mechanical polishing; and therefore, a serious load effect generated by the chemical mechanical polishing process can be avoided, and process cost can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of flattening method.
Background technology
In existing semiconductor device manufactures, in order to obtain planarizing surface, often use chemical mechanical milling tech.Change
Learning mechanical milling tech mainly utilizes the chemical action of lapping liquid and the physical action of grinding head rotation to make to be ground object
Obtain comprehensive planarization.
In actual applications, cmp is easily subject to grind the impact of object and load effect occur.Concrete,
Surface is formed with to the wafer of depression, due to the density of surface indentation formation, the recessed openings area phase not to the utmost of wafer
With, so that the grinding rate carrying out crystal column surface zones of different during cmp is different.In general, grand
In sight, the region grinding rate little for depression density is relatively slow, and the region grinding rate that depression density is big is very fast；Microcosmic
On, the grinding rate of the depression depression less than aperture area that aperture area is big is fast；Thus result in the product of load effect
Raw, make the surface after cmp form the non-planarization effect not being expected to.Further, chemical machinery is needed
Grinding the volume removed the most, the time of required processing procedure is the longest, and its load effect produced is the most serious.
For the load effect of above-mentioned appearance, prior art proposes the reverse process (reverse) utilizing photoresist, as
Shown in Fig. 1 a-1e.First, as shown in Figure 1a, it is provided that semiconductor base 10 to be ground, described semiconductor base
The first depression 11 it is formed with, in semiconductor base 10 surface deposition packed layer 12 to cover semiconductor base 10 on 10
Surface, described packed layer 12 surface is formed with the second depression 13；As shown in Figure 1 b, in described second depression 13
Forming patterning photoresist 14, to fill described second depression 13, this process those skilled in the art can be first in filling out
Fill layer 12 surface and form photoresist layer, utilize light shield that photoresist is exposed, so that photoresist layer pattern, thus
Form the patterning photoresist 14 filling the second depression 13；As illustrated in figure 1 c, with described patterning photoresist 14 it is
Mask, performs etching, and to expose described semiconductor base 10 surface, then, as shown in Figure 1 d, institute is removed in ashing
State patterning photoresist 14；Finally, as shown in fig. le, remaining packed layer 12 ' is carried out cmp.By
In having eliminated most packed layer 12, therefore, profit using patterning photoresist as the process that mask performs etching
During removing remaining packed layer 12 ' with cmp, affected the least by load effect, the most permissible
Obtain desired flattening effect.
But, utilize the reverse process of existing photoresist to form photoresist layer due to needs, and need to be fabricated separately
It is applicable to the light shield of reverse process, adds process costs undoubtedly.
Summary of the invention
For solving the problems referred to above, the invention provides a kind of flattening method, produce avoiding chemical mechanical milling tech
Serious load effect while, reduce process costs.
The invention provides a kind of flattening method, including:
Thering is provided semiconductor base to be ground, described semiconductor base is formed with the first depression；
The first packed layer, described first packed layer is become to be filled up completely with in described semiconductor base overlying cap-shaped described first recessed
Fall into, and, described first packed layer is formed with the second depression of corresponding described first recessed position；
Depositing the second packed layer in described first packed layer surface, described second packed layer is filled up completely with described second depression,
And cover described first packed layer surface；
Perform cmp for the first time, to expose described first packed layer surface；
Perform etching for the first time, to remove the first packed layer exposed；
Perform second time etching and remove remaining second packed layer；
Perform second time cmp, to remove remaining first packed layer；
Wherein, the material of described first packed layer is different from the material of described second packed layer；Described second packed layer
Material selects in high cmp in described first time cmp relative to the material of the first packed layer
Ratio；The material of described second packed layer presents low quarter relative to the material of the first packed layer in described first time etches
Erosion selects ratio；The material of described second packed layer presents in described second time etches relative to the material of the first packed layer
High etching selection ratio.
Further, the described semiconductor substrate surface in addition to described first sunk surface is formed with barrier layer.
Further, the material of described first packed layer is silicon dioxide, and the material of described second packed layer is polysilicon.
Further, etching of described first time uses plasma etching, and etching gas includes C4F8, Ar, CO and O2。
Further, described second time etching uses plasma etching, and etching gas includes HBr, He and HeO2。
Further, the material on described barrier layer is silicon nitride or silicon oxynitride.
Use the flattening method that the present invention provides, the second packed layer the photoresist substituted in traditional reverse process covers
It is placed on the first packed layer surface, removes in the first packed layer the beyond the second depression by first time cmp
Two packed layers, and with the second packed layer in the second depression as mask, utilize etching for the first time to remove most first
Packed layer, after the second packed layer in removing the second depression, removes remaining the by second time cmp
One packed layer, thus while the serious load effect avoiding chemical mechanical milling tech to produce, reduces technique
Cost.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the structural representation of reverse process flow process in prior art；
Fig. 2 is the application flattening method schematic flow sheet；
Fig. 3 a-3f is the flowage structure schematic diagram of the application flattening method exemplary embodiments.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, develop simultaneously embodiment referring to the drawings,
The present invention is described in further detail.
The invention provides the manufacture method of a kind of semiconductor device, as in figure 2 it is shown, include:
Thering is provided semiconductor base to be ground, described semiconductor base is formed with the first depression；
The first packed layer, described first packed layer is become to be filled up completely with in described semiconductor base overlying cap-shaped described first recessed
Fall into, and, described first packed layer is formed with the second depression of corresponding described first recessed position；
Depositing the second packed layer in described first packed layer surface, described second packed layer is filled up completely with described second depression,
And cover described first packed layer surface；
Perform cmp for the first time, to expose described first packed layer surface；
Perform etching for the first time, to remove the first packed layer exposed；
Perform second time etching and remove remaining second packed layer；
Perform second time cmp, to remove remaining first packed layer；
Wherein, the material of described first packed layer is different from the material of described second packed layer；Described second packed layer
Material selects in high cmp in described first time cmp relative to the material of the first packed layer
Ratio；The material of described second packed layer presents low quarter relative to the material of the first packed layer in described first time etches
Erosion selects ratio；The material of described second packed layer presents in described second time etches relative to the material of the first packed layer
High etching selection ratio.
Below in conjunction with Fig. 3 a to Fig. 3 e, the exemplary embodiments of the application flattening method is described in detail:
As shown in Figure 3 a, it is provided that semiconductor base 20, semiconductor base 20 is formed with the first depression 21；Preferably,
Quasiconductor 20 becomes to have barrier layer 22, using barrier layer 22 as subsequent etching and chemistry in the first depression 21 surface topography
The stop-layer of mechanical lapping；Semiconductor base 20 overlying cap-shaped becomes the first packed layer 23, the first packed layer 23 to fill out completely
Fill the first depression 21, owing to semiconductor base 20 is formed with the first depression, such pattern based on semiconductor base 20,
The first packed layer 23 being covered on semiconductor base 20 is also formed with the second depression of corresponding described first recessed position
24；As preferably, the material of the first packed layer 23 is preferably silicon dioxide；
As shown in Figure 3 b, depositing the second packed layer 25 in the first packed layer 23 surface, the second packed layer 25 is filled out completely
Fill the second depression 24, and cover the first packed layer 23 surface；As preferably, the material of the second packed layer 25 is preferred
For polysilicon；
As shown in Figure 3 c, cmp for the first time is performed, to expose the first packed layer 23 surface；For the first time
In chemical mechanical planarization process, the material of the first packed layer 23 and the second packed layer 25 need to meet following condition, and i.e.
The material of two packed layers grinds in high chemical machinery in first time cmp relative to the material of the first packed layer
Mill selects ratio, and the material as described previously for the first packed layer 23 is silicon dioxide, the material of the second packed layer 25
For the situation of polysilicon, existing cmp carries out chemistry machine using milling apparatus and lapping liquid to polysilicon
When tool grinds, due to lapping liquid not with silicon dioxde reaction, therefore, the meeting when carrying out for the first time cmp
Occurring that cmp selects than higher than the grinding selectivity ratio of polysilicon, in other words, the i.e. first packed layer 23 is the
Cmp serves the effect of cmp stop-layer.
As shown in Figure 3 d, perform etching for the first time, to remove the first packed layer 23 exposed；The most etched
Cheng Zhong, the material of the first packed layer 23 and the second packed layer 25 need to meet following condition, the i.e. second packed layer further
The material of 25 presents low etching selection ratio relative to the material of the first packed layer 23 in etching for the first time；As above institute
State, when the material of the first packed layer 23 is silicon dioxide, and the material of the second packed layer 25 is polysilicon, preferably adopt
With plasma etching, the etching gas of employing is C4F8, Ar, CO and O2, utilizes above-mentioned etching gas, due to
The material of second layer packed layer 25 is silicon dioxide, therefore, in first time etching process, is seldom consumed, and it is carved
Erosion selects the ratio silicon dioxide less than the first packed layer 23, and remaining second packed layer 25 ' is in first time etching process
Act as etch mask；In preferred scheme, the material on the barrier layer that semiconductor base 20 surface is formed is preferably
Silicon nitride or silicon oxynitride, the etching gas used for etching of above-mentioned first time, silicon nitride can stop semiconductor-based
The end 20, sustains damage in first time etching process；
As shown in Figure 3 e, perform second time etching and remove remaining second packed layer 25 '；As it has been described above, when first fills out
The material filling layer 23 is silicon dioxide, when the material of the second packed layer 25 is polysilicon, it is preferred to use plasma etching,
The etching gas used is HBr, He and HeO2；Same, when using silicon nitride as above-mentioned barrier layer, also
Semiconductor base 20 can be stoped to sustain damage in second time etching process；
As illustrated in figure 3f, second time cmp is performed, to remove remaining first packed layer 23 '.Preferably
Embodiment in, when the material of the first packed layer 23 is silicon dioxide, and the material of the second packed layer 25 is polysilicon,
The material on the barrier layer that semiconductor base 20 surface is formed is preferably silicon nitride or silicon oxynitride, at second time chemical machinery
During grinding, barrier layer is as the stop-layer of second time cmp.
Comparison diagram 3f and Fig. 1 e of the existing reverse process of employing, finally utilizes and grinds residue the first packed layer 23 ' removed
Process be identical, therefore, use the application provide flattening method, also can make last second time chemistry machine
Tool process of lapping is affected by the least load effect, and, owing to eliminating the step forming patterning photoresist,
Thus reduce production cost.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. done, should be included in the scope of protection of the invention
Within.
Claims (6)
1. a flattening method, it is characterised in that including:
Thering is provided semiconductor base to be ground, described semiconductor base is formed with the first depression；
The first packed layer, described first packed layer is become to be filled up completely with in described semiconductor base overlying cap-shaped described first recessed
Fall into, and, described first packed layer is formed with the second depression of corresponding described first recessed position；
Depositing the second packed layer in described first packed layer surface, described second packed layer is filled up completely with described second depression,
And cover described first packed layer surface；
Perform cmp for the first time, to expose described first packed layer surface；
Perform etching for the first time, to remove the first packed layer exposed；
Perform second time etching and remove remaining second packed layer；
Perform second time cmp, to remove remaining first packed layer；
Wherein, the material of described first packed layer is different from the material of described second packed layer；Described second packed layer
Material selects in high cmp in described first time cmp relative to the material of the first packed layer
Ratio；The material of described second packed layer presents low quarter relative to the material of the first packed layer in described first time etches
Erosion selects ratio；The material of described second packed layer presents in described second time etches relative to the material of the first packed layer
High etching selection ratio.
Method the most according to claim 1, it is characterised in that described half in addition to described first sunk surface
Conductor substrate surface is formed with barrier layer.
Method the most according to claim 2, it is characterised in that the material of described first packed layer is silicon dioxide,
The material of described second packed layer is polysilicon.
Method the most according to claim 3, it is characterised in that etching of described first time uses plasma etching,
Etching gas includes C4F8, Ar, CO and O2。
Method the most according to claim 3, it is characterised in that described second time etching uses plasma etching,
Etching gas includes HBr, He and HeO2。
6. according to the method described in claim 4 or 5, it is characterised in that the material on described barrier layer be silicon nitride or
Silicon oxynitride.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510056936.0A CN105990130B (en) | 2015-02-04 | 2015-02-04 | Flattening method |
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| CN201510056936.0A CN105990130B (en) | 2015-02-04 | 2015-02-04 | Flattening method |
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| CN105990130B CN105990130B (en) | 2019-01-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106430080A (en) * | 2016-10-13 | 2017-02-22 | 重庆中科渝芯电子有限公司 | Production method for MEMS wide-groove and low-step structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970053449U (en) * | 1996-03-12 | 1997-10-13 | 김강철 | Airtight container |
| CN1681102A (en) * | 2004-04-07 | 2005-10-12 | 中芯国际集成电路制造(上海)有限公司 | Flattening method of insulating layer or interlayer medium layer in semiconductor device |
| CN101097882A (en) * | 2006-06-30 | 2008-01-02 | 上海华虹Nec电子有限公司 | Method for improving flatness in STI-CMP surface |
| CN102412140A (en) * | 2010-09-17 | 2012-04-11 | 台湾积体电路制造股份有限公司 | Non-uniformity reduction in semiconductor planarization |
-
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- 2015-02-04 CN CN201510056936.0A patent/CN105990130B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970053449U (en) * | 1996-03-12 | 1997-10-13 | 김강철 | Airtight container |
| CN1681102A (en) * | 2004-04-07 | 2005-10-12 | 中芯国际集成电路制造(上海)有限公司 | Flattening method of insulating layer or interlayer medium layer in semiconductor device |
| CN101097882A (en) * | 2006-06-30 | 2008-01-02 | 上海华虹Nec电子有限公司 | Method for improving flatness in STI-CMP surface |
| CN102412140A (en) * | 2010-09-17 | 2012-04-11 | 台湾积体电路制造股份有限公司 | Non-uniformity reduction in semiconductor planarization |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106430080A (en) * | 2016-10-13 | 2017-02-22 | 重庆中科渝芯电子有限公司 | Production method for MEMS wide-groove and low-step structure |
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