CN106663675A - 电力用半导体装置 - Google Patents

电力用半导体装置 Download PDF

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CN106663675A
CN106663675A CN201480080396.3A CN201480080396A CN106663675A CN 106663675 A CN106663675 A CN 106663675A CN 201480080396 A CN201480080396 A CN 201480080396A CN 106663675 A CN106663675 A CN 106663675A
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power semiconductor
semiconductor device
emitter
holding wire
thyristor
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CN106663675B (zh
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羽鸟宪司
北村周
北村周一
本宫哲男
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

目的在于提供一种能够对栅极信号的波形的振动进行抑制的技术。电力用半导体装置具有：功率半导体芯片(2g)；多个集电极主端子(4)及多个发射极主端子(5)，它们与功率半导体芯片(2g)电连接；以及信号线(8)。多个集电极主端子(4)及多个发射极主端子(5)具有从功率半导体芯片(2g)的配置面凸出的凸出部分，针对这些凸出部分，信号线(8)包围全部凸出部分的整周，且在俯视观察时与这些凸出部分分离。

Description

电力用半导体装置
技术领域
本发明涉及一种具有半导体开关元件的电力用半导体装置。
背景技术
具有半导体开关元件的电力用半导体装置(功率半导体装置)应用于逆变器、转换器等(例如专利文献1)。
专利文献1：日本特开2001－185679号公报
发明内容
对于电力用半导体装置，在刚切换为截止后，在栅极信号的波形中发生振动。该振动现象的发生机理尚不完全清楚，但由于上述的栅极信号的波形中的振动可能导致电力用半导体装置的误动作，因此要求抑制该振动现象。
因此，本发明就是鉴于上述问题而提出的，其目的在于提供一种能够抑制栅极信号的波形的振动的技术。
本发明所涉及的电力用半导体装置具有：半导体开关元件；多个集电极主端子及多个发射极主端子，它们与所述半导体开关元件电连接，具有从所述半导体开关元件的配置面凸出的凸出部分；以及信号线，针对所述多个集电极主端子的所述凸出部分、以及所述多个发射极主端子的所述凸出部分，所述信号线包围全部所述凸出部分的整周，且在俯视观察时与这些凸出部分分离。
发明的效果
根据本发明，能够抑制栅极信号的波形的振动。
通过以下的详细说明和附图，使得本发明的目的、特征、方式以及优点更清楚。
附图说明
图1是表示实施方式1所涉及的电力用半导体装置的结构的斜视图。
图2是示意性地表示实施方式1所涉及的电力用半导体装置的局部结构的剖面斜视图。
图3是示意性地表示实施方式1所涉及的电力用半导体装置的局部结构的剖面斜视图。
图4是表示相关半导体装置的结构的斜视图。
图5是表示相关半导体装置的各信号的波形的图。
图6是表示实施方式1所涉及的电力用半导体装置的各信号的波形的图。
图7是示意性地表示实施方式1的变形例所涉及的电力用半导体装置的局部结构的剖面斜视图。
图8是示意性地表示实施方式2所涉及的电力用半导体装置的局部结构的剖面斜视图。
具体实施方式
＜实施方式1＞
图1是表示本发明的实施方式1所涉及的电力用半导体装置的结构的斜视图，图2及图3是沿图1的A－A线及B－B线的剖面斜视图。此外，在图2及图3中，为了容易理解，省略了图1的电力用半导体装置的结构要素的一部分的图示，或者对图1的栅极信号电极3d及发射极信号电极3e的配置进行了变更。
本实施方式1所涉及的电力用半导体装置具有图1所示的散热用基座板1、多个芯片搭载基板2、多个信号电极部3、多个集电极主端子4、多个发射极主端子5、印刷基板6、图2所示的发射极导线7a、栅极信号导线7b、发射极信号导线7c和图3所示的信号线8。
多个芯片搭载基板2及多个信号电极部3配置于由金属构成的散热用基座板1的主面之上。
各芯片搭载基板2包含图2所示的焊料2a、金属电极2b、绝缘基板2c(例如陶瓷基板)、集电极电极2d、发射极电极2e、焊料2f以及功率半导体芯片2g。
焊料2a、金属电极2b及绝缘基板2c依次配置于散热用基座板1的主面之上。集电极电极2d及发射极电极2e配置于绝缘基板2c的主面之上。功率半导体芯片2g通过焊料2f而与集电极电极2d接合。
在本实施方式1中，功率半导体芯片2g例如由碳化硅(SiC)、氮化镓(GaN)或者金刚石等宽带隙半导体构成，搭载于未图示的半导体模块。并且，功率半导体芯片2g包含例如IGBT(Insulated Gate Bipolar Transistor)等未图示的半导体开关元件、和未图示的二极管。
各信号电极部3包含图2所示的焊料3a、金属电极3b、绝缘基板3c(例如陶瓷基板)、栅极信号电极3d以及发射极信号电极3e。
焊料3a、金属电极3b及绝缘基板3c依次配置于散热用基座板1的主面之上。栅极信号电极3d及发射极信号电极3e配置于绝缘基板3c的主面之上，并且具有从该配置面凸出而到达至印刷基板6的凸出部分。
功率半导体芯片2g经由发射极导线7a与发射极电极2e电连接，经由栅极信号导线7b与栅极信号电极3d电连接，经由发射极信号导线7c与发射极信号电极3e电连接。
各集电极主端子4经由集电极电极2d与功率半导体芯片2g(半导体开关元件)电连接，并且具有从功率半导体芯片2g(半导体开关元件)的配置面凸出的凸出部分。此外，在本实施方式1中，功率半导体芯片2g的配置面与绝缘基板2c的主面相对应。
各发射极主端子5经由发射极导线7a及发射极电极2e与功率半导体芯片2g(半导体开关元件)电连接，并且具有从功率半导体芯片2g(半导体开关元件)的配置面凸出的凸出部分。根据上述结构，集电极主端子4及发射极主端子5并联连接于功率半导体芯片2g。
集电极主端子4及发射极主端子5的数量是多个即可，不限于图1所示的各为3个。此外，对于1in1(在1个模块内有1个元件)的封装来说，大多采用下述构造，即，将2个集电极主端子4及2个发射极主端子5、或者3个集电极主端子4及3个发射极主端子5与半导体开关元件连接，使并联电流流过上述端子。
印刷基板6在功率半导体芯片2g的配置面上方与该配置面平行地配置，如图1及图3所示，设置有在俯视观察时具有四边形形状的多个孔6a。并且，在各孔6a中活动嵌合有1组集电极主端子4及发射极主端子5的凸出部分。根据上述结构，针对多个集电极主端子4的凸出部分、以及多个发射极主端子5的凸出部分，印刷基板6包围全部凸出部分的整周，且在俯视观察时与这些凸出部分分离。
如图3所示，信号线8包含栅极信号线8a及发射极信号线8b，该信号线8配线于印刷基板6。此外，在图3中，栅极信号线8a配线于印刷基板6的上表面，发射极信号线8b配线于印刷基板6的背面，但不限于此，例如也可以是，栅极信号线8a及发射极信号线8b这二者集中地配线于印刷基板6的上表面及背面中的任一者。
信号线8(栅极信号线8a及发射极信号线8b)与印刷基板6同样地，针对多个集电极主端子4的凸出部分、以及多个发射极主端子5的凸出部分，包围全部凸出部分的整周，且在俯视观察时与这些凸出部分分离。此外，关于信号线8(栅极信号线8a及发射极信号线8b)与多个集电极主端子4、多个发射极主端子5各自之间的距离(间隙)，是考虑到对电力用半导体装置要求的耐压及尺寸而决定的。例如，对于具有大于或等于3.3kV的耐压的电力用半导体装置，从避免封装件的极端的大型化的角度出发，优选该距离(间隙)设为3.0～30.0mm左右。此外，在该数值的计算中，将空气的绝缘耐压假定为3kV/mm。
栅极信号线8a经由栅极信号电极3d等与功率半导体芯片2g(半导体开关元件)电连接，发射极信号线8b经由发射极信号电极3e等与功率半导体芯片2g(半导体开关元件)电连接。
下面，在对以上述方式构成的本实施方式1所涉及的电力用半导体装置的效果进行说明之前，对与此相关的电力用半导体装置(以下记作“相关半导体装置”)进行说明。
图4是表示相关半导体装置的结构的斜视图。如图4所示，相关半导体装置构成为，在由虚线包围的区域，印刷基板6是开放的。因此，就相关半导体装置而言，针对多个集电极主端子4的凸出部分以及多个发射极主端子5的凸出部分，信号线8并未包围全部凸出部分的整周，这一点与实施方式1所涉及的电力用半导体装置不同。
然后，针对本实施方式1所涉及的电力用半导体装置及相关半导体装置，对刚切换为截止后的各信号的波形进行了调查。图5是表示相关半导体装置的各信号的波形的图，图6是表示本实施方式1所涉及的电力用半导体装置的各信号的波形的图。
＜效果＞
从图5及图6所示的结果可知，就相关半导体装置而言，在栅极信号的波形中发生了振动，但就本实施方式1所涉及的电力用半导体装置而言，能够在栅极信号的波形中抑制振动。因此，根据本实施方式1，能够实现可靠性高的电力用半导体装置。
特别地，对于由SiC等宽带隙半导体构成的器件来说，由于容易发现上述振动现象，因此上述效果是有效的。
另外，在本实施方式1中，由于信号线8(栅极信号线8a及发射极信号线8b)配线于印刷基板6，因此能够容易地进行信号线8的形成(配线)。
＜变形例＞
在实施方式1中，将集电极主端子4及发射极主端子5的凸出部分的整周包围的信号线8包含栅极信号线8a及发射极信号线8b这二者。但不限于此，该信号线8也可以包含栅极信号线8a及发射极信号线8b中的任一者。在图7中示出信号线8包含栅极信号线8a而不包含发射极信号线8b的结构。
即使根据上述本变形例的结构，也能够在一定程度上得到实施方式1的效果。但是，从提高对栅极信号的波形的振动进行抑制的效果的角度出发，优选如实施方式1那样，信号线8包含栅极信号线8a及发射极信号线8b这二者。
＜实施方式2＞
图8是示意性地表示本发明的实施方式2所涉及的电力用半导体装置的局部结构的剖面斜视图。此外，对于本实施方式2所涉及的电力用半导体装置，对与以上说明的结构要素相同或者相似的结构要素标注相同的参照标号，主要对不同的部分进行说明。
如图8所示，在本实施方式2中，作为接地电位的发射极信号线8b是由满铺图案(solid pattern)(将印刷基板6的一个主面全部实质性地覆盖)形成在印刷基板6的。由此，能够通过发射极信号线8b的屏蔽效果，抑制流过集电极主端子4及发射极主端子5的主电流对信号线8施加的电磁感应的影响。其结果，能够提高对栅极信号的波形的振动进行抑制的效果。另外，在本实施方式2中，由于栅极信号线8a也是由满铺图案形成的，因此同样能够提高对栅极信号的波形的振动进行抑制的效果。
并且，在本实施方式2中，栅极信号线8a及发射极信号线8b由彼此平行的平板构成，它们隔着印刷基板6而形成平行平板构造(多层配线构造)。由此，由于能够降低信号线8的电感，因此能够抑制流过集电极主端子4及发射极主端子5的主电流对信号线8施加的电磁感应的影响。其结果，能够进一步提高对栅极信号的波形的振动进行抑制的效果。
＜变形例＞
在实施方式2中，栅极信号线8a及发射极信号线8b这二者由满铺图案形成。但不限于此，也可以是栅极信号线8a及发射极信号线8b中的一方由满铺图案形成、另一方不由满铺图案形成的结构。
即使根据上述本变形例的结构，也能够在一定程度上得到实施方式2的效果。但是，从提高对栅极信号的波形的振动进行抑制的效果的角度出发，优选如实施方式2那样，栅极信号线8a及发射极信号线8b这二者由满铺图案形成。
另外，设想为对集电极主端子4施加与其他结构要素相比较高的电压。鉴于此，也可以对集电极主端子4涂敷具有绝缘性的树脂。根据上述结构，由于能够维持电力用半导体装置的耐压，并且缩短信号线8和集电极主端子4之间的距离(间隙)(例如设为小于3.0mm)，因此能够实现装置的小型化。
此外，本发明在其发明的范围内，能够对各实施方式及各变形例自由地进行组合，或者对各实施方式及各变形例适当地进行变形、省略。
另外，详细地说明了本发明，但上述说明的所有方案均为例示，本发明不限定于此。可以理解为在不脱离本发明的范围的情况下能够想到未例示出的无数的变形例。
标号的说明
2g功率半导体芯片，4集电极主端子，5发射极主端子，6印刷基板，8信号线，8a栅极信号线，8b发射极信号线。

Claims (7)

1.一种电力用半导体装置，其具有：
半导体开关元件；
多个集电极主端子及多个发射极主端子，它们与所述半导体开关元件电连接，具有从所述半导体开关元件的配置面凸出的凸出部分；以及
信号线，针对所述多个集电极主端子的所述凸出部分、以及所述多个发射极主端子的所述凸出部分，所述信号线包围全部所述凸出部分的整周，且在俯视观察时与这些凸出部分分离。
2.根据权利要求1所述的电力用半导体装置，其中，
所述信号线包含与所述半导体开关元件电连接的栅极信号线及发射极信号线中的至少一者。
3.根据权利要求2所述的电力用半导体装置，其中，
所述信号线包含所述栅极信号线及所述发射极信号线，
所述栅极信号线及所述发射极信号线由彼此平行的平板构成。
4.根据权利要求1至3中任一项所述的电力用半导体装置，其中，
还具有在所述配置面上方配置的印刷基板，
所述信号线配线于所述印刷基板。
5.根据权利要求1至3中任一项所述的电力用半导体装置，其中，
在所述集电极主端子涂敷有具有绝缘性的树脂。
6.根据权利要求2所述的电力用半导体装置，其中，
还具有在所述配置面上方配置的印刷基板，
所述栅极信号线及发射极信号线中的至少一者由满铺图案形成在所述印刷基板。
7.根据权利要求1至3中任一项所述的电力用半导体装置，其中，
所述半导体开关元件包含于半导体芯片，该半导体芯片搭载于半导体模块，由宽带隙半导体构成。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030173579A1 (en) * 2001-04-02 2003-09-18 Kazufumi Ishii Power semiconductor device
JP2009021345A (ja) * 2007-07-11 2009-01-29 Mitsubishi Electric Corp パワー半導体モジュール
JP2010041809A (ja) * 2008-08-04 2010-02-18 Hitachi Ltd 車両用電力変換装置、パワーモジュール用金属ベースおよびパワーモジュール

Family Cites Families (8)

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CN1146988C (zh) * 1997-12-08 2004-04-21 东芝株式会社 半导体功率器件的封装及其组装方法
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JP2013183022A (ja) * 2012-03-01 2013-09-12 Toyota Industries Corp 半導体装置および半導体装置の製造方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030173579A1 (en) * 2001-04-02 2003-09-18 Kazufumi Ishii Power semiconductor device
JP2009021345A (ja) * 2007-07-11 2009-01-29 Mitsubishi Electric Corp パワー半導体モジュール
JP2010041809A (ja) * 2008-08-04 2010-02-18 Hitachi Ltd 車両用電力変換装置、パワーモジュール用金属ベースおよびパワーモジュール

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