CN106653698B - 阵列基板及其制备方法、显示装置 - Google Patents
阵列基板及其制备方法、显示装置 Download PDFInfo
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Abstract
本发明提供一种阵列基板及其制备方法、显示装置,属于阵列基板技术领域,其可至少部分解决现有的阵列基板容易因为像素电极的偏移产生显示异常的问题。本发明的阵列基板制备方法包括依次形成公共电极线、第一绝缘层、像素电极、第二绝缘层的步骤,以及形成连通至所述公共电极线的过孔的步骤,且在形成所述过孔后还包括:通过构图工艺形成覆盖所述过孔的公共电极,该构图工艺包括对覆盖有所述公共电极的过孔的一部分进行刻蚀以形成隔离区;所述隔离区包括所述过孔的第一边缘内侧的区域,所述第一边缘为所述过孔与像素电极相邻或叠置的边缘,所述过孔还包括不与所述像素电极相邻也不与所述像素电极叠置的第二边缘。
Description
技术领域
本发明属于阵列基板技术领域,具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
对于HADS模式的液晶显示装置,像素电极2和公共电极12均设于阵列基板中。如图1、图2所示,公共电极线11与栅线3同层设置,并位于阵列基板的基底9上,其上覆盖栅绝缘层91(第一绝缘层);板状的像素电极2设于栅绝缘层91上,其上覆盖钝化层92(第二绝缘层);狭缝式的公共电极12设在钝化层92上,且需要通过栅绝缘层91和钝化层92中的过孔5与公共电极线11相连以获得信号。为避免公共电极12与像素电极2导通,以上过孔5设于相邻像素电极2之间的位置。
随着分辨率的提高,相邻像素电极2间的距离越来越小,过孔5和与其相邻的像素电极2间的距离也越来越小(如只有3微米)。而在实际制备工艺中,像素电极2的位置可能存在一定偏差,如图3、图4所示,若像素电极2偏移而与过孔5部分重叠,则会导致过孔5处有像素电极2暴露,像素电极2下方的栅绝缘层91也无法被除去;而在继续形成公共电极12时,则公共电极12会在过孔5中与像素电极2接触并导通,由此导致像素电极2接入公共电压,相应像素的显示异常。
发明内容
本发明至少部分解决现有的阵列基板容易因为像素电极的偏移产生显示异常的问题,提供一种可避免显示异常的阵列基板及其制备方法、显示装置。
解决本发明技术问题所采用的技术方案是一种阵列基板制备方法,包括依次形成公共电极线、第一绝缘层、像素电极、第二绝缘层的步骤,以及形成连通至所述公共电极线的过孔的步骤,且在形成所述过孔后还包括:
通过构图工艺形成覆盖所述过孔的公共电极,该构图工艺包括对覆盖有所述公共电极的过孔的一部分进行刻蚀以形成隔离区;所述隔离区包括所述过孔的第一边缘内侧的区域,所述第一边缘为所述过孔与像素电极相邻或叠置的边缘,所述过孔还包括不与所述像素电极相邻也不与所述像素电极叠置的第二边缘。
优选的是,所述过孔的部分位置设有所述像素电极。
优选的是,所述隔离区为沿所述过孔第一边缘内侧分布的条形区域。
优选的是,所述公共电极线包括条状的本体和设于本体一侧的凸出部,所述过孔连通至所述凸出部。
进一步优选的是,所述过孔覆盖所述凸出部。
进一步优选的是,所述凸出部远离所述本体的一侧的边缘与像素电极相邻或叠置;所述过孔的第一边缘对应所述凸出部的远离所述本体的一侧的边缘。
解决本发明技术问题所采用的技术方案是一种阵列基板,其包括基底和在远离基底的方向上依次设置的公共电极线、第一绝缘层、像素电极、第二绝缘层、公共电极;且
所述阵列基板还包括连通至所述公共电极线且被公共电极覆盖的过孔;
所述过孔的第一边缘与像素电极相邻或叠置,所述过孔还包括不与像素电极相邻也不与像素电极叠置的第二边缘;
所述公共电极在隔离区中设有开口,所述隔离区包括过孔的第一边缘内侧的区域。
优选的是,所述像素电极有一部分位于过孔内,所述像素电极在对应隔离区的位置设有沟槽,所述像素电极在过孔内的部分与过孔外的部分被所述沟槽隔开。
优选的是,所述隔离区为沿所述过孔第一边缘内侧分布的条形区域。
优选的是,所述公共电极线包括条状的本体和设于本体一侧的凸出部,所述过孔连通至所述凸出部。
解决本发明技术问题所采用的技术方案是一种显示装置,其包括以上所述的任意一种阵列基板。
本发明的阵列基板制备方法中,在形成公共电极时,要在过孔靠近像素电极的第一边缘内侧也刻蚀形成开口。当过孔与像素电极发生重叠时,则过孔第一边缘内侧有像素电极,由于像素电极与公共电极材料相同,故在刻蚀公共电极时会将开口处的像素电极也一起除去,从而将像素电极和公共电极连接的部分与像素电极的其它部分切断,由此避免真正起到显示作用的像素电极与公共电极导通,消除显示异常。
附图说明
图1为现有的一种阵列基板的俯视结构示意图;
图2为图1中沿AA’的剖面结构示意图;
图3为现有的一种阵列基板在像素电极发生偏移时的俯视结构示意图;
图4为图3中沿BB’的剖面结构示意图;
图5为本发明实施例的一种阵列基板的俯视结构示意图;
图6为图1中沿CC’的剖面结构示意图;
图7为本发明实施例的一种阵列基板在像素电极发生偏移时的俯视结构示意图;
图8为图7中沿DD’的剖面结构示意图;
图9为图7中过孔附近的公共电极的局部结构示意图;
图10为图7中过孔附近的像素电极的局部结构示意图;
其中,附图标记为:
11、公共电极线;12、公共电极;121、开口;2、像素电极;21、沟槽;3、栅线;4、隔离区;5、过孔;9、基底;91、栅绝缘层;92、钝化层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
在本发明中,两结构“同层设置”是指二者是由同一个材料层经构图工艺后形成的,故它们在层叠关系上处于相同层中,但并不代表它们与基底间的距离必然相等。
在本发明中,“光刻工艺”是构图工艺的一种具体形式,其是用完整的材料层形成特定的图形结构的工艺,具体包括形成材料层、涂布光刻胶、曝光、显影、刻蚀、光刻胶剥离等步骤中的一步或多步。
实施例1:
如图5至图10所示,本实施例提供一种阵列基板制备方法,包括依次形成公共电极线11、第一绝缘层(栅绝缘层91)、像素电极2、第二绝缘层(钝化层92)的步骤,以及形成连通至公共电极线11的过孔5的步骤,且在形成过孔5后还包括:
通过构图工艺形成覆盖过孔5的公共电极12,该构图工艺包括对覆盖有公共电极12的过孔5的一部分进行刻蚀以形成隔离区4;隔离区4包括过孔5的第一边缘内侧的区域,第一边缘为过孔5与像素电极2相邻或叠置的边缘,过孔5还包括不与像素电极2相邻也不与像素电极2叠置的第二边缘。
其中,过孔5一侧与像素电极2相邻,故过孔5该侧的边缘(第一边缘)可与像素电极2相邻;而当像素电极2偏移时,或者故意将像素电极2设计成与过孔5部分重叠时,该第一边缘会与像素电极2重叠,故过孔5第一边缘内侧的部分区域中会有像素电极2。同时,过孔5的另一侧与像素电极2之间设有栅线3等,故过孔5该侧的边缘(第二边缘)不与像素电极2相邻;且即使像素电极2偏移时,该第二边缘也不会与像素电极2重叠(因为像素电极2不会偏移很多)。也就是说,过孔5第二边缘内侧的部分区域是不会有像素电极2的。
本实施例的阵列基板制备方法中,在形成公共电极12(如刻蚀公共电极12中的狭缝)时,需要在过孔5靠近像素电极2的第一边缘内侧(隔离区4)也刻蚀形成开口121。当过孔5与像素电极2发生重叠时,过孔5第一边缘内侧(隔离区4)会有像素电极2,由于像素电极2与公共电极12材料相同,故在刻蚀公共电极12形成开口121时,会将开口121处(隔离区4)的像素电极2也一起除去,从而可将像素电极2和公共电极12连接的部分与像素电极2的其它部分切断,故真正起到显示作用的像素电极2不会与公共电极12连接,可避免显示异常。同时,由于过孔5还具有不与像素电极2相邻的第二边缘,故其第二边缘内侧是不会有像素电极2的,因此公共电极12仍可在第二边缘内侧与公共电极线11相连,公共电极信号的正常传输。
下面对本实施例的阵列基板制备方法进行详细介绍,其包括以下步骤:
S101、在基底9上,通过光刻工艺形成包括公共电极线11的图形。
也就是说,用金属等材料在玻璃等的基底9上形成公共电极线11。
其中,在形成公共电极线11的同时,还可一起形成栅极(图中未示出)和栅线3,即公共电极线11可与栅线3同层设置。
优选的,公共电极线11包括条状的本体和设于本体一侧的凸出部,后续形成的过孔5连通至该凸出部。
如图5所示,通常而言,为了扩大过孔5与公共电极线11的连接面积,可在公共电极线11中设置凸出部(如梯形的凸出部),而过孔5即可连接到该凸出部处。
当然,在形成公共电极线11之前,还可包括形成缓冲层(图中未示出)等的步骤,在此不再详细描述。
S102、在完成前述步骤的基底9上,形成第一绝缘层(即栅绝缘层91,以下以此为例)。
也就是说,用氧化硅、氮化硅等材料形成覆盖公共电极线11、栅线3、栅极的栅绝缘层91。
S103、在完成前述步骤的基底9上,通过光刻工艺形成包括有源区的图形。
也就是说,用半导体材料形成薄膜晶体管的有源区(图中未示出)。
S104、在完成前述步骤的基底9上,通过光刻工艺形成包括数据线、源极、漏极的图形。
也就是说,用金属等材料形成数据线、源极、漏极(图中均未示出),构成薄膜晶体管,其中数据线与源极相连,而源极和漏极均与有源区相连。
S105、在完成前述步骤的基底9上,通过光刻工艺形成包括像素电极2的图形。
也就是说,用氧化铟锡(ITO)等透明导电材料形成像素电极2,该像素电极2为块状,每个像素的像素电极2均与相应像素的薄膜晶体管的漏极连接,而不同像素的像素电极2间隔设置。
S106、在完成前述步骤的基底9上,通过光刻工艺形成第二绝缘层(即钝化层92,以下以此为例)。
也就是说,用氧化硅、氮化硅等材料形成覆盖像素电极2、数据线、源极、漏极、有源区的钝化层92。
S107、在完成前述步骤的基底9上,形成连通至公共电极线11的过孔5。其中,过孔5具有与像素电极2相邻或叠置的第一边缘,且还包括不与像素电极2相邻也不与像素电极2叠置的第二边缘。
也就是说,对公共电极线11特定位置(如凸出部)上方的栅绝缘层91和钝化层92进行刻蚀,以形成贯穿栅绝缘层91和钝化层92而连通至公共电极线11的过孔5,用于实现公共电极12与公共电极线11的连接。
优选的,过孔5的部分位置设有像素电极2。
也就是说,如图7、图8所示,当像素电极2发生偏移时,则过孔5会连接到像素电极2处,即过孔5中有部分位置是有像素电极2的。当然,由于过孔5只有第一边缘与像素电极2相邻,而第二边缘不与像素电极2相邻,故像素电极2即使偏移,最多也只会偏移到第一边缘内侧,而不会布满整个过孔5。
或者,也可以将像素电极2设计为延伸到过孔5第一边缘内侧,即故意让像素电极2的边缘部进入过孔5中(其效果和偏移后是一样的)。当然,此时同样要保证像素电极2不能布满整个过孔5。
优选的,过孔5连接至以上公共电极线11的凸出部。更优选的,过孔5覆盖凸出部。进一步优选的,凸出部远离本体的一侧的边缘与像素电极2相邻或叠置;过孔5的第一边缘对应凸出部的远离本体的一侧的边缘。
也就是说,如图5、图7所示,过孔5优选是连接至以上凸出部的;而由于根据本实施例的方法,即使像素电极2发生偏移,也可避免显示异常,故过孔5可设置的较大,完全覆盖以上的凸出部;更优选是,以上凸出部远离公共电极线11本体的一侧与过孔5的第一边缘正好重叠,即过孔5形状与凸出部形状相同。
S108、在完成前述步骤的基底9上,通过构图工艺(具体可为光刻工艺)形成公共电极12;且在该构图工艺中,包括对覆盖有公共电极12的过孔5的一部分进行刻蚀以形成隔离区4;其中,隔离区4包括过孔5的第一边缘内侧的区域。
也就是说,先形成氧化铟锡等的透明导电材料层;再进行涂布光刻胶、曝光、显影的步骤,将对应公共电极12狭缝处的光刻胶去除,使相应位置的透明导电材料层暴露;之后进行刻蚀,将暴露的透明导电材料层除去,形成具有狭缝的公共电极12;最后将光刻胶剥离。
与常规的形成公共电极12步骤不同,在以上的曝光、显影步骤中,还要将对应隔离区4位置的光刻胶也一起除去。这样,如图5、图6所示,在进行刻蚀的过程中,会对隔离区4的透明导电材料层也进行刻蚀,从而将该位置的公共电极12除去形成开口121。而如图7、图8所示,如果像素电极2发生偏移或者故意将像素电极2设计为与过孔5部分重叠,则过孔5的第一边缘内侧的区域会设有像素电极2,该位置的像素电极2上方连接公共电极5,因此在公共电极12中形成以上开口121时,会将其下方的像素电极2也一起除去,从而在像素电极2中形成沿第一边缘分布的“沟槽21”。
如图8、图9所示,公共电极12是覆盖过孔的,因此其中虽然形成以上开口121,但公共电极12与公共电极线11相连的部分(即公共电极12位于过孔5第二边缘内侧的部分)仍然与公共电极12的其它部分连为一体,公共电极线11的信号仍可传递到整个公共电极12中。
而如图8、图10所示,像素电极2仅与第一边缘重叠而未延伸到第二边缘处,因此,以上“沟槽21”能将像素电极2“分割”为两个互不相连的独立部分,其中一部分位于过孔5内并与公共电极12连接,而另一部分位于过孔5外,其不与公共电极5连接。由于真正用于产生驱动电压的像素电极2是位于过孔外的那部分,因此,以上沟槽21可避免公共电极12的信号传递到真正起到显示作用的像素电极2中,从而可避免显示异常。
优选的,隔离区4为沿过孔5第一边缘内侧分布的条形区域。
也就是说,隔离区4优选是一个设在过孔5的第一边缘内侧的长条状的区域,以起到形成以上开口121和沟槽21的作用。这样的隔离区4面积较小,可使过孔5内公共电极12与公共电极12的接触面积尽量较大,改善电连接状况。
当然,以上隔离区4也可为其它的形式,只要其包括过孔5第一边缘内侧的区域即可。例如,隔离区4也可为过孔5中靠近第一边缘的一半区域,这样该区域中的像素电极2可能不是被沟槽隔开,而是会被完全除去,而公共电极12则通过过孔5的另外一般区域与公共电极线11相连,这样同样能起到避免显示异常的作用。
其中,如果像素电极2发生偏移,或者故意将像素电极2设计成与过孔5部分重叠时,则过孔5中有像素电极2的位置下方的栅绝缘层91是不能被除去的,该位置的高度相对较高。这样,公共电极12与该位置的像素电极2相连时段差较小,可减小电阻,避免公共电极12发生断裂等。
本实施例还提供一种上述方法制备的阵列基板,其包括基底9和在远离基底9的方向上依次设置的公共电极线11、第一绝缘层(栅绝缘层91)、像素电极2、第二绝缘层(钝化层92)、公共电极12,其中,阵列基板还包括连通至公共电极线11且被公共电极12覆盖的过孔5;
过孔5的第一边缘与像素电极2相邻或叠置,过孔5还包括不与像素电极2相邻也不与像素电极2叠置的第二边缘;
公共电极12在隔离区4中设有开口121,隔离区4包括过孔5的第一边缘内侧的区域。
本实施例的阵列基板是通过上述方法制备的,其公共电极12在隔离区4中有开口121,故即使像素电极2发生偏移时,在阵列基板产品中公共电极12也不会与真正起到显示作用的像素电极2的导通。
优选的,像素电极2有一部分位于过孔5内,像素电极2在对应隔离区4的位置设有沟槽21,像素电极2在过孔5内的部分与过孔5外的部分被沟槽21隔开。
也就是说,如果像素电极2发生偏移,或者故意将像素电极2设计成与过孔5部分重叠时,像素电极2在隔离区4中可能形成沟槽21,沟槽21将过孔5内的像素电极2与过孔5外的像素电极2分开,防止公共电极12与真正起到显示作用的像素电极2的导通。
优选的,隔离区4为沿第一边缘内侧分布的条形区域。
优选的,公共电极线11包括条状的本体和设于本体一侧的凸出部,过孔5连通至凸出部。
如前所述,阵列基板中的隔离区4优选为条形区域;而公共电极线11也可设有以上的用于与过孔5连接的凸出部。
实施例2
本实施例提供一种显示装置,包括本发明任意一个实施例所述的阵列基板,其中,该显示装置可以为液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (11)
1.一种阵列基板制备方法,包括依次形成公共电极线、第一绝缘层、像素电极、第二绝缘层的步骤,以及形成连通至所述公共电极线的过孔的步骤,其特征在于,在形成所述过孔后还包括:
通过构图工艺形成覆盖所述过孔的公共电极,该构图工艺包括对覆盖有所述公共电极的过孔的一部分进行刻蚀以形成隔离区,所述隔离区的公共电极被除去形成开口;所述隔离区包括所述过孔的第一边缘内侧的区域,所述第一边缘为所述过孔与像素电极相邻或叠置的边缘,所述过孔还包括不与所述像素电极相邻也不与所述像素电极叠置的第二边缘;
若所述过孔第一边缘内侧的部分区域中存在像素电极,则在形成隔离区时所述隔离区中的像素电极被除去,以使所述像素电极和公共电极连接的部分与像素电极的其它部分切断。
2.根据权利要求1所述的阵列基板制备方法,其特征在于,
所述过孔的部分位置设有所述像素电极。
3.根据权利要求1所述的阵列基板制备方法,其特征在于,
所述隔离区为沿所述过孔第一边缘内侧分布的条形区域。
4.根据权利要求1所述的阵列基板制备方法,其特征在于,
所述公共电极线包括条状的本体和设于本体一侧的凸出部,所述过孔连通至所述凸出部。
5.根据权利要求4所述的阵列基板制备方法,其特征在于,
所述过孔覆盖所述凸出部。
6.根据权利要求5所述的阵列基板制备方法,其特征在于,
所述凸出部远离所述本体的一侧的边缘与像素电极相邻或叠置;
所述过孔的第一边缘对应所述凸出部的远离所述本体的一侧的边缘。
7.一种阵列基板,包括基底和在远离基底的方向上依次设置的公共电极线、第一绝缘层、像素电极、第二绝缘层、公共电极,其特征在于,
所述阵列基板还包括连通至所述公共电极线且被公共电极覆盖的过孔;
所述过孔的第一边缘与像素电极相邻或叠置,所述过孔还包括不与像素电极相邻也不与像素电极叠置的第二边缘;
所述公共电极在隔离区中设有开口,所述隔离区包括过孔的第一边缘内侧的区域;
当所述过孔与所述像素电极叠置时,所述像素电极在对应所述隔离区的位置设有沟槽,以使所述像素电极和公共电极连接的部分与像素电极的其它部分切断。
8.根据权利要求7所述的阵列基板,其特征在于,
所述像素电极有一部分位于过孔内,所述像素电极在对应隔离区的位置设有沟槽,所述像素电极在过孔内的部分与过孔外的部分被所述沟槽隔开。
9.根据权利要求7所述的阵列基板,其特征在于,
所述隔离区为沿所述过孔第一边缘内侧分布的条形区域。
10.根据权利要求7所述的阵列基板,其特征在于,
所述公共电极线包括条状的本体和设于本体一侧的凸出部,所述过孔连通至所述凸出部。
11.一种显示装置,其特征在于,包括:
权利要求7至10中任意一项所述的阵列基板。
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