CN106611782A - 一种降低FinFET寄生电阻的方法 - Google Patents

一种降低FinFET寄生电阻的方法 Download PDF

Info

Publication number
CN106611782A
CN106611782A CN201611230454.3A CN201611230454A CN106611782A CN 106611782 A CN106611782 A CN 106611782A CN 201611230454 A CN201611230454 A CN 201611230454A CN 106611782 A CN106611782 A CN 106611782A
Authority
CN
China
Prior art keywords
finfet
source
preparation
layer
shaped contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611230454.3A
Other languages
English (en)
Other versions
CN106611782B (zh
Inventor
郭奥
刘林林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Chengdu Image Design Technology Co Ltd
Original Assignee
Shanghai Integrated Circuit Research and Development Center Co Ltd
Chengdu Image Design Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Integrated Circuit Research and Development Center Co Ltd, Chengdu Image Design Technology Co Ltd filed Critical Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority to CN201611230454.3A priority Critical patent/CN106611782B/zh
Publication of CN106611782A publication Critical patent/CN106611782A/zh
Priority to US16/465,575 priority patent/US20190296011A1/en
Priority to PCT/CN2017/087281 priority patent/WO2018120651A1/zh
Application granted granted Critical
Publication of CN106611782B publication Critical patent/CN106611782B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/158—Carbon nanotubes
    • C01B32/16—Preparation
    • C01B32/162—Preparation characterised by catalysts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B2202/00—Structure or properties of carbon nanotubes
    • C01B2202/02—Single-walled nanotubes
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B2202/00—Structure or properties of carbon nanotubes
    • C01B2202/06—Multi-walled nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种降低FinFET寄生电阻的器件结构及其制备方法，该方法包括：制备常规FinFET器件结构，包括制备FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构和定义FinFET器件的源漏区域的分步骤；其中，常规FinFET器件结构包括由金属栅电极和栅介质层组成的栅叠结构分别从侧面和表面包裹FinFET硅鳍结构，形成MOSFET的三维沟道；在源漏区域制备催化剂层；生长碳纳米管，形成条形接触孔层M0；其中，条形接触孔层M0的下端覆盖并连接FinFET器件的源漏区域；碳纳米管包括单壁和多壁碳纳米管材料；实现FinFET器件的源漏引出及后道工艺制备，即使条形接触孔层M0的上端与金属层M1相连。

Description

一种降低FinFET寄生电阻的方法
技术领域
本发明涉及集成电路制造领域的半导体产品制作工艺，尤其涉及一种降低鳍式场效应晶体管(Fin Field-Effect Transistor，简称FinFET)寄生电阻的方法。
背景技术
随着半导体工艺技术节点的不断缩小，传统的平面金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)遇到了越来越多的技术挑战。
FinFET作为一种新型的三维器件结构，可以极大地提升MOSFET的器件特性，这些器件特性可以包括抑制短沟效应(SCE)、减小器件漏电、提高驱动电流以及提升亚阈值特性等等。
目前，国际上领先的半导体代工厂都已经在16/14nm工艺节点中量产了FinFET技术。请参阅图1，图1所示为现有技术中FinFET器件结构的典型示意图；其中，由金属栅电极和栅介质层组成的栅叠结构(Gate Stack)分别从侧面和表面包裹硅鳍结构(Si Fin)，形成MOSFET的三维沟道，由于Si Fin的宽度很小，源漏电极通常通过条形接触孔层M0进行引出，并进一步通过接触孔层V0连接金属层M1，进而完成传统的后道互连相关工艺。
从图1可以看出，虽然FinFET技术为MOS器件尺寸的进一步缩小提供了便利，但其三维器件结构所引起的寄生电阻和寄生电容相比平面MOS器件也更为严重，尤其是随着FinFET器件尺寸进一步缩小至7nm工艺代，FinFET器件的寄生电阻和寄生电容将会成为影响FinFET器件性能的决定性因素，这将给FinFET器件性能的进一步提升带来巨大挑战。
请参阅图2，图2所示为FinFET器件典型的寄生电阻示意图。如图所示，寄生电阻主要包括源漏区域的寄生电阻R_SD、源漏与沟道之间Si Fin扩展区域的电阻R_extension以及源漏区域通过源漏金属层M0引出时接触电阻R_contact。
请参阅图3，图3所示为各工艺节点的FinFET器件寄生电阻的仿真结果示意图。如图所示，随着FinFET器件尺寸的不断缩小，寄生电阻R_SD和寄生(Parasitic)电阻R_extension变化不大，但是，接触电阻R_contact则显著增加。
因此，降低条形接触孔层M0引出时的接触电阻R_contact已成为改善FinFET寄生电阻、提升器件性能的主要努力方向，也是FinFET技术路线进一步按比例缩小亟需解决的关键难题。
在目前主流的FinFET技术中，对条形接触孔层M0通常采用金属钨来进行填充，本领域技术人员正在尝试通过各种途径降低条形接触孔层M0与源漏区域的接触电阻R_contact，以便应用于更先进的FinFET工艺中。例如，这些技术主要包括利用界面工程调控金属-半导体接触的肖特基势垒、对源漏区域进行硅化物处理、以及采用更低电阻率的金属进行条形接触孔层M0的填充等。
发明内容
针对现有技术存在的不足，本发明也提出了一种降低FinFET寄生电阻的方法，该方法通过采用碳纳米管(CNT)作为导电材料制备FinFET器件的条形接触孔M0，即利用碳纳米管优异的导电特性实现降低FinFET器件寄生电阻的目的。
为实现上述目的，本发明的技术方案如下：
一种降低FinFET寄生电阻的器件结构，其包括：FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构、用于源漏引出的条形接触孔层M0以及用于后道互连工艺的金属层M1；其中，所述栅叠结构分别从两个侧面和表面包裹所述FinFET硅鳍结构，形成FinFET器件的三维沟道，所述条形接触孔层M0的下端覆盖并连接FinFET器件的源漏区域，上端与所述金属层M1相连，以实现FinFET器件的源漏引出；所述条形接触孔层M0采用单壁或多壁碳纳米管材料。
优选地，所述FinFET硅鳍结构通过浅沟槽隔离介质STI进行隔离，所述栅叠结构由金属栅电极和高k栅介质组成，所述金属层M1为铜互连导线。
为实现上述目的，本发明还提供一种技术方案如下：
一种采用上述降低FinFET寄生电阻的器件结构的制备方法，其包括：
步骤S1：制备常规FinFET器件结构，包括制备FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构和定义FinFET器件的源漏区域的分步骤；其中，所述常规FinFET器件结构包括由金属栅电极和栅介质层组成的栅叠结构分别从侧面和表面包裹FinFET硅鳍结构，形成MOSFET的三维沟道；
步骤S2：在所述源漏区域制备催化剂层；
步骤S3：生长碳纳米管，形成条形接触孔层M0；其中，所述条形接触孔层M0的下端覆盖并连接所述FinFET器件的源漏区域；所述碳纳米管包括单壁和多壁碳纳米管材料；
步骤S4：实现FinFET器件的源漏引出及后道工艺制备，即使所述条形接触孔层M0的上端与所述金属层M1相连。
优选地，所述制备常规FinFET器件结构方法包含一系列光刻、刻蚀、氧化、淀积和/或外延工艺步骤的组合。
优选地，所述步骤S2具体包括如下步骤：
步骤S21：通过光刻和刻蚀工艺定义出所述条形接触孔层M0；
步骤S22：利用原子层淀积技术在所述条形接触孔层M0中和表面淀积催化剂层；
步骤S23：通过退火工艺使所述催化剂层颗粒化。
优选地，所述催化剂材料为铁Fe、钴Co或镍Ni。
优选地，所述生长碳纳米管的方法为化学气相淀积法。
优选地，所述步骤S4中实现FinFET器件的源漏引出及后道工艺制备金属引出采用传统CMOS后道互连制备工艺。
从上述技术方案可以看出，本发明所提出的降低FinFET寄生电阻的器件结构，其采用碳纳米管作为导电材料填充FinFET条形接触孔层M0的，可以得到如下有益效果：
①、由于碳纳米管具有优良的导电特性，能够承载的电流密度比目前主流的铜导线仍可高出2-3个数量级，是理想的金属互连材料。因此，本发明可大大降低FinFET器件的寄生电阻。
②、由于碳纳米管作为金属互连材料已经可以在传统的CMOS后道互连工艺中予以实现。因此，本发明所提出的降低FinFET寄生电阻的制备方法不仅易于实施，且与传统的CMOS工艺保持较好的工艺兼容性，具有非常重要的应用价值。
附图说明
图1所示为现有技术中FinFET器件结构的典型示意图
图2所示为FinFET器件典型的寄生电阻示意图
图3所示为各工艺节点的FinFET器件寄生电阻的仿真结果示意图
图4所示为本发明一实施例中的所提出的降低FinFET寄生电阻的器件结构的示意图；
图5为本发明所提出的降低FinFET寄生电阻的器件制备方法流程示意图
图6为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S1后的产品剖面示意图
图7为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S2后的产品剖面示意图
图8为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S3后的产品剖面示意图
图9为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S4后的产品剖面示意图
具体实施方式
下面结合附图对本发明的具体实施方式进行详细的说明。应理解的是本发明能够在不同的示例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上当做说明之用，而非用以限制本发明。
请参阅图4，图4所示为本发明一实施例中的所提出的降低FinFET寄生电阻的器件结构的示意图。如图所示，在本发明的实施例中，该降低FinFET寄生电阻的器件结构包括：FinFET硅鳍结构(Si Fin)、由栅电极和栅介质层组成的栅叠结构(Gate Stack)、用于源漏引出的条形接触孔层M0以及用于后道互连工艺的金属层M1；其中，栅叠结构分别从两个侧面和表面包裹FinFET硅鳍结构，形成FinFET器件的三维沟道，条形接触孔层M0的下端覆盖并连接FinFET器件的源漏区域，上端与所述金属层M1相连，以实现FinFET器件的源漏引出。
在本发明的实施例中，条形接触孔层M0可以采用单壁或多壁碳纳米管材料。也就是说，本发明通过采用碳纳米管(CNT)作为导电材料制备FinFET器件的条形接触孔M0，即利用纳米管替代现有技术中的金属钨接触孔，从而充分发挥了碳纳米管作为一维理想导线的优异导电特性，以实现降低FinFET器件寄生电阻的目的。
如图4所示，硅鳍结构、栅叠结构和金属层M1可以采用目前主流FinFET工艺技术中的器件结构和材料，例如，硅鳍结构通常可以采用浅沟槽隔离介质(STI)进行隔离，栅叠结构通常可以由金属栅电极和高k栅介质组成，金属层M1通常可以为铜互连导线。
接下来，请参考图5，图5所示为本发明一实施例中的所提出的降低FinFET寄生电阻的器件结构的示意图。需要说明的是，图9和图4是相同的图，并且请结合图4中的标示文字参看图5、图6、图7、图8和图9中所对应的图形。如图5所示，本发明所提出的降低FinFET寄生电阻的器件制备方法大致包含以下步骤：
步骤S1：制备常规FinFET器件结构，包括制备FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构和定义FinFET器件的源漏区域的分步骤；其中，常规FinFET器件结构包括由金属栅电极和栅介质层组成的栅叠结构分别从侧面和表面包裹FinFET硅鳍结构，形成MOSFET的三维沟道。
具体地，在本发明的实施例中，制备常规FinFET器件结构的制备工艺可以采用目前主流的FinFET工艺技术；例如，包含一系列光刻、刻蚀、氧化、淀积、外延等工艺步骤的组合。
上述工艺步骤和细节为本领域的一般技术人员所熟知，在此不作赘述，制备完常规FinFET器件结构的器件示意图如图6所示。需要说明的是，通常栅电极周围及器件结构表面会覆盖各种隔离介质材料，这里为图示方便，略去各种隔离介质材料(下同)。
步骤S2：在源漏区域制备催化剂层；具体地，步骤S2具体包括：
步骤S21：通过光刻和刻蚀工艺定义出所述条形接触孔层M0；
步骤S22：利用原子层淀积技术在所述条形接触孔层M0中和表面淀积催化剂层；其中，催化剂材料可以为铁Fe、钴Co或镍Ni等等常用于碳纳米管生长的催化剂材料；
步骤S23：通过退火工艺使催化剂层颗粒化。
请参阅图7，图7为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S2后的形成条形接触孔层M0器件结构示意图。
步骤S3：生长碳纳米管，形成条形接触孔层M0；其中，条形接触孔层M0的下端覆盖并连接所述FinFET器件的源漏区域；碳纳米管包括单壁和多壁碳纳米管材料。
具体地，请参阅图8，图8为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S3生长碳纳米管后结构示意图。碳纳米管的生长方法通常采用化学气相淀积法(CVD)，根据具体生长工艺条件的不同，所生长的碳纳米管可以是单壁和多壁碳纳米管材料。
步骤S4：实现FinFET器件的源漏引出及后道工艺制备，即使所述条形接触孔层M0的上端与所述金属层M1相连。
具体地，制备工艺采用传统CMOS后道互连工艺即可，在此不作赘述，请参阅图9，图9为本发明一实施例中采用的降低FinFET寄生电阻的器件制备方法完成步骤S9后的器件结构示意图。
综上所述，本发明所提出的降低FinFET寄生电阻的方法，采用碳纳米管作为M0的填充材料替代传统FinFET器件结构中金属钨，充分发挥碳纳米管作为一维理想导线的优势，从而实现降低FinFET寄生电阻的目的。同时由于碳纳米管作为金属互连材料已经可以在传统的CMOS后道互连工艺中予以实现，因而本发明所提出的降低FinFET寄生电阻的制备方法不仅易于实施，而且与传统的CMOS工艺保持较好的工艺兼容性，具有非常重要的应用价值。
以上的仅为本发明的实施例，实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

1.一种降低FinFET寄生电阻的器件结构，其特征在于，包括：FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构、用于源漏引出的条形接触孔层M0以及用于后道互连工艺的金属层M1；
其中，所述栅叠结构分别从两个侧面和表面包裹所述FinFET硅鳍结构，形成FinFET器件的三维沟道，所述条形接触孔层M0的下端覆盖并连接FinFET器件的源漏区域，上端与所述金属层M1相连，以实现FinFET器件的源漏引出；所述条形接触孔层M0采用单壁或多壁碳纳米管材料。
2.根据权利要求1所述的降低FinFET寄生电阻的器件结构，其特征在于，所述FinFET硅鳍结构通过浅沟槽隔离介质STI进行隔离。
3.根据权利要求1所述的降低FinFET寄生电阻的器件结构，其特征在于，所述栅叠结构由金属栅电极和高k栅介质组成。
4.根据权利要求1所述的降低FinFET寄生电阻的器件结构，其特征在于，所述金属层M1为铜互连导线。
5.一种采用权利要求1所述降低FinFET寄生电阻的器件结构的制备方法，其特征在于，包括
步骤S1：制备常规FinFET器件结构，包括制备FinFET硅鳍结构、由栅电极和栅介质层组成的栅叠结构和定义FinFET器件的源漏区域的分步骤；其中，所述常规FinFET器件结构包括由金属栅电极和栅介质层组成的栅叠结构分别从侧面和表面包裹FinFET硅鳍结构，形成MOSFET的三维沟道；
步骤S2：在所述源漏区域制备催化剂层；
步骤S3：生长碳纳米管，形成条形接触孔层M0；其中，所述条形接触孔层M0的下端覆盖并连接所述FinFET器件的源漏区域；所述碳纳米管包括单壁和多壁碳纳米管材料；
步骤S4：实现FinFET器件的源漏引出及后道工艺制备，即使所述条形接触孔层M0的上端与所述金属层M1相连。
6.根据权利要求5所述的制备方法，其特征在于，所述制备常规FinFET器件结构方法包含一系列光刻、刻蚀、氧化、淀积和/或外延工艺步骤的组合。
7.根据权利要求5所述的制备方法，其特征在于，所述步骤S2具体包括如下步骤：
步骤S21：通过光刻和刻蚀工艺定义出所述条形接触孔层M0；
步骤S22：利用原子层淀积技术在所述条形接触孔层M0中和表面淀积催化剂层；
步骤S23：通过退火工艺使所述催化剂层颗粒化。
8.根据权利要求3所述的制备方法，其特征在于，所述催化剂材料为铁Fe、钴Co或镍Ni。
9.根据权利要求3所述的制备方法，其特征在于，所述生长碳纳米管的方法为化学气相淀积法。
10.根据权利要求3所述的制备方法，其特征在于，所述步骤S4中实现FinFET器件的源漏引出及后道工艺制备金属引出采用传统CMOS后道互连制备工艺。
CN201611230454.3A 2016-12-27 2016-12-27 一种降低FinFET寄生电阻的方法 Active CN106611782B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201611230454.3A CN106611782B (zh) 2016-12-27 2016-12-27 一种降低FinFET寄生电阻的方法
US16/465,575 US20190296011A1 (en) 2016-12-27 2017-06-06 Means for reducing finfet parasitic resistance
PCT/CN2017/087281 WO2018120651A1 (zh) 2016-12-27 2017-06-06 一种降低FinFET寄生电阻的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611230454.3A CN106611782B (zh) 2016-12-27 2016-12-27 一种降低FinFET寄生电阻的方法

Publications (2)

Publication Number Publication Date
CN106611782A true CN106611782A (zh) 2017-05-03
CN106611782B CN106611782B (zh) 2020-10-02

Family

ID=58636402

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611230454.3A Active CN106611782B (zh) 2016-12-27 2016-12-27 一种降低FinFET寄生电阻的方法

Country Status (3)

Country Link
US (1) US20190296011A1 (zh)
CN (1) CN106611782B (zh)
WO (1) WO2018120651A1 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107679262A (zh) * 2017-08-11 2018-02-09 上海集成电路研发中心有限公司 一种mos器件衬底外围寄生电阻的建模方法
WO2018120651A1 (zh) * 2016-12-27 2018-07-05 上海集成电路研发中心有限公司 一种降低FinFET寄生电阻的方法
CN108305901A (zh) * 2018-02-12 2018-07-20 上海集成电路研发中心有限公司 一种FinFET器件及其制备方法
CN108563801A (zh) * 2017-12-21 2018-09-21 上海集成电路研发中心有限公司 一种提取FinFET寄生电阻模型的测试结构和方法
WO2018236560A1 (en) * 2017-06-21 2018-12-27 Qualcomm Incorporated ARRANGEMENT TECHNIQUE FOR CENTRAL END OF LINE
CN113517349A (zh) * 2021-07-15 2021-10-19 广东省大湾区集成电路与系统应用研究院 鳍式场效应晶体管源漏寄生电阻分解结构及测试结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10978351B2 (en) * 2017-11-17 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Etch stop layer between substrate and isolation structure
CN112838050A (zh) * 2021-02-05 2021-05-25 泉芯集成电路制造(济南)有限公司 一种半导体器件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376686A (zh) * 2010-08-11 2012-03-14 中国科学院微电子研究所 一种半导体器件及其制造方法
CN103383964A (zh) * 2012-05-03 2013-11-06 台湾积体电路制造股份有限公司 用于FinFET的结构
US20140051217A1 (en) * 2011-04-18 2014-02-20 International Business Machines Corporation GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES
CN105206561A (zh) * 2014-05-28 2015-12-30 中芯国际集成电路制造(上海)有限公司 互连结构的形成方法和半导体结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4167212B2 (ja) * 2004-10-05 2008-10-15 富士通株式会社 カーボンナノチューブ構造体、半導体装置、および半導体パッケージ
US20070023839A1 (en) * 2005-07-27 2007-02-01 International Business Machines Corporation Finfet gate formed of carbon nanotubes
CN102044524B (zh) * 2009-10-13 2016-03-16 中芯国际集成电路制造(上海)有限公司 互连结构及其形成方法
CN106611782B (zh) * 2016-12-27 2020-10-02 上海集成电路研发中心有限公司 一种降低FinFET寄生电阻的方法
US10374083B1 (en) * 2018-01-17 2019-08-06 International Business Machines Corporation Vertical fin field effect transistor with reduced gate length variations

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376686A (zh) * 2010-08-11 2012-03-14 中国科学院微电子研究所 一种半导体器件及其制造方法
US20140051217A1 (en) * 2011-04-18 2014-02-20 International Business Machines Corporation GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SiC FINS OR NANOWIRE TEMPLATES
CN103383964A (zh) * 2012-05-03 2013-11-06 台湾积体电路制造股份有限公司 用于FinFET的结构
CN105206561A (zh) * 2014-05-28 2015-12-30 中芯国际集成电路制造(上海)有限公司 互连结构的形成方法和半导体结构

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018120651A1 (zh) * 2016-12-27 2018-07-05 上海集成电路研发中心有限公司 一种降低FinFET寄生电阻的方法
WO2018236560A1 (en) * 2017-06-21 2018-12-27 Qualcomm Incorporated ARRANGEMENT TECHNIQUE FOR CENTRAL END OF LINE
US10325845B2 (en) 2017-06-21 2019-06-18 Qualcomm Incorporated Layout technique for middle-end-of-line
US10410965B2 (en) 2017-06-21 2019-09-10 Qualcomm Incorporated Layout technique for middle-end-of-line
CN107679262A (zh) * 2017-08-11 2018-02-09 上海集成电路研发中心有限公司 一种mos器件衬底外围寄生电阻的建模方法
CN107679262B (zh) * 2017-08-11 2021-03-26 上海集成电路研发中心有限公司 一种mos器件衬底外围寄生电阻的建模方法
CN108563801A (zh) * 2017-12-21 2018-09-21 上海集成电路研发中心有限公司 一种提取FinFET寄生电阻模型的测试结构和方法
CN108563801B (zh) * 2017-12-21 2022-01-04 上海集成电路研发中心有限公司 一种提取FinFET寄生电阻模型的测试结构和方法
CN108305901A (zh) * 2018-02-12 2018-07-20 上海集成电路研发中心有限公司 一种FinFET器件及其制备方法
WO2019153724A1 (zh) * 2018-02-12 2019-08-15 上海集成电路研发中心有限公司 一种FinFET器件及其制备方法
CN113517349A (zh) * 2021-07-15 2021-10-19 广东省大湾区集成电路与系统应用研究院 鳍式场效应晶体管源漏寄生电阻分解结构及测试结构

Also Published As

Publication number Publication date
CN106611782B (zh) 2020-10-02
WO2018120651A1 (zh) 2018-07-05
US20190296011A1 (en) 2019-09-26

Similar Documents

Publication Publication Date Title
CN106611782A (zh) 一种降低FinFET寄生电阻的方法
CN103563085B (zh) 垂直隧穿负微分电阻器件
US9911829B2 (en) FinFET with bottom SiGe layer in source/drain
CN104701376B (zh) 替换栅极纳米线器件
CN100428471C (zh) 混合半导体结构及其制造方法
US20170053982A1 (en) Series resistance reduction in vertically stacked silicon nanowire transistors
JP6013777B2 (ja) ライントンネリングトンネル電界効果トランジスタ（ｔｆｅｔ）及びその製造方法
CN108122774A (zh) 用于全环栅半导体结构的阈值电压调整
CN108172549B (zh) 一种堆叠式围栅纳米线cmos场效应管结构及制作方法
CN105895694A (zh) 堆叠的全环栅FinFET及其形成方法
CN104009071B (zh) 半导体装置
Berg et al. Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
CN104347408B (zh) 半导体装置及其制造方法
CN107039514A (zh) Iii‑v族纳米线隧穿fet的方法及结构
CN106684151A (zh) 一种GaN侧墙绝缘栅鳍式高电子迁移率晶体管及其制造方法
CN103094347B (zh) 一种双材料欠叠异质栅结构的碳纳米管场效应管
CN108155101A (zh) 一种堆叠纳米线及其制造方法
CN104392917B (zh) 一种全包围栅结构的形成方法
CN105870062B (zh) 高质量纳米线cmos器件及其制造方法及包括其的电子设备
US9978836B1 (en) Nanostructure field-effect transistors with enhanced mobility source/drain regions
WO2019153724A1 (zh) 一种FinFET器件及其制备方法
CN104269407A (zh) 一种非易失性高密度三维半导体存储器件及其制备方法
US10707148B2 (en) Elbow contact for field-effect transistor and manufacture thereof
CN107424994A (zh) 环栅iii-v量子阱晶体管及锗无结晶体管及其制造方法
CN204130534U (zh) 一种非易失性高密度三维半导体存储器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant